WO2017168756A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2017168756A1
WO2017168756A1 PCT/JP2016/060953 JP2016060953W WO2017168756A1 WO 2017168756 A1 WO2017168756 A1 WO 2017168756A1 JP 2016060953 W JP2016060953 W JP 2016060953W WO 2017168756 A1 WO2017168756 A1 WO 2017168756A1
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WIPO (PCT)
Prior art keywords
substrate
conductor substrate
terminal
conductor
semiconductor element
Prior art date
Application number
PCT/JP2016/060953
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English (en)
French (fr)
Inventor
洋輔 中田
達也 川瀬
三紀夫 石原
宮本　昇
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201690001618.2U priority Critical patent/CN209150089U/zh
Priority to PCT/JP2016/060953 priority patent/WO2017168756A1/ja
Priority to JP2018508340A priority patent/JP6849660B2/ja
Priority to US16/080,029 priority patent/US10825751B2/en
Publication of WO2017168756A1 publication Critical patent/WO2017168756A1/ja

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    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10272—Silicon Carbide [SiC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a power semiconductor device for improving cooling efficiency.
  • a mechanism for dissipating heat generated by the power semiconductor device from only one side such as the lowermost surface thereof is disclosed in, for example, JP-A-2015-115471.
  • Patent Document 1 a mechanism for dissipating heat generated by the power semiconductor device from only one side such as the lowermost surface thereof is disclosed in, for example, JP-A-2015-115471.
  • Patent Document 2 another semiconductor device for power which improves the heat radiation is disclosed, for example, in Japanese Patent Laid-Open No. 2003-258166 (Patent Document 2).
  • a cooler such as a heat sink is joined to the lowermost surface side of the semiconductor device, and heat can be dissipated from below.
  • the heat conducted upward is basically more difficult to dissipate to the outside than the heat conducted downward, and it is desirable to efficiently dissipate the heat conducted upward.
  • the upper surfaces of both of the two power semiconductor devices having large amounts of heat generation are connected to the metal plate. Therefore, in Japanese Unexamined Patent Publication No. 2015-115471, the metal plate connected above the semiconductor element receives large heat generation from the two power semiconductor elements.
  • semiconductor elements generally have larger thermal resistance than conductor materials and the like. Therefore, it is considered that the heat dissipation to the outside of the device through the metal plate is not sufficient because of the problem of heat capacity. That is, it is considered that the semiconductor device disclosed in JP-A-2015-115471 does not have sufficient heat dissipation as a whole.
  • the present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device capable of being easily attached to a cooler while obtaining uniform heat dissipation.
  • the semiconductor device of the present invention comprises a substrate material, a semiconductor element, and a terminal.
  • the substrate material includes an insulating substrate, first and second conductive substrates spaced from each other on one main surface of the insulating substrate, and the other main surface opposite to the one main surface of the insulating substrate. And a third conductive substrate disposed on the upper side.
  • the semiconductor element is connected to the side opposite to the insulating substrate of the first conductor substrate.
  • the terminal is connected to the side opposite to the first conductor substrate of the semiconductor element.
  • the terminal extends from the region on the semiconductor element to the region on the second conductor substrate and is connected to the second conductor substrate. At least a part of the substrate material, the semiconductor element, and the terminal is sealed with a resin.
  • the third conductor substrate is exposed from the resin.
  • the terminal since the terminal is connected to extend from the upper surface side of the semiconductor element to the second conductor substrate disposed on the lower surface side of the semiconductor element, the heat dissipation from the upper surface side to the lower surface side of the semiconductor element Can be enhanced.
  • the third conductor substrate on the other main surface of the substrate enhances the flatness of the entire semiconductor device and facilitates the attachment of the cooler therebelow.
  • FIG. 1 is a schematic cross-sectional view showing the configuration of a characterizing part of the semiconductor device of Embodiment 1;
  • FIG. 2 is a schematic plan view showing the configuration of a herb bridge circuit including the characteristic part shown in FIG. 1 of the semiconductor device of Embodiment 1;
  • FIG. 18 is a schematic cross-sectional view showing the configuration of the characterizing portion of the semiconductor device of Embodiment 2;
  • FIG. 13 is a schematic plan view showing the configuration of a herb bridge circuit including the characteristic part shown in FIG. 1 of the semiconductor device of Embodiment 2;
  • FIG. 18 is a schematic cross-sectional view showing the configuration of the characterizing portion of the semiconductor device of Embodiment 3;
  • FIG. 18 is a schematic plan view showing the configuration of a herb bridge circuit including the characteristic part shown in FIG. 1 of the semiconductor device of Embodiment 3;
  • FIG. 26 is a schematic cross-sectional view showing the configuration of the characterizing portion of the semiconductor device of Fourth Embodiment;
  • FIG. 18 is a schematic plan view showing the configuration of a herb bridge circuit including the characteristic part shown in FIG. 1 of the semiconductor device of the fourth embodiment.
  • FIG. 35 is a schematic cross-sectional view showing the configuration of the characterizing portion of the semiconductor device of Embodiment 5;
  • FIG. 31 is a schematic plan view showing the configuration of a herb bridge circuit including the characteristic part shown in FIG. 1 of the semiconductor device of Embodiment 5;
  • FIG. 1 is a schematic cross-sectional view of a portion along line II in FIG.
  • semiconductor device 100 of the present embodiment mainly includes substrate material 1, semiconductor element 3, terminal 5, connection material 7, and resin 9.
  • the connection member 7 includes connection members 7A, 7B and 7C.
  • the substrate material 1 includes an insulating substrate 10, a first conductor substrate 11, a second conductor substrate 12, and a third conductor substrate 13.
  • Insulating substrate 10 is an insulating flat member made of, for example, aluminum nitride, and has, for example, a rectangular shape in plan view. Insulating substrate 10 has one main surface 10A disposed upward in FIG. 1 and the other main surface 10B disposed opposite to one main surface 10A, that is, downward in FIG.
  • the first conductor substrate 11 and the second conductor substrate 12 are flat members disposed on one main surface 10 A of the insulating substrate 10.
  • the first conductor substrate 11 and the second conductor substrate 12 are spaced apart from each other on one main surface 10A.
  • the third conductor substrate 13 is disposed on the other main surface 10 B of the insulating substrate 10.
  • the third conductor substrate 13 is a flat member having, for example, a rectangular shape in a plan view.
  • Third conductor substrate 13 is arranged to cover as large a region as possible on the other main surface 10B so as to include a region overlapping with first conductor substrate 11 and second conductor substrate 12 at least in plan view. Are more preferable, and it is more preferable to be disposed so as to cover the entire surface of the other main surface 10B.
  • the first conductor substrate 11, the second conductor substrate 12, and the third conductor substrate 13 are preferably made of, for example, copper, and are directly bonded on one main surface 10A or the other main surface 10B.
  • the semiconductor element 3 is a chip-like member on which a power semiconductor device such as an IGBT, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a diode is mounted.
  • the chip-like member as the main body of the semiconductor element 3 is preferably a wide band gap semiconductor element, and the semiconductor element 3 is preferably made of, for example, a compound containing silicon and carbon as main components, for example, silicon carbide (SiC) It is preferable that it consists of. In this way, the dimensions of the semiconductor element 3 can be reduced.
  • the semiconductor element 3 is connected to the side opposite to the insulating substrate 10 of the first conductor substrate 11, that is, the upper side of FIG. 1 by a connecting material 7A such as solder.
  • the metal film for solder bonding is a metal film formed on the outside in a plan view of the electrode and supplied prior to the supply of the connection material 7A such as solder for protecting the electrode from the connection material 7A.
  • the electrode made of a thin film of aluminum may be, for example, a control electrode 4 described later.
  • the terminal 5 is connected to the side opposite to the first conductor substrate 11 of the semiconductor element 3, that is, the upper side in FIG. 1 by a connecting material 7 B such as solder.
  • the terminal 5 extends from the region on the semiconductor element 3 to the region on the second conductor substrate 12 and is connected to the second conductor substrate 12. That is, the terminal 5 is joined to the upper surface of the semiconductor element 3 by the connecting material 7B, and is joined to the upper surface of the second conductor substrate 12 by the connecting material 7C such as solder.
  • the terminal 5 is directly connected to the second conductor substrate 12.
  • “directly connected” means that any member (for example, an insulating sheet or the like) other than a connecting material for connecting both, such as solder, between the terminal 5 and the second conductor substrate 12 is not sandwiched. means. That is, the semiconductor element 3 is not connected to the upper side of FIG. 1 of the second conductor substrate 12.
  • the terminal 5 is connected to only a single semiconductor element 3.
  • the thickness of the connecting material 7A in the vertical direction in FIG. 1 is preferably 50 ⁇ m to 200 ⁇ m, and the same thickness of the connecting material 7B is preferably 50 ⁇ m to 300 ⁇ m.
  • the same thickness of the connection material 7C is preferably 50 ⁇ m or more and 200 ⁇ m or less.
  • the connection material 7 has a thickness of 50 ⁇ m or more to buffer the stress generated due to the difference between the linear expansion coefficients at the contact portion between the semiconductor element 3, the first and second conductor substrates 11 and 12, and the terminal 5. can do.
  • the thickness of the connecting material 7A directly below the semiconductor element 3 to 200 ⁇ m or less, it is possible to suppress the decrease in the thermal resistance of the connecting material 7A and the inclination of the semiconductor element 3 mounted thereon.
  • the upper limit value of the thickness of the connection members 7B and 7C to 300 ⁇ m or less, it is possible to suppress the decrease in thermal resistance in the connection members 7B and 7C while absorbing the parallelism tolerance of the terminal 5.
  • the first terminal surface on the side of the substrate material 1 of the terminal 5, that is, on the lower side of FIG. 1 is a distance from the substrate material 1 directly above the second conductor substrate 12 as compared to directly above the first conductor substrate Is getting shorter. That is, the terminal 5 is bent so as to extend downward in FIG. 1 in a region between immediately above the first conductor substrate 11 and just above the second conductor substrate 12. If the thicknesses of the connection material 7A and the connection material 7C in FIG. 1 are approximately equal, the terminal 5 is directly above the second conductor substrate 12 as compared to the one above the first conductor substrate 11, compared to the semiconductor element 3 and The connection material 7B is disposed on the lower side of FIG. 1 by the sum of the thicknesses in the vertical direction of FIG.
  • the terminal 5 is a rectangular plate-like conductor extending in a direction from the first conductor substrate 11 to the second conductor substrate 12 in a plan view, for example.
  • Terminal 5 is formed of a conductive material such as copper, for example, and has a thickness of about 0.3 mm or more and 2.0 mm or less.
  • the terminal 5 preferably has a heat capacity larger than that of the first conductor substrate 11.
  • the semiconductor device 100 at least a part of the substrate material 1, the semiconductor element 3, and the terminal 5 described above is sealed with a resin 9. That is, in FIG. 1, the surfaces of the first conductor substrate 11 and the second conductor substrate 12 on one main surface 10A of the insulating substrate 10 of the substrate material 1 are sealed except for the regions connected by other members. It is covered with the stopped resin 9.
  • the semiconductor element 3 is also covered with the resin 9 except the regions joined by the connecting members 7A and 7B.
  • the terminal 5 is exposed from the resin 9 in the region on the right side of the right end of the substrate material 1 in FIG. 1, but in the other regions, it is covered with the resin 9 except the regions joined by the joining materials 7B and 7C. There is.
  • the resin 9 is, for example, a generally known epoxy resin material.
  • the third conductor substrate 13 is exposed from the resin 9 without being sealed by the resin 9.
  • the main surface 13B on the lower side of FIG. 1 of the third conductor substrate 13 is exposed from the resin 9 in the other regions except the region joined to the other main surface 10B of the insulating substrate 10.
  • the resin 9 can suppress a short circuit with other members of the semiconductor element 3 due to a foreign matter and a disturbance factor such as humidity. Therefore, the handleability and reliability of the semiconductor device 100 can be improved.
  • the lower main surface 13B of the semiconductor device 100 shown in FIG. 1, that is, the lower side of the third conductor substrate 13 is a cooler such as a heat sink with a bonding material such as grease which is different from It is connected to the.
  • the semiconductor element 3 has, for example, a plurality of control electrodes 4 on the upper surface thereof.
  • the control electrode 4 is electrically connected to the external electrode 25 by a wire 21 made of, for example, aluminum.
  • the external electrode 25 is an electrode for electrically connecting the inside and the outside of the resin 9, that is, the inside and the outside of the semiconductor device 100, and extends from the area inside the resin 9 to the area outside.
  • an electrical signal can be input to the semiconductor element 3 from the outside of the semiconductor device 100 through the external electrode 25 and the wire 21. Therefore, the semiconductor element 3 can be operated from the outside of the semiconductor device 100.
  • the cross-sectional view of semiconductor device 100 shown in FIG. 1 is actually a part of the entire semiconductor device 100, and corresponds to, for example, the right half of FIG. In FIG. 2, the resin 9 of FIG. 1 is not shown for convenience of description.
  • the second conductor substrate 12 has a rectangular shape in plan view.
  • the first conductor substrate 11 is not only a region adjacent to the left side of the second conductor substrate 12 shown in FIG. 1, that is, a region adjacent to the lower side of the second conductor substrate 12 shown in FIG. It extends to the adjacent area on the left side of.
  • the semiconductor element 3 connected to the upper side of FIG. 1 of the first conductor substrate 11 is mounted so as to spread in a rectangular shape on a partial region on the first conductor substrate 11, but the other It is not placed on the area.
  • a region on which the semiconductor element 3 is connected in plan view is taken as a first region, and the other region is taken as a second region.
  • Substrate material 1 further includes a fourth conductor substrate 14 spaced apart from first conductor substrate 11 and second conductor substrate 12 on one main surface 10A of insulating substrate 10. .
  • the fourth conductor substrate 14 is disposed in the region on the upper left side of the insulating substrate 10 of FIG. 2 and is preferably made of, for example, copper, like the first to third conductor substrates 11 to 13.
  • the fourth conductor substrate 14 is directly bonded on one of the main surfaces 10A by a connecting material 7 such as a solder similar to FIG.
  • Another semiconductor element 30 is connected to the side opposite to the insulating substrate 10 of the fourth conductor substrate 14, that is, to the upper side of FIG. 1.
  • the fourth conductor substrate 14 and the other semiconductor element 30 are directly joined by a connecting material 7 such as a solder similar to FIG. 1, for example.
  • the other semiconductor element 30 is preferably made of, for example, a compound containing silicon and carbon as main components, for example, preferably made of silicon carbide (SiC).
  • Another terminal 50 is connected to the other semiconductor element 30 on the opposite side to the fourth conductor substrate 14, that is, to the upper side of FIG. 1.
  • the other terminals 50 extend from the area on the other semiconductor element 30 to the second area on the first conductor substrate 11, that is, from the upper area to the lower area in FIG.
  • the other terminal 50 is connected to the second region of the first conductor substrate 11. That is, the other terminal 50 is joined to the upper surface of the other semiconductor element 30 by the connecting material 7, and by the connecting material 7, a region corresponding to the second region of the upper surface of the first conductor substrate 11. It is joined.
  • the semiconductor element 3 on the first conductor substrate 11 whose cross section is shown in FIG. 1 and the second conductor substrate 12 adjacent to the first conductor substrate 11 are connected by the terminals 5.
  • the other semiconductor element 30 on the fourth conductor substrate 14 disposed on the left side of them in FIG. 2 and the second region of the first conductor substrate 11 adjacent to the fourth conductor substrate 14 are other It is connected by the terminal 50. Both the terminal 5 and the other terminal 50 are electrically connected to the first conductor substrate 11 to constitute a half bridge circuit.
  • the first conductor substrate 11 has a role as a first region to which the semiconductor element 3 is connected and the terminal 5 directly above the semiconductor element 3 is connected to the other second conductor substrate 12, and conversely, the other fourth conductor substrate
  • the other terminals 50 connected to the other 14 semiconductor elements 30 share the role of receiving and connecting as a second region.
  • the fourth conductor substrate 14 to which the other semiconductor element 30 in the left half region of FIG. 2 is connected corresponds to the first conductor substrate 11 to which the semiconductor element 3 in the right half region of FIG.
  • the first conductor substrate 11 in the left half of FIG. 2 corresponds to the second conductor substrate 12 to which the semiconductor element 3 in the right half of FIG. 2 is not connected. That is, the semiconductor element 3 is not directly connected to the second region of the first conductor substrate 11.
  • the area occupied by the members having the two roles is reduced as compared with the case where they are formed as separate members. it can. Further, by arranging three half bridge circuits in parallel, a full bridge circuit can be configured, which can be accommodated in one semiconductor device 100.
  • the above-described power semiconductor device mounted on the semiconductor element 3 and the other semiconductor element 30 shown in FIG. 2 has both a function as a switch and a function as a diode for reflux, and specifically, A power MOSFET and an RC-IGBT can be used as the power semiconductor device.
  • the semiconductor element on which the power semiconductor device having a function as a switch is mounted and the semiconductor element on which the power semiconductor device having a function as a free wheeling diode are mounted are on the substrate material 1 as separate chips.
  • the number of chips can be reduced compared to when mounted. That is, the area occupied by the semiconductor elements 3 and 30 on the upper surface of the substrate material 1 can be reduced by the reduction in the number of chips.
  • the planar layout of the semiconductor device 100 can be allocated to other regions as much as the area occupied by the semiconductor elements 3 and 30 is reduced. Further, the distance between the semiconductor element 3 and the second conductor substrate 12 and the distance between the other semiconductor elements 30 and the second region of the first conductor substrate 11 are equal to the reduction of the area occupied by the semiconductor elements 3 and 30. The length of the terminal 5 in the direction connecting the semiconductor element 3 and the second conductor substrate 12 and the distance between the other semiconductor element 30 of the other terminal 50 and the second region can be shortened. .
  • the semiconductor device 100 of the present embodiment having the above configuration is basically formed by the manufacturing method described below. The main parts of the method of manufacturing the semiconductor device 100 will be described below.
  • the first conductor substrate 11, the second conductor substrate 12, and the third conductor substrate 13 are made of a copper-oxygen eutectic liquid phase formed using a small amount of oxide contained in copper constituting them. It is preferable to be directly bonded on one main surface 10A or the other main surface 10B by using. Alternatively, the first conductor substrate 11, the second conductor substrate 12, and the third conductor substrate 13 may be provided on one main surface 10A or the other main surface using a brazing material to which an active metal material such as titanium and zirconium is added. It may be directly bonded on 10B. The bonding interface between the insulating substrate 10 and the first conductor substrate 11, the second conductor substrate 12, and the third conductor substrate 13 thus formed has good thermal conductivity, reliability and flatness. It can be
  • first conductor substrate 11, second conductor substrate 12 and third conductor substrate 13 on one main surface 10A and the other main surface 10B of insulating substrate 10 will be described in more detail.
  • a flat copper plate is bonded onto one major surface 10A and the other major surface 10B.
  • a copper flat plate on one main surface 10A is formed as a circuit pattern by a normal photolithographic technique, that is, exposure and development processing.
  • the first conductor substrate 11 and the second conductor substrate 12 are formed on one main surface 10A.
  • the thickness of the above-described copper flat plate is preferably about 0.6 mm or less.
  • An electrode made of a thin film of aluminum on the upper or lower surface of semiconductor element 3 is formed by a generally known sputtering method, for example, in the manufacturing process of semiconductor element 3.
  • the metal film for solder bonding on the upper or lower surface of the semiconductor element 3 is formed by using a generally known wet plating method or sputtering method after the aluminum electrode is formed by the sputtering method described above. .
  • the semiconductor element 3 is connected on the first conductor substrate 11 by a connecting material 7A such as solder.
  • a connecting material 7A such as solder.
  • solder or the like as the connection material 7A is placed on the first conductor substrate 11, and the semiconductor element is thereon Three more are stacked. Then, by heating them in a reducing atmosphere, a solder joint between the back surface of the semiconductor element 3 and the first conductor substrate 11 can be obtained.
  • solder and the like as the connection material 7 B are also provided on the surface of the semiconductor element 3, whereby the terminal 5 to be described later
  • the connection material can be formed in advance.
  • the space between the first conductor substrate 11 and the semiconductor element 3 can be made favorable electrically and thermally. It is possible to connect and secure the reliability of the connection interface of both.
  • the terminal 5 is formed by punching a copper plate having a thickness of about 0.3 mm or more and 2.0 mm or less as shown in FIG. 1 in part of its area than other areas (at least the semiconductor element 3 and the connecting material 7B ) Is configured to be placed downward by the sum of the thickness of the layer, and then controlled by pressing so that a part of the area is placed downward by the necessary size with respect to the other area It is formed by being done.
  • the relationship between the distance between the first terminal surface of the terminal 5 and the surface of the first conductor substrate 11 and the distance between the first terminal surface of the terminal 5 and the surface of the second conductor substrate 12 is arbitrary. It can be adjusted.
  • the terminal 5 is bent in a region between the first conductor substrate 11 and the second conductor substrate 12, for example, so that the angle in which the terminal 5 extends in the horizontal direction in FIG. It is preferable that the angle be, for example, 30 ° or more and 45 ° or less with respect to the direction along one main surface 10A.
  • the terminal 5 is placed at a predetermined position on the solder as the connection material 7B previously installed on the semiconductor element 3 and the solder as the connection material 7C previously installed on the second conductor substrate 12. By heating the whole system in a reducing atmosphere in this state, the terminal 5, the semiconductor element 3 and the second conductor substrate 12 are bonded to each other.
  • the entire system is sealed with the resin 9 so as to be in the mode shown in FIG.
  • This step is preferably performed by, for example, transfer molding or potting.
  • the transfer molding method is a method in which a fluid resin is pressed into a mold in which the entire system is set, and the resin is cured by pressing and heating.
  • the potting method is a method of flowing a fluid resin into a resin frame in which the entire system is set and heating the resin to cure the resin.
  • a bonding material such as grease is applied on the lower surface of the third conductor substrate 13 exposed from the resin 9 and cooled onto the lower surface of the third conductor substrate 13 using a plate spring or the like.
  • the vessels are joined. That is, the third conductor substrate 13 and the cooler are fixed to each other by the pressing force of the plate spring. Thereby, the whole of the semiconductor device 100 shown in FIG. 1 can be connected to a cooler that facilitates good heat conduction.
  • the semiconductor element if the semiconductor element is disposed also in the region above the second conductor substrate 12 of the second path, the semiconductor element does not exist in this portion due to heat generation of the semiconductor element itself.
  • the heat radiation action in the second path which propagates the terminal 5 from the upper side of the semiconductor element 3 of FIG. 1 is weakened.
  • the material such as silicon carbide constituting the semiconductor element weakens the heat radiation effect in the second path also by the fact that the thermal resistance is larger than that of the conductor material.
  • the heat generation of the semiconductor element 3 can be dissipated from the first and second paths which are the following two paths.
  • the first path is transmitted from the semiconductor element 3 through the lower connection material 7A to the lower first conductor substrate 11, the insulating substrate 10, and the third conductor substrate 13 and from there to the cooler (not shown) below. It is a route to be transmitted.
  • the second path passes from the semiconductor element 3 through the upper connection material 7B to the terminal 5, and after the terminal 5 is transmitted to the second conductor substrate 12, the connection material 7C, the second conductor substrate 12, insulation It is a path which is transmitted to the substrate 10 and the third conductor substrate 13 and then to a cooler (not shown) therebelow.
  • the heat generation of the semiconductor element 3 is dissipated from the upper and lower surfaces thereof through the first and second paths.
  • the heat transferred to the upper side of the semiconductor element 3 can also be efficiently dissipated from the substrate material 1 to the cooler (not shown) below the substrate material 1 by the second path passing through the terminal 5.
  • the heat radiation efficiency can be significantly improved as compared with the case where the heat is dissipated only from the lower side of the semiconductor element 3 by the first path.
  • the heat dissipation by the second path is realized by the terminal 5 being connected to the semiconductor element 3 by the connection member 7B and directly connected to the second conductor substrate 12 by the connection member 7C. Therefore, the distance of the first terminal surface of the terminal 5 from the substrate material 1 in the vertical direction in FIG. 1 from the substrate material 1 becomes short as compared with that just above the first conductor substrate 11 immediately above the second conductor substrate 12 It has been bent. By having such a configuration, the heat transmitted from the upper side of the semiconductor element 3 to the terminal 5 can be propagated downward more quickly to reach the substrate material 1.
  • the present invention is particularly effective in the semiconductor device 100 using the compound semiconductor of
  • the third conductor substrate 13 corresponding to the lowermost portion of the semiconductor device 100 is exposed from the resin. If third conductive substrate 13 is formed so as to be exposed from resin 9 and cover most of the other main surface 10B of insulating substrate 10, the base of the entire semiconductor device 100 is flat third conductive substrate 13 It can be firmly supported by the lower surface part. This means that the third conductor substrate 13 is firmly joined onto the other main surface of the insulating substrate 10 constituting the substrate material 1, and the insulating substrate 10 is the substrate material 1 and the semiconductor device 100 including the substrate material 1. And a member that can firmly support the entire foundation of the Therefore, the parallelism, that is, the flatness of the semiconductor device 100 can be improved by applying the configurations of the substrate material 1 and the third conductor substrate 13 of the present embodiment.
  • the lowermost conductor substrate of the semiconductor device 100 is only the third conductor substrate 13. That is, only the third conductor substrate 13 is connected to the cooler below it. Therefore, the parallelism of the entire semiconductor device 100 including the third conductor substrate 13 is necessarily improved as compared with the case where the semiconductor device is connected to the cooler by, for example, a plurality of conductor substrates spaced from each other. .
  • the parallelism of the portion of the third conductor substrate 13 is inferior, for example, in the case where a cooler is attached below the third conductor substrate 13 with the insulating sheet interposed therebetween, the insulating sheet and the semiconductor device thereon An air gap occurs between 100 and 100, and the thermal resistance between these regions increases.
  • a gap is generated between the third conductor substrate 13 and the cooler, creeping discharge occurs in the portion of the gap, which makes it difficult to secure insulation in the region. Therefore, if the flatness of the third conductor substrate 13 which is the lowermost part of the semiconductor device 100 is improved as in the present embodiment, the bonding between the third conductor substrate 13 and the cooler therebelow should be better. can do. Therefore, the heat dissipation from the third conductor substrate 13 to the cooler can be further improved.
  • the insulating substrate 10 included in the substrate material 1 can ensure the electrical insulation between the cooler connected to the lower side of the substrate material 1 and the semiconductor element 3 or the like. Therefore, the substrate material 1 and the cooler can be joined using a simple member such as grease or solder.
  • connection between the semiconductor element 3 and the first conductor substrate 11 and the terminal 5 and the connection between the terminal 5 and the second conductor substrate 12 included in the semiconductor device 100 are made by a connection material 7 such as solder. It is more preferable that a solder be used as the connection material 7.
  • connection between the members included in the semiconductor device 100 using the connection material 7 may form a defect such as a step (height difference) in the vertical direction in FIG. 1 due to a dimensional error of each member. .
  • the steps (height difference) and the like can be minimized by forming the semiconductor device 100 having excellent flatness based on the substrate material 1 including the insulating substrate 10 described above. However, minute steps still remain. Therefore, in the present embodiment, it is more preferable to use, for example, a solder containing tin, copper and silver as the connection material 7 for connecting the respective members. If such a solder is used, it is possible to offset by easily filling the minute steps.
  • the thermal conductivity of the solder is about 60 W / m ⁇ K
  • the thermal conductivity of the grease is about 5 W / m ⁇ K
  • the thermal conductivity of the insulating sheet is about 10 W / m ⁇ K. Is larger than the thermal conductivity of the grease and the insulating sheet. For this reason, even if a level difference is formed between the respective members and it can not be offset by the solder, the high thermal conductivity of the solder can suppress an increase in the thermal resistance between the respective members, and the semiconductor device The reliability of 100 can be secured.
  • the terminal 5 preferably has a heat capacity larger than that of the first conductor substrate 11. If the thickness of the first conductor substrate 11 and the second conductor substrate 12 is reduced to, for example, 0.6 mm or less, the distance in the vertical direction of FIG. 1 to these coolers can be reduced. The steady-state thermal resistance of the substrate 11 can be lowered. However, on the other hand, since the thicknesses of the first conductor substrate 11 and the second conductor substrate 12 are thin and the heat capacities thereof are small, the transient thermal resistance of the first conductor substrate 11 becomes high. On the other hand, the thickness of the terminal 5 is about 2.0 mm at maximum, and is formed thicker than the first conductor substrate 11 and the second conductor substrate 12. Thus, the terminal 5 can reduce the transient thermal resistance.
  • the steady-state thermal resistance between the terminal 5 and the second conductor substrate 12 is inversely proportional to the cross-sectional area of the terminal 5. Therefore, by forming the terminal 5 thick, the steady-state thermal resistance between the terminal 5 and the second conductor substrate 12 can be lowered, and heat transfer from the terminal 5 to the second conductor substrate 12 in the second path can be achieved. Can be promoted.
  • the second terminal surface of the terminal 5 is covered with the resin 9 immediately above the first and second conductor substrates 11 and 12, and the terminal 5 is formed from the uppermost surface of the resin 9. It is not exposed. For this reason, on the uppermost surface of the resin 9, that is, the uppermost surface of the semiconductor device 100, a fixing device for fixing the semiconductor device 100, a control substrate, and the like can be placed.
  • FIG. 3 is a schematic cross-sectional view of a portion along the line III-III in FIG.
  • semiconductor device 200 according to the present embodiment has the same configuration as that of semiconductor device 100 according to the first embodiment. Therefore, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.
  • the first heat capacity body 31 is disposed on the side opposite to the semiconductor element 3 of the terminal 5 directly above the first conductor substrate 11, that is, on the upper side of FIG.
  • the first heat capacity body 31 is connected to the upper surface of the terminal 5 by the connection material 7D. That is, the connection member 7 includes the connection members 7A, 7B, 7C, and 7D.
  • the first heat capacity body 31 is preferably a heat sink using, for example, copper as a base material, and is formed, for example, in a rectangular parallelepiped shape by punching a copper plate.
  • press processing for forming a crookedness part like formation of terminal 5 is unnecessary.
  • a copper plate thicker than the copper plate for forming terminal 5 can be used, for example, the 1st heat capacity body 31 whose thickness is 3.0 mm can be formed.
  • the bonding step of the terminal 5 and the first heat capacity body 31 using the connecting material 7D can be performed using solder simultaneously with the bonding step of the semiconductor element 3 and the terminal 5 using the connecting material 7A, for example. At this time, it is preferable to secure the positional accuracy of the first heat capacity body 31 using a jig.
  • the heat capacity of the first heat capacity body 31 formed in this manner is larger than that of the first conductor substrate 11 and the second conductor substrate 12.
  • the present embodiment exerts the following effects in addition to the effects of the first embodiment.
  • the first heat capacity body 31 having a larger heat capacity than the first conductor substrate 11 and the second conductor substrate 12 is connected to the terminal 5. For this reason, the heat capacity of the whole of the portion which united the terminal 5 and the 1st heat capacity body 31 can be made still larger than Embodiment 1. In addition, the overall transient thermal resistance of the portion where the terminal 5 and the first heat capacity body 31 are combined can be made lower than that of the first embodiment. As a result, it is possible to further improve the heat dissipation than in the first embodiment.
  • the first heat capacity body 31 is formed separately from the terminal 5 and is connected to the terminal 5 by a connection material 7D. Therefore, without making the shape of the terminal 5 complicated, it is possible to achieve an effect such as increasing the heat capacity of a member obtained by combining the terminal 5 and the first heat capacity body 31.
  • FIG. 5 is a schematic cross-sectional view of a portion along line VV in FIG.
  • semiconductor device 300 of the present embodiment has a configuration similar to that of semiconductor devices 100 and 200 of the first and second embodiments. Therefore, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.
  • the second heat capacity body 32 is disposed on the side opposite to the substrate material 1 of the terminal 5 directly above the second conductor substrate 12, that is, on the upper side of FIG.
  • the second heat capacity body 32 is connected to the upper surface of the terminal 5 by the connection material 7D. That is, the connection member 7 includes the connection members 7A, 7B, 7C, and 7D.
  • the second heat capacity body 32 is formed of the same material as the first heat capacity body 31 and formed in the same size by the same manufacturing method, so the detailed description will be omitted.
  • the second heat capacity body 32 formed in this manner has a heat capacity larger than that of the first conductor substrate 11 and the second conductor substrate 12.
  • the present embodiment exhibits the following effects in addition to the effects of the first and second embodiments.
  • the second heat capacity body 32 having a larger heat capacity than the first conductor substrate 11 and the second conductor substrate 12 is connected to the terminal 5.
  • the heat capacity of the whole of the portion which united the terminal 5 and the 2nd heat capacity body 32 can be made still larger than Embodiment 1.
  • the overall transient thermal resistance of the portion where the terminal 5 and the first heat capacity body 31 are combined can be made lower than that of the first embodiment. As a result, it is possible to further improve the heat dissipation than in the first embodiment.
  • the thickness of the semiconductor element 3 and the connecting material 7B is higher than that of the first conductive substrate 11 (when the thicknesses of the connecting material 7A and the connecting material 7C are equal) right above the second conductive substrate 12
  • the terminal 5 is disposed on the lower side of FIG. Therefore, even if the thick second heat capacity body 32 is formed right above the second conductor substrate 12, the sum of the thickness and the thickness of the connection material 7D is equal to or less than the sum of the thicknesses of the semiconductor element 3 and the connection material 7B.
  • the height of the top surface of the second heat capacity body 32 will not be higher than the top surface of the terminal 5 on the first conductor substrate 11.
  • the second conductor substrate as in the present embodiment, an increase in the dimension in the vertical direction of FIG. 5 in particular of the entire semiconductor device 100 can be suppressed. Therefore, the entire semiconductor device 100 can be miniaturized as compared with the second embodiment, and as a result, the cooling performance can be further improved.
  • FIG. 7 is a schematic cross-sectional view of a portion along line VII-VII in FIG.
  • semiconductor device 400 of the present embodiment generally has the same configuration as that of semiconductor devices 100 to 300 of the first to third embodiments. Therefore, the same components are denoted by the same reference numerals, and the description thereof will not be repeated.
  • the terminal 5 is not directly connected to the second conductor substrate 12, and a member other than the connecting material 7 is disposed between the two. Have. Specifically, the terminal 5 is connected to the second conductor substrate 12 via the third heat capacity body 33.
  • the third heat capacity body 33 is formed as a rectangular parallelepiped heat sink by punching out a copper plate in the same manner as the first heat capacity body 31 and the second heat capacity body 32. Therefore, the detailed description of the third heat capacity body 33 is omitted.
  • the third heat capacity body 33 is connected to the side opposite to the substrate material 1 of the second conductor substrate 12, that is, the upper side of FIG. 7 by the connection material 7 ⁇ / b> C. Further, the third heat capacity body 33 is connected to the terminal 5 by the connection material 7D on the upper side of FIG.
  • the third heat capacity body 33 preferably has a heat capacity larger than that of the first conductor substrate 11 and the second conductor substrate 12.
  • the sum of the thicknesses of the connection material 7A, the semiconductor element 3 and the connection material 7B is the connection material 7C. It is preferable to form so that it may become equal to the sum of the thickness of the 3rd heat capacity body 33 and the connection material 7D.
  • the terminal 5 does not have to be bent so that the distance from the substrate material 1 is shorter than the region on the first conductor substrate 11 in the region on the second conductor substrate 12. 5 has a flat shape between the area on the first conductor substrate 11 and the area on the second conductor substrate 12.
  • the present embodiment exerts the following effects in addition to the effects of the first to third embodiments.
  • the third heat capacity body 33 disposed between the terminal 5 and the second conductor substrate 12 can be used as a spacer.
  • the total heat capacity of the portion where the terminal 5 and the third heat capacity body 33 are combined can be further increased as compared with the first embodiment.
  • the cross-sectional area of the entire portion of the combination of the terminal 5 and the third heat capacity 33 is larger than that of the first embodiment by the third heat capacity 33, so both transient heat resistance and steady state heat resistance are obtained. Can be lowered, and the heat dissipation by the second path can be further improved.
  • the third heat capacity body 33 is disposed right above the second conductor substrate 12.
  • the second conductor as in the present embodiment, an increase in the size in the vertical direction of FIG. 7 of the entire semiconductor device 100 can be suppressed. Therefore, the entire semiconductor device 100 can be miniaturized as compared with the second embodiment, and as a result, the cooling performance can be further improved.
  • the terminal 5 can be formed into a flat shape. In this way, it is not necessary to perform press work for forming a portion bent downward to the connecting member 7B and the terminal 5 connected on the connecting member 7D. Therefore, the processing cost of the terminal 5 can be reduced, and the upper limit of the thickness of the terminal 5 can be designed to be higher. Specifically, the thickness of the terminal 5 can be 3.0 mm. This is because the copper plate is required to be thin in order to bend the copper plate by pressing.
  • FIG. 9 is a schematic cross-sectional view of a portion along line IX-IX in FIG.
  • semiconductor device 500 of the present embodiment has substantially the same configuration as that of semiconductor device 400 of the fourth embodiment. Therefore, the same components are denoted by the same reference numerals, and the description thereof will not be repeated. However, in the semiconductor device 500, the portions of the third heat capacity body 33 and the connection material 7 D of the semiconductor device 400 are configured integrally with the terminal 5.
  • the terminal 5 is a region extending flatly from the region on the first conductor substrate 11 similar to the terminal 5 of the semiconductor device 400 to the region on the second conductor substrate 12, and the third thermal capacitor of the semiconductor device 400 It has a structure which consists of a copper plate with which projection part 5T corresponded to 33 and the part of connecting material 7D was united.
  • the terminal 5 has a projection 5T in which the surface of the first terminal on the side of the substrate material 1 projects to the side of the substrate material 1 immediately above the second conductor substrate 12.
  • the distance from the substrate material 1 is shorter on the first terminal surface than on the first conductor substrate 11 immediately above the second conductor substrate 12.
  • the thickness of the protrusion 5T is, for example, about 1 mm, and preferably 0.7 mm or more and 1.3 mm or less.
  • the protrusion 5T and the second conductor substrate 12 are connected by a connecting material 7C. Further, on the first conductor substrate 11, the terminals 5 are connected by the connection material 7B on the semiconductor element 3 as in the other embodiments.
  • the protrusion 5T is provided, and the connection material 7D of the fourth embodiment and the portion of the third heat capacity body 33 are integrated with the terminal 5, so that the number of parts is smaller than that of the fourth embodiment. It can be reduced and processing can be facilitated.
  • the portion of the connection material 7D as the solder is replaced with the protrusion 5T which is a part of the copper plate. While the thermal conductivity of the solder is about 60 W / m ⁇ K, the thermal conductivity of copper is about 400 W / m ⁇ K, which is much higher than that of the solder. Therefore, by applying the terminal 5 of the present embodiment, the heat dissipation of the second path can be further improved as compared to the fourth embodiment.
  • each configuration of the second to fifth embodiments is described as applied to, for example, the area on the right side of FIGS. 4, 6, 8 and 10, but the left side of FIGS. These can be applied to the area of.
  • the region where the other semiconductor element 30 is connected to the fourth conductor substrate 14 corresponds to the region where the semiconductor element 3 is connected to the first conductor substrate 11 in FIGS.
  • the second region of the first conductor substrate 11 corresponds to the region on the second conductor substrate 12 of FIGS.
  • FIGS. 1, 3, 5, 7 and 9 of the first to fifth embodiments are combined as appropriate for each of the left half region and the right half region in FIGS. It may be applied as That is, the technical features in the respective embodiments described above may be appropriately combined and applied as long as there is no technical contradiction.

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Abstract

均一な放熱性が得られるとともに、容易に冷却器への取り付けが可能な半導体装置（１００）は、基板材（１）と、半導体素子（３）と、端子（５）とを備えている。基板材（１）は、絶縁基板（１０）と、絶縁基板（１０）の一方の主表面（１０Ａ）上に互いに間隔をあけて配置された第１および第２の導体基板（１１，１２）と、絶縁基板（１０）の一方の主表面（１０Ａ）と反対側の他方の主表面（１０Ｂ）上に配置された第３の導体基板（１３）とを含む。半導体素子（３）は、第１の導体基板（１１）の絶縁基板（１０）と反対側に接続される。端子（５）は、半導体素子（３）の第１の導体基板（１１）と反対側に接続される。端子（５）は半導体素子（３）上の領域から第２の導体基板（１２）の上の領域まで延びるとともに、第２の導体基板（１２）と接続されている。基板材（１）、半導体素子（３）および端子（５）の少なくとも一部は樹脂（９）により封止される。第３の導体基板（１３）は樹脂（９）から露出している。

Description

半導体装置
　本発明は半導体装置に関し、特に冷却効率を向上するための電力用半導体装置に関するものである。
　ＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）などの電力用半導体素子が搭載された半導体装置において、その最下面側など片面のみから電力用半導体素子の発する熱を放熱する機構が、たとえば特開２０１５－１１５４７１号公報（特許文献１）に開示されている。一方、放熱性を向上させる電力用の他の半導体装置が、たとえば特開２００３－２５８１６６号公報（特許文献２）に開示されている。これらの半導体装置においては、その最下面側にヒートシンクなどの冷却器が接合され、その下方からの放熱が可能となっている。
特開２０１５－１１５４７１号公報 特開２００３－２５８１６６号公報
　一般的に半導体素子は基本的にその下方に伝わる熱よりも上方に伝わる熱の方が外部への放熱が困難であり、その上方に伝わる熱を効率的に放熱することが望まれる。しかし特開２０１５－１１５４７１号公報においては発熱量の大きい２つの電力用半導体素子の双方とも、その上面が金属板に接続されている。このため特開２０１５－１１５４７１号公報においては半導体素子の上方に接続された金属板は２つの電力用半導体素子から大きな発熱を受ける。また半導体素子は一般的に導体材料などに比べて熱抵抗が大きい。このため熱容量の問題から、この金属板を介した装置外部への放熱性は十分でないと考えられる。つまり特開２０１５－１１５４７１号公報に開示の半導体装置は、全体としての放熱性が十分でないと考えられる。
　一方、特開２００３－２５８１６６号公報においては、半導体素子の上面側および下面側の双方に金属体が接合され、それら双方の金属体が半導体素子の下面側にて樹脂材料から露出する構成となっている。このため半導体素子の上方に伝わる熱がその下方に伝わる熱と同様に、半導体素子の下方に接続された冷却器などにより高効率に放熱される。
　しかし特開２００３－２５８１６６号公報においては、半導体装置の最下面側において樹脂材料から露出する、半導体素子の下面側に接合された第１の金属体と半導体素子の上面側に接合された第２の金属体との双方が絶縁シート等により電気的に絶縁される必要がある。このため当該絶縁シートの存在によりその下方への冷却器の取り付けの位置精度などを確保することが困難となる。また半導体素子の下面側において、樹脂材料から露出した第１の金属体と第２の金属体との間の平行度を確保することが求められるが、そのように２つの金属体の双方が同じ平面上に配置され半導体装置全体の平行度を確保する態様とすることは困難である。これら２つの金属体の間の平行度が悪ければ、たとえば第２の金属体とヒートシンクとの間に隙間が形成され、第２の金属体からの放熱性が低下したり、第１および第２の金属体間の絶縁性の確保が困難になるという問題が発生する。
　本発明は上記の課題に鑑みてなされたものであり、その目的は、均一な放熱性が得られるとともに、容易に冷却器への取り付けが可能な半導体装置を提供することである。
　本発明の半導体装置は、基板材と、半導体素子と、端子とを備えている。基板材は、絶縁基板と、絶縁基板の一方の主表面上に互いに間隔をあけて配置された第１および第２の導体基板と、絶縁基板の一方の主表面と反対側の他方の主表面上に配置された第３の導体基板とを含む。半導体素子は、第１の導体基板の絶縁基板と反対側に接続される。端子は、半導体素子の第１の導体基板と反対側に接続される。端子は半導体素子上の領域から第２の導体基板の上の領域まで延びるとともに、第２の導体基板と接続されている。基板材、半導体素子および端子の少なくとも一部は樹脂により封止される。第３の導体基板は樹脂から露出している。
　本発明によれば、端子が半導体素子の上面側から、半導体素子の下面側に配置される第２の導体基板まで延びるように接続されるため、半導体素子の上面側から下面側への放熱性を高めることができる。また基板の他方の主表面上の第３の導体基板により、半導体装置全体の平坦性を高め、その下方への冷却器の取り付けが容易になる。
実施の形態１の半導体装置の特徴部分の構成を示す概略断面図である。 実施の形態１の半導体装置の、図１に示す特徴部分を含むハーブブリッジ回路の構成を示す概略平面図である。 実施の形態２の半導体装置の特徴部分の構成を示す概略断面図である。 実施の形態２の半導体装置の、図１に示す特徴部分を含むハーブブリッジ回路の構成を示す概略平面図である。 実施の形態３の半導体装置の特徴部分の構成を示す概略断面図である。 実施の形態３の半導体装置の、図１に示す特徴部分を含むハーブブリッジ回路の構成を示す概略平面図である。 実施の形態４の半導体装置の特徴部分の構成を示す概略断面図である。 実施の形態４の半導体装置の、図１に示す特徴部分を含むハーブブリッジ回路の構成を示す概略平面図である。 実施の形態５の半導体装置の特徴部分の構成を示す概略断面図である。 実施の形態５の半導体装置の、図１に示す特徴部分を含むハーブブリッジ回路の構成を示す概略平面図である。
　以下、一実施の形態について図に基づいて説明する。
　（実施の形態１）
　まず本実施の形態の半導体装置の構成について図１および図２を用いて説明する。なお図１は図２中のＩ－Ｉ線に沿う部分の概略断面図である。図１を参照して、本実施の形態の半導体装置１００は、基板材１と、半導体素子３と、端子５と、接続材７と、樹脂９とを主に有している。接続材７は接続材７Ａ，７Ｂ，７Ｃを有している。
　基板材１は、絶縁基板１０と、第１の導体基板１１と、第２の導体基板１２と、第３の導体基板１３とを含んでいる。絶縁基板１０は、たとえば窒化アルミニウムからなる絶縁性を有する平板状の部材であり、たとえば平面視において矩形状を有している。絶縁基板１０は、図１における上方に配置される一方の主表面１０Ａと、一方の主表面１０Ａと反対側すなわち図１における下方に配置される他方の主表面１０Ｂとを有している。第１の導体基板１１および第２の導体基板１２は、絶縁基板１０の一方の主表面１０Ａ上に配置された平板状の部材である。
　第１の導体基板１１および第２の導体基板１２は、一方の主表面１０Ａ上において互いに間隔をあけて配置されている。第３の導体基板１３は、絶縁基板１０の他方の主表面１０Ｂ上に配置されている。第３の導体基板１３は、平面視においてたとえば矩形状を有する平板状の部材である。第３の導体基板１３は、少なくとも平面視において第１の導体基板１１および第２の導体基板１２と重なる領域を含むように他方の主表面１０Ｂ上のなるべく広い領域を覆うように配置されることが好ましく、他方の主表面１０Ｂの全面を覆うように配置されることがより好ましい。第１の導体基板１１、第２の導体基板１２および第３の導体基板１３はたとえば銅からなることが好ましく、一方の主表面１０Ａ上または他方の主表面１０Ｂ上に直接接合されている。
　次に半導体素子３は、ＩＧＢＴ、ＭＯＳＦＥＴ（Metal　Oxide　Semiconductor　Field　Effect　Transistor）またはダイオードなどの電力用半導体装置が搭載されたチップ状の部材である。半導体素子３の本体としてのチップ状の部材は、ワイドバンドギャップ半導体素子であることが好ましく、半導体素子３はたとえばシリコンとカーボンとを主成分とする化合物からなることが好ましく、たとえば炭化珪素（ＳｉＣ）からなることが好ましい。このようにすれば、半導体素子３の寸法を縮小することができる。半導体素子３は、第１の導体基板１１の絶縁基板１０と反対側すなわち図１の上側に、はんだなどの接続材７Ａにより接続されている。
　半導体素子３の図１の上側の表面と、半導体素子３の図１の下側の表面とには、図１中に示されないがたとえばアルミニウムの薄膜からなる電極と、ニッケルからなるはんだ接合用金属膜とが形成される。ここではんだ接合用金属膜は電極の平面視における外側に形成され、はんだなどの接続材７Ａの供給に先立って供給される、電極を接続材７Ａから保護するための金属膜である。アルミニウムの薄膜からなる電極は、たとえば後述する制御用電極４であってもよい。
　端子５は、半導体素子３の第１の導体基板１１と反対側すなわち図１の上側に、はんだなどの接続材７Ｂにより接続されている。端子５は、半導体素子３上の領域から第２の導体基板１２の上の領域まで延びるとともに、第２の導体基板１２と接続されている。すなわち端子５は、半導体素子３の上側の表面と接続材７Ｂにより接合されるとともに、はんだなどの接続材７Ｃにより第２の導体基板１２の上側の表面と接合されている。
　したがって端子５は第２の導体基板１２と直接接続されている。ここで直接接続されるとは、端子５と第２の導体基板１２との間にはんだなどの両者を接続するための接続材以外のいかなる部材（たとえば絶縁シートなど）も挟まれていないことを意味する。つまり第２の導体基板１２の図１の上側には、半導体素子３は接続されていない。端子５は、単一の半導体素子３のみと接続されている。
　接続材７Ａの図１の上下方向の厚みは５０μｍ以上２００μｍ以下であることが好ましく、接続材７Ｂの同厚みは５０μｍ以上３００μｍ以下であることが好ましい。また接続材７Ｃの同厚みは５０μｍ以上２００μｍ以下であることが好ましい。接続材７は５０μｍ以上の厚みを有することにより、半導体素子３と、第１および第２の導体基板１１，１２と、端子５との接触部において両者の線膨張係数差によって発生する応力を緩衝することができる。また半導体素子３の真下における接続材７Ａの厚みを２００μｍ以下とすることにより、接続材７Ａにおける熱抵抗の低下およびその上に搭載される半導体素子３の傾きを抑制することができる。さらに接続材７Ｂ，７Ｃの厚みの上限値を３００μｍ以下とすることにより、端子５の平行度公差を吸収しつつ、接続材７Ｂ，７Ｃにおける熱抵抗の低下を抑制することができる。
　端子５の基板材１側すなわち図１の下側にある第１の端子表面は、第２の導体基板１２の真上において第１の導体基板１１の真上に比べて基板材１からの距離が短くなっている。すなわち端子５は、第１の導体基板１１の真上と第２の導体基板１２の真上との間の領域において、図１の下側に延びるように屈曲している。図１における接続材７Ａと接続材７Ｃとの厚みがほぼ等しければ、端子５は、第２の導体基板１２の真上において、第１の導体基板１１の真上に比べて、半導体素子３および接続材７Ｂの図１の上下方向の厚みの和の分だけ図１の下側に配置されている。
　端子５は、平面視においてたとえば第１の導体基板１１から第２の導体基板１２に向かう方向に長く延びる矩形状の板状導体である。端子５は、たとえば銅などの導体材料により形成されており、０．３ｍｍ以上２．０ｍｍ以下程度の厚みを有している。また端子５は第１の導体基板１１よりも熱容量が大きいことが好ましい。
　半導体装置１００においては、上記の基板材１、半導体素子３および端子５の少なくとも一部は樹脂９により封止されている。すなわち図１においては、基板材１の絶縁基板１０の一方の主表面１０Ａ上、第１の導体基板１１および第２の導体基板１２の表面は、他の部材により接続されている領域以外は封止された樹脂９に覆われている。半導体素子３についても接続材７Ａ，７Ｂにより接合された領域以外は樹脂９に覆われている。端子５は図１の基板材１の右端よりも右側の領域において樹脂９から露出しているが、それ以外の領域においては接合材７Ｂ，７Ｃにより接合された領域を除き樹脂９に覆われている。特に端子５の基板材１と反対側すなわち図１の上側にある第２の端子表面は、少なくとも第１の導体基板１１および第２の導体基板１２の真上において樹脂９に覆われている。したがって端子５の第２の端子表面は、樹脂９の外側にはみ出ている図１の右端の領域を除き、樹脂９の最上面から露出することなく、その全体が樹脂９に覆われている。樹脂９はたとえば一般公知のエポキシ系の樹脂材料である。
　ただし第３の導体基板１３は、樹脂９により封止されることなく、樹脂９から露出している。第３の導体基板１３の図１下側の主表面１３Ｂは、絶縁基板１０の他方の主表面１０Ｂと接合される領域を除く他の領域において樹脂９から露出している。
　基板材１、半導体素子３、第１の導体基板１１、第２の導体基板１２および端子５の少なくとも一部が樹脂９に封止されることにより、これらの各部材と半導体装置１００の外部との電気的な絶縁性を確保することができる。また樹脂９により、異物および湿度などの外乱要因による半導体素子３の他の各部材との短絡を抑制することができる。したがって半導体装置１００の取扱性および信頼性を向上することができる。
　なお図示されないが、図１に示す半導体装置１００の下方、すなわち第３の導体基板１３の下側の主表面１３Ｂは、接続材７とは異なるたとえばグリスなどの接合材により、ヒートシンクなどの冷却器に接続されている。
　半導体素子３は、その上側の表面に、たとえば複数の制御用電極４を有している。制御用電極４は、たとえばアルミニウムからなるワイヤ２１により外部電極２５と電気的に接続されている。外部電極２５は、樹脂９の内側と外側、すなわち半導体装置１００の内側と外側とを電気的に接続するための電極であり、樹脂９の内側の領域から外側の領域まで延びている。これにより、半導体装置１００の外部から、外部電極２５およびワイヤ２１を介して、半導体素子３に電気信号を入力することができる。このため、半導体装置１００の外部から半導体素子３を動作させることができる。
　図２を参照して、図１に示す半導体装置１００の断面図は、実際には半導体装置１００全体の一部であり、たとえば図２の右半分の領域に相当する。なお図２においては説明の都合上、図１の樹脂９については図示省略されている。
　図２に示すように、第２の導体基板１２は平面視において矩形状を有している。しかし第１の導体基板１１は図１に示す第２の導体基板１２の左側に隣り合う領域すなわち図２に示す第２の導体基板１２の下側に隣り合う領域のみならず、そこから図２の左側に隣り合う領域にまで延び拡がっている。第１の導体基板１１の図１の上側に接続される半導体素子３は、第１の導体基板１１上の一部の領域上に矩形状に拡がるように載置されているが、それ以外の領域上には載置されていない。ここでは第１の導体基板１１のうち、平面視においてその上に半導体素子３が接続された領域を第１領域とし、それ以外の領域を第２領域とする。
　基板材１は、絶縁基板１０の一方の主表面１０Ａ上に、第１の導体基板１１および第２の導体基板１２と互いに間隔をあけて配置された第４の導体基板１４をさらに含んでいる。第４の導体基板１４は図２の絶縁基板１０の左上側の領域に配置されており、第１～第３の導体基板１１～１３と同様にたとえば銅からなることが好ましい。図示されないが第４の導体基板１４は一方の主表面１０Ａ上に、たとえば図１と同様のはんだなどの接続材７により直接接合されている。
　第４の導体基板１４の絶縁基板１０と反対側すなわち図１の上側には、他の半導体素子３０が接続されている。図示されないが第４の導体基板１４と他の半導体素子３０とはたとえば図１と同様のはんだなどの接続材７により直接接合されている。他の半導体素子３０は基本的に半導体素子３と同様に、たとえばシリコンとカーボンとを主成分とする化合物からなることが好ましく、たとえば炭化珪素（ＳｉＣ）からなることが好ましい。
　他の半導体素子３０の第４の導体基板１４と反対側すなわち図１の上側には、他の端子５０が接続されている。他の端子５０は端子５と同様に、他の半導体素子３０上の領域から第１の導体基板１１上の第２領域まで、すなわち図２における上側の領域から下側の領域まで延びている。そして他の端子５０は第１の導体基板１１の第２領域と接続されている。すなわち他の端子５０は、他の半導体素子３０の上側の表面と接続材７により接合されるとともに、接続材７により第１の導体基板１１の上側の表面のうち第２領域に相当する領域と接合されている。
　以上により、図２においては、図１に断面図を示す第１の導体基板１１上の半導体素子３と、第１の導体基板１１に隣り合う第２の導体基板１２とが端子５により接続され、図２にてそれらの左側に配置される第４の導体基板１４上の他の半導体素子３０と、第４の導体基板１４に隣り合う第１の導体基板１１の第２領域とが他の端子５０により接続される。第１の導体基板１１には端子５と他の端子５０との双方が電気的に接続されており、これによりハーフブリッジ回路が構成されている。
　すなわち第１の導体基板１１は、半導体素子３が接続されその真上の端子５を他の第２の導体基板１２に接続させる第１領域としての役割と、逆に他の第４の導体基板１４の他の半導体素子３０と接続された他の端子５０を受け入れ接続する第２領域としての役割との双方を共有している。言い換えれば、図２の左側半分の領域における他の半導体素子３０が接続された第４の導体基板１４は図２の右側半分の領域における半導体素子３が接続された第１の導体基板１１に相当し、図２の左側半分の領域における第１の導体基板１１は図２の右側半分の領域における半導体素子３が接続されない第２の導体基板１２に相当する。つまり第１の導体基板１１の第２領域には半導体素子３が直接接続されていない。
　このように第１の導体基板１１が２つの役割を掛け持つように有することにより、２つの役割それぞれを有する部材が別個の部材として形成される場合に比べて、その占める面積を縮小することができる。またハーフブリッジ回路を３つ並列に並べることによりフルブリッジ回路を構成することができ、それを１つの半導体装置１００の中に納めることができる。
　図２に示す半導体素子３および他の半導体素子３０に搭載される上記の電力用半導体装置は、スイッチとしての機能と、還流用ダイオードとしての機能との双方を有するものであり、具体的には、当該電力用半導体装置として、パワーＭＯＳＦＥＴおよびＲＣ－ＩＧＢＴを用いることができる。このようにすれば、スイッチとしての機能を有する電力用半導体装置を搭載する半導体素子と還流用ダイオードとしての機能を有する電力用半導体装置を搭載する半導体素子とが別個のチップとして基板材１上に実装される場合に比べて、チップの数を少なくすることができる。つまりチップの数が少なくなる分だけ、基板材１の上面上を半導体素子３，３０が占める面積を小さくすることができる。このため、半導体素子３，３０の占める面積が小さくなった分だけ、半導体装置１００の平面レイアウトを他の領域に充てることができる。また半導体素子３，３０の占める面積が小さくなった分だけ、半導体素子３と第２の導体基板１２との距離および他の半導体素子３０と第１の導体基板１１の第２領域との距離を短縮することができ、端子５の半導体素子３と第２の導体基板１２とを結ぶ方向の長さおよび他の端子５０の他の半導体素子３０と第２領域との距離を短縮することができる。
　以上の構成を有する本実施の形態の半導体装置１００は、基本的に以下に説明する製造方法により形成される。以下に、半導体装置１００の製造方法の主要部分について説明する。
　第１の導体基板１１、第２の導体基板１２および第３の導体基板１３は、これらを構成する銅中に含まれる微量な酸化物を利用して形成された銅－酸素共晶液相を用いることにより、一方の主表面１０Ａまたは他方の主表面１０Ｂ上に直接接合されることが好ましい。あるいは第１の導体基板１１、第２の導体基板１２および第３の導体基板１３は、チタンおよびジルコニウムなどの活性な金属材料を添加したろう材を用いて一方の主表面１０Ａまたは他方の主表面１０Ｂ上に直接接合されてもよい。このようにして形成された絶縁基板１０と第１の導体基板１１、第２の導体基板１２および第３の導体基板１３との接合界面は、良好な熱伝導性、信頼性および平坦性を有するものとすることができる。
　絶縁基板１０の一方の主表面１０Ａおよび他方の主表面１０Ｂ上への第１の導体基板１１、第２の導体基板１２および第３の導体基板１３の接合方法についてより詳細に説明すれば、まず一方の主表面１０Ａおよび他方の主表面１０Ｂ上に銅の平板が接合される。そして一方の主表面１０Ａ上の銅の平板が通常の写真製版技術すなわち露光および現像処理により回路パターンとして形成される。その回路パターンが薬液によりエッチングされることにより、一方の主表面１０Ａ上には第１の導体基板１１および第２の導体基板１２が形成される。上記の薬液によるエッチング工程の生産性および、一方の主表面１０Ａ上の回路パターンと他方の主表面１０Ｂ上の回路パターンとの厚みおよび形状などの不釣り合いに起因する絶縁基板１０の反りを抑制する観点から、上記の銅の平板の厚みは０．６ｍｍ以下程度とすることが好ましい。
　半導体素子３の上側または下側の表面上のアルミニウムの薄膜からなる電極は、たとえば半導体素子３の製造工程において、一般公知のスパッタ法により形成される。また半導体素子３の上側または下側の表面上のはんだ接合用金属膜は、上記のスパッタ法でアルミニウムの電極が形成された後に、一般公知の湿式めっき法またはスパッタ法などを用いて形成される。
　半導体素子３は第１の導体基板１１上に、はんだなどの接続材７Ａにより接続されている。具体的には上記の電極およびはんだ接合用金属膜が予め半導体素子３に形成されたうえで、第１の導体基板１１上に接続材７Ａとしてのはんだなどが載置され、その上に半導体素子３がさらに重ねられる。そしてそれらを還元雰囲気中で加熱することにより、半導体素子３の裏面と第１の導体基板１１とのはんだ接合が得られる。なお上記の半導体素子３を第１の導体基板１１上に接合する際に、併せて半導体素子３の表面上に接続材７Ｂとしてのはんだなどを設置しておくことで、後述する端子５との接続材を予め形成しておくことができる。以上のように第１の導体基板１１と半導体素子３とをはんだなどの接続材７Ａで接合することにより、第１の導体基板１１と半導体素子３との間を電気的および熱的に良好に接続することができ、かつ両者の接続界面の信頼性を確保することができる。
　端子５は、０．３ｍｍ以上２．０ｍｍ以下程度の厚みを有する銅板を打ち抜き加工により図１のようにその一部の領域においてそれ以外の他の領域よりも（少なくとも半導体素子３および接続材７Ｂの厚みの和の分だけ）下方に配置されるような形状とされ、その後プレス加工により一部の領域が他の領域に対して必要な寸法分だけ下方に配置されるように制御されながら加工されることにより形成される。これにより、端子５の第１の端子表面と第１の導体基板１１の表面との距離、および端子５の第１の端子表面と第２の導体基板１２の表面との距離の関係を任意に調整することができる。端子５がたとえば第１の導体基板１１上と第２の導体基板１２上との間の領域にて屈曲することにより、この領域における端子５が図１の左右方向に延びる角度は絶縁基板１０の一方の主表面１０Ａに沿う方向に対してたとえば３０°以上４５°以下の角度となることが好ましい。
　端子５は、半導体素子３上に予め設置された接続材７Ｂとしてのはんだおよび第２の導体基板１２上に予め設置された接続材７Ｃとしてのはんだの上の所定位置に載置される。この状態で系全体が還元雰囲気中で加熱されることにより、端子５と、半導体素子３と、第２の導体基板１２とが互いに接合される。
　端子５が接続され、ワイヤボンディングにより制御用電極４と外部電極２５とが電気的に接続された後に、系全体が樹脂９により、図１に示す態様となるように封止される。この工程は、たとえばトランスファーモールド法またはポッティング法によりなされることが好ましい。トランスファーモールド法は、系全体がセットされた金型内に流動性のある樹脂が圧入され、加圧および加熱することにより樹脂を硬化させる方法である。またポッティング法は、系全体がセットされた樹脂枠内に流動性のある樹脂を流入し、加熱することで樹脂を硬化させる方法である。
　樹脂９から露出された第３の導体基板１３の下側の表面上にはグリスなどの接合材が塗布され、板バネなどを用いて、第３の導体基板１３の下側の表面上に冷却器が接合される。すなわち第３の導体基板１３と冷却器とは、板バネの押圧力により互いに固定される。これにより、図１に示す半導体装置１００の全体を、良好な熱伝導が容易な冷却器に接続することができる。
　次に、本実施の形態の主要な作用効果について説明する。
　図１を再度参照して、仮に第２経路の第２の導体基板１２の上方の領域にも半導体素子が配置されれば、その半導体素子自体の発熱により、この部分に半導体素子が存在しない本実施の形態の構成に比べて、図１の半導体素子３の上方から端子５を伝わる第２経路での放熱作用が弱められる。また半導体素子を構成する炭化珪素などの材料は、導体材料に比べて熱抵抗が大きいことによっても、第２経路での放熱作用が弱められる。
　そこで本実施の形態においては、半導体素子３の発熱は、以下の２つの経路である第１および第２経路から放熱可能な構成となっている。第１経路は半導体素子３からその下側の接続材７Ａを通ってさらに下方の第１の導体基板１１、絶縁基板１０、第３の導体基板１３に伝わりそこからその下方の図示されない冷却器に伝わる経路である。また第２経路は半導体素子３からその上側の接続材７Ｂを通って端子５に達し、端子５を第２の導体基板１２側に伝わった後、接続材７Ｃ、第２の導体基板１２、絶縁基板１０、第３の導体基板１３に伝わりそこからその下方の図示されない冷却器に伝わる経路である。
　つまり半導体素子３の発熱が、その上側および下側の双方の表面から第１および第２経路を通って放熱される。半導体素子３の上方に伝わる熱についても、端子５を経由する第２経路により、基板材１からその下方の図示されない冷却器へ高効率に放熱させることができる。このため本実施の形態では、半導体素子３の下方から第１経路のみにより放熱される場合に比べて、放熱効率を格段に向上させることができる。
　第２経路による放熱は、端子５が接続材７Ｂにより半導体素子３と接続されるとともに、接続材７Ｃにより第２の導体基板１２と直接接続されていることにより実現される。そのために、端子５の第１の端子表面が、第２の導体基板１２の真上において第１の導体基板１１の真上に比べて基板材１からの図１の上下方向に関する距離が短くなくなるよう屈曲されている。このような構成を有することにより、半導体素子３の上側から端子５に伝わった熱を、より早くに下方へ伝播させて基板材１に到達させることができる。
　半導体素子３の上側および下側の表面の両面からの放熱が可能になり放熱性が向上することは、特により高温条件下で使用され、チップを大面積化することが困難な、炭化珪素などの化合物半導体を用いた半導体装置１００において特に有効である。
　次に、本実施の形態においては、半導体装置１００の最下部に相当する第３の導体基板１３は樹脂から露出している。第３の導体基板１３が樹脂９から露出して絶縁基板１０の他方の主表面１０Ｂの大部分を覆うように形成されていれば、半導体装置１００全体の土台を平坦な第３の導体基板１３の下側の表面部にてしっかりと支えることができる。このことは、第３の導体基板１３は基板材１を構成する絶縁基板１０の他方の主表面上に強固に接合されていることと、絶縁基板１０は基板材１およびこれを含む半導体装置１００の全体の土台をしっかりと支えることができる部材であることとに基づく。このため本実施の形態の基板材１および第３の導体基板１３の構成を適用すれば、半導体装置１００の平行度すなわち平坦性を向上させることができる。
　また本実施の形態においては、半導体装置１００の最下部の導体基板が第３の導体基板１３のみとなっている。つまり第３の導体基板１３のみがその下の冷却器と接続されることとなる。このため、第３の導体基板１３を含む半導体装置１００全体の平行度は、たとえば互いに間隔をあけた複数の導体基板により半導体装置が冷却器と接続される場合に比べて必然的に改善される。
　仮に第３の導体基板１３の部分の平行度が劣っていれば、たとえば第３の導体基板１３の下に冷却器を両者間に絶縁シートを挟んで取り付ける場合、絶縁シートとその上の半導体装置１００との間に空隙が生じ、これらの領域間の熱抵抗が増加する。また第３の導体基板１３と冷却器との間に空隙が生じれば、当該空隙の部分で沿面放電するため、当該領域における絶縁性の確保が困難となる。そこで本実施の形態のように半導体装置１００の最下部である第３の導体基板１３の平坦性が向上されれば、第３の導体基板１３とその下方の冷却器との接合をより良好とすることができる。このため、第３の導体基板１３から冷却器への放熱性をより向上させることができる。
　基板材１に含まれる絶縁基板１０により、基板材１の下方に接続される冷却器と、半導体素子３などとの電気的な絶縁状態を確保することができる。このため基板材１と冷却器とを、グリスまたははんだなどの簡易な部材を用いて接合することができる。
　半導体装置１００に含まれる半導体素子３と第１の導体基板１１および端子５との接続、および端子５と第２の導体基板１２との接続は、はんだなどの接続材７によりなされている。接続材７としては、はんだが用いられることがより好ましい。
　上記の接続材７を用いた半導体装置１００に含まれる各部材間の接続により、各部材の寸法誤差に起因する図１の上下方向の段差（高低差）などの不具合が形成されることがある。この段差（高低差）などは、上記の絶縁基板１０を含む基板材１を土台として平坦性に優れた半導体装置１００が形成されることにより、極力小さくすることが可能である。しかしそれでも微小な段差が残存する。そこで本実施の形態においては、各部材を接続する接続材７として、たとえばスズと銅と銀とを含むはんだが用いられることがより好ましい。このようなはんだを用いれば、上記の微小な段差を容易に埋めることにより相殺することができる。
　またはんだの熱伝導率は約６０Ｗ／ｍ・Ｋ、グリスの熱伝導率は約５Ｗ／ｍ・Ｋ、絶縁シートの熱伝導率は約１０Ｗ／ｍ・Ｋであることから、はんだの熱伝導率はグリスおよび絶縁シートの熱伝導率よりも大きい。このため仮に各部材間に段差が形成され、それがはんだにて相殺しきれなかったとしても、はんだの高い熱伝導性により、各部材間の熱抵抗の増加を抑制することができ、半導体装置１００の信頼性を確保することができる。
　また端子５は第１の導体基板１１よりも熱容量が大きいことが好ましい。第１の導体基板１１および第２の導体基板１２の厚みをたとえば０．６ｍｍ以下と薄くすれば、これらの冷却器との図１の上下方向の距離を小さくすることができ、第１の導体基板１１の定常熱抵抗を低くすることができる。しかしその反面、第１の導体基板１１および第２の導体基板１２の厚みが薄くその熱容量が小さいため、第１の導体基板１１の過渡熱抵抗が高くなる。一方、端子５の厚みは最大で２．０ｍｍ程度となり、第１の導体基板１１および第２の導体基板１２に比べて厚く形成される。このため端子５により過渡熱抵抗を低くすることができる。また端子５と第２の導体基板１２との定常熱抵抗は端子５の断面積に反比例する。このため端子５を厚く形成することにより、端子５と第２の導体基板１２との定常熱抵抗を低くすることができ、第２経路における端子５から第２の導体基板１２への熱伝達を促進することができる。
　その他、本実施の形態においては端子５の第２の端子表面が、第１および第２の導体基板１１，１２の真上において樹脂９に覆われており、樹脂９の最上面から端子５が露出してはいない。このため、樹脂９の最上面すなわち半導体装置１００の最上面の上に、半導体装置１００を固定するための固定器具および制御基板などを載置することができる。
　（実施の形態２）
　図３は図４中のＩＩＩ－ＩＩＩ線に沿う部分の概略断面図である。図３および図４を参照して、本実施の形態の半導体装置２００は、大筋で実施の形態１の半導体装置１００の構成と同様の構成を有している。このため同一の構成要素については同一の参照番号を付し、その説明を繰り返さない。半導体装置２００においては、第１の導体基板１１の真上における端子５の半導体素子３と反対側すなわち図３の上側に第１の熱容量体３１が配置されている。第１の熱容量体３１は、端子５の上側の表面と接続材７Ｄにより接続されている。つまり接続材７は接続材７Ａ，７Ｂ，７Ｃ，７Ｄを有している。
　第１の熱容量体３１は、たとえば銅を母材としたヒートシンクであることが好ましく、銅板の打ち抜き加工によりたとえば直方体状に形成される。第１の熱容量体３１の形成の際には、端子５の形成の際のように屈曲部を形成するためのプレス加工が不要である。このため端子５を形成するための銅板よりも厚い銅板を用いることができ、たとえば厚みが３．０ｍｍの第１の熱容量体３１を形成することができる。接続材７Ｄを用いた端子５と第１の熱容量体３１との接合工程は、たとえば接続材７Ａを用いた半導体素子３と端子５との接合工程と同時に、はんだを用いて行なうことができる。このとき、治具を用いて第１の熱容量体３１の位置精度を確保することが好ましい。
　このようにして形成される第１の熱容量体３１は、第１の導体基板１１および第２の導体基板１２よりも熱容量が大きくなっている。
　以下に、本実施の形態の作用効果を説明する。本実施の形態は、実施の形態１の作用効果に加えて、以下の作用効果を奏する。
　本実施の形態においては、端子５に、第１の導体基板１１および第２の導体基板１２よりも熱容量が大きい第１の熱容量体３１が接続される。このため、端子５と第１の熱容量体３１とを合わせた部分の全体の熱容量を実施の形態１に比べてさらに大きくすることができる。また端子５と第１の熱容量体３１とを合わせた部分の全体の過渡熱抵抗を実施の形態１よりもさらに低くすることができる。その結果、実施の形態１よりもさらに放熱性を向上させることができる。
　第１の熱容量体３１は端子５とは別体として形成され、接続材７Ｄにより端子５と接続されている。このため端子５の形状を複雑にすることなく、端子５と第１の熱容量体３１とを合わせた部材の熱容量を大きくするなどの効果を奏することができる。
　（実施の形態３）
　図５は図６中のＶ－Ｖ線に沿う部分の概略断面図である。図５および図６を参照して、本実施の形態の半導体装置３００は、大筋で実施の形態１，２の半導体装置１００，２００の構成と同様の構成を有している。このため同一の構成要素については同一の参照番号を付し、その説明を繰り返さない。半導体装置３００においては、第２の導体基板１２の真上における端子５の基板材１と反対側すなわち図５の上側に第２の熱容量体３２が配置されている。第２の熱容量体３２は、端子５の上側の表面と接続材７Ｄにより接続されている。つまり接続材７は接続材７Ａ，７Ｂ，７Ｃ，７Ｄを有している。第２の熱容量体３２は第１の熱容量体３１と同様の材質を用いて、同様の製法により、同様のサイズのものが形成されるため、詳細な説明を省略する。
　このようにして形成される第２の熱容量体３２は、第１の導体基板１１および第２の導体基板１２よりも熱容量が大きくなっている。
　以下に、本実施の形態の作用効果を説明する。本実施の形態は、実施の形態１，２の作用効果に加えて、以下の作用効果を奏する。
　本実施の形態においては、端子５に、第１の導体基板１１および第２の導体基板１２よりも熱容量が大きい第２の熱容量体３２が接続される。このため、端子５と第２の熱容量体３２とを合わせた部分の全体の熱容量を実施の形態１に比べてさらに大きくすることができる。また端子５と第１の熱容量体３１とを合わせた部分の全体の過渡熱抵抗を実施の形態１よりもさらに低くすることができる。その結果、実施の形態１よりもさらに放熱性を向上させることができる。
　なお第２の導体基板１２の真上においては（接続材７Ａと接続材７Ｃとの厚みが等しければ）、第１の導体基板１１の真上に比べて、半導体素子３および接続材７Ｂの厚み分だけ、端子５が図５の下側に配置される。このため第２の導体基板１２の真上に厚い第２の熱容量体３２が形成されても、その厚みと接続材７Ｄの厚みの和が半導体素子３および接続材７Ｂの厚みの和以下であれば、第１の導体基板１１上の端子５の最上面に比べて第２の熱容量体３２の最上面の高さが高くなることはない。したがって実施の形態２のように第１の導体基板１１（半導体素子３）の真上に第１の熱容量体３１が形成される場合に比べて、本実施の形態のように第２の導体基板１２の真上に第２の熱容量体３２が形成されれば、半導体装置１００全体の特に図５の上下方向の寸法の増加を抑制することができる。このため実施の形態２よりも半導体装置１００全体を小型化させることができ、その結果、冷却性能をより向上させることができる。
　（実施の形態４）
　図７は図８中のＶＩＩ－ＶＩＩ線に沿う部分の概略断面図である。図７および図８を参照して、本実施の形態の半導体装置４００は、大筋で実施の形態１～３の半導体装置１００～３００の構成と同様の構成を有している。このため同一の構成要素については同一の参照番号を付し、その説明を繰り返さない。半導体装置４００においては、実施の形態１の半導体装置１００と異なり、端子５は第２の導体基板１２と直接接続されてはおらず、両者の間に接続材７以外の部材が配置された構成を有している。具体的には、端子５は第２の導体基板１２と、第３の熱容量体３３を介して接続されている。第３の熱容量体３３は、第１の熱容量体３１および第２の熱容量体３２と同様に銅板の打ち抜き加工により、直方体状のヒートシンクとして形成される。このため第３の熱容量体３３についての詳細な説明を省略する。第３の熱容量体３３は、第２の導体基板１２の基板材１と反対側すなわち図７の上側に、接続材７Ｃにより接続されている。また第３の熱容量体３３は、その図７の上側において、接続材７Ｄにより端子５と接続されている。第３の熱容量体３３は第１の導体基板１１および第２の導体基板１２よりも熱容量が大きいことが好ましい。
　また本実施の形態においては、特に第１の導体基板１１と第２の導体基板１２との厚みが等しい場合、接続材７Ａと半導体素子３と接続材７Ｂとの厚みの和は、接続材７Ｃと第３の熱容量体３３と接続材７Ｄとの厚みの和に等しくなるように形成されることが好ましい。この場合、端子５は第２の導体基板１２上の領域において第１の導体基板１１上の領域よりも基板材１からの距離が短い位置に配置されるように屈曲される必要はなく、端子５は第１の導体基板１１上の領域と第２の導体基板１２上の領域との間で平坦な形状を有している。
　以下に、本実施の形態の作用効果を説明する。本実施の形態は、実施の形態１～３の作用効果に加えて、以下の作用効果を奏する。
　本実施の形態においては、端子５と第２の導体基板１２との間に配置される第３の熱容量体３３をスペーサとして活用することができる。これにより、端子５と第３の熱容量体３３とを合わせた部分の全体の熱容量を実施の形態１に比べてさらに大きくすることができる。また第３の熱容量体３３により、実施の形態１に比べて端子５と第３の熱容量体３３とを合わせた部分の全体の断面積が大きくなるため、過渡熱抵抗と定常熱抵抗との双方を低くすることができ、第２経路による放熱性をさらに向上させることができる。
　また本実施の形態においても実施の形態３と同様に、第２の導体基板１２の真上に第３の熱容量体３３が配置される。このため実施の形態２のように第１の導体基板１１（半導体素子３）の真上に第１の熱容量体３１が形成される場合に比べて、本実施の形態のように第２の導体基板１２の真上に第２の熱容量体３２が形成されれば、半導体装置１００全体の図７の上下方向の寸法の増加を抑制することができる。このため実施の形態２よりも半導体装置１００全体を小型化させることができ、その結果、冷却性能をより向上させることができる。
　さらに、上記のように本実施の形態においては、第３の熱容量体３３の厚みを調整することにより、端子５を平坦な形状とすることができる。このようにすれば、接続材７Ｂおよび接続材７Ｄ上に接続される端子５に下方に屈曲した部分を形成するためのプレス加工を行なう必要がなくなる。したがって、端子５の加工費を削減することができるとともに、端子５の厚みの上限値をより高く設計することができる。具体的には、端子５の厚みを３．０ｍｍとすることができる。プレス加工により銅板を屈曲させるためには、銅板は薄いことが要求されるためである。
　（実施の形態５）
　図９は図１０中のＩＸ－ＩＸ線に沿う部分の概略断面図である。図９および図１０を参照して、本実施の形態の半導体装置５００は、大筋で実施の形態４の半導体装置４００の構成と同様の構成を有している。このため同一の構成要素については同一の参照番号を付し、その説明を繰り返さない。しかし半導体装置５００においては、半導体装置４００の第３の熱容量体３３および接続材７Ｄの部分が、端子５と一体として構成されている。このため端子５は、半導体装置４００の端子５と同様の第１の導体基板１１上の領域から第２の導体基板１２上の領域まで平坦に延びる領域と、半導体装置４００の第３の熱容量体３３および接続材７Ｄの部分に相当する突起部５Ｔとが合体された、銅板からなる構造となっている。言い換えれば、端子５は、基板材１側の第１の端子表面が、第２の導体基板１２の真上において基板材１側に突起する突起部５Ｔを有している。これにより第１の端子表面は、第２の導体基板１２の真上において第１の導体基板１１の真上に比べて基板材１からの距離が短くなっている。
　突起部５Ｔの厚みはたとえば約１ｍｍであり、０．７ｍｍ以上１．３ｍｍ以下とすることが好ましい。
　突起部５Ｔと第２の導体基板１２とは、接続材７Ｃにより接続されている。また第１の導体基板１１上においては、他の実施の形態と同様に、半導体素子３上の接続材７Ｂにより端子５が接続されている。
　以下に、本実施の形態の作用効果を説明する。本実施の形態は、実施の形態４の作用効果に加えて、以下の作用効果を奏する。
　本実施の形態のように突起部５Ｔを設け、実施の形態４の接続材７Ｄおよび第３の熱容量体３３の部分が端子５と一体化することにより、実施の形態４に比べて部品点数を削減することができ、加工を容易にすることができる。またはんだとしての接続材７Ｄの部分が銅板の一部である突起部５Ｔに代えられている。はんだの熱伝導率は約６０Ｗ／ｍ・Ｋであるのに対し、銅の熱伝導率は約４００Ｗ／ｍ・Ｋとはんだに比べて非常に大きい。このため本実施の形態の端子５を適用することにより、実施の形態４に比べて第２経路の放熱性をより向上させることができる。
　以上において、実施の形態２～５の各構成は、たとえば図４，６，８，１０の右側半分の領域に適用したものとして説明しているが、図４，６，８，１０の左側半分の領域にも同様にこれらを適用することができる。この場合、第４の導体基板１４に他の半導体素子３０が接続された領域が図３，５，７，９の第１の導体基板１１に半導体素子３が接続される領域に相当すると考え、第１の導体基板１１の第２領域が図３，５，７，９の第２の導体基板１２上の領域に相当すると考えればよい。
　また実施の形態１～５の図１，３，５，７，９に示す特徴を、図２，４，６，８，１０の左側半分の領域および右側半分の領域のそれぞれに対して適宜組み合わせるように適用してもよい。すなわち以上に説明した各実施の形態における技術的特徴を、技術的に矛盾のない範囲で適宜組み合わせて適用してもよい。
　今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
　１　基板材、３　半導体素子、４　制御用電極、５　端子、５Ｔ　突起部、７，７Ａ，７Ｂ，７Ｃ，７Ｄ　接続材、９　樹脂、１０　絶縁基板、１０Ａ　一方の主表面、１０Ｂ　他方の主表面、１１　第１の導体基板、１２　第２の導体基板、１３　第３の導体基板、２１　ワイヤ、２５　外部電極、３０　他の半導体素子、３１　第１の熱容量体、３２　第２の熱容量体、５０　他の端子、１００，２００，３００，４００，５００　半導体装置。

Claims (12)

  1. 　絶縁基板と、前記絶縁基板の一方の主表面上に互いに間隔をあけて配置された第１および第２の導体基板と、前記絶縁基板の前記一方の主表面と反対側の他方の主表面上に配置された第３の導体基板とを含む基板材と、
    　前記第１の導体基板の前記絶縁基板と反対側に接続される半導体素子と、
    　前記半導体素子の前記第１の導体基板と反対側に接続される端子とを備え、
    　前記端子は前記半導体素子上の領域から前記第２の導体基板の上の領域まで延びるとともに、前記第２の導体基板と接続されており、
    　前記基板材、前記半導体素子および前記端子の少なくとも一部は樹脂により封止され、
    　前記第３の導体基板は前記樹脂から露出している、半導体装置。
  2. 　前記端子は前記第２の導体基板と直接接続される、請求項１に記載の半導体装置。
  3. 　前記端子の前記基板材側にある第１の端子表面は、前記第２の導体基板の真上において前記第１の導体基板の真上に比べて前記基板材からの距離が短い、請求項１または２に記載の半導体装置。
  4. 　前記端子は前記第１の導体基板より熱容量が大きい、請求項１～３のいずれか１項に記載の半導体装置。
  5. 　前記第１の導体基板の真上における前記端子の前記半導体素子と反対側に第１の熱容量体をさらに備え、
    　前記第１の熱容量体は、前記第１および第２の導体基板より熱容量が大きい、請求項１～４のいずれか１項に記載の半導体装置。
  6. 　前記第２の導体基板の真上における前記端子の前記基板材と反対側に第２の熱容量体をさらに備え、
    　前記第２の熱容量体は、前記第１および第２の導体基板より熱容量が大きい、請求項１～５のいずれか１項に記載の半導体装置。
  7. 　前記端子は前記第２の導体基板と、第３の熱容量体を介して接続される、請求項１に記載の半導体装置。
  8. 　前記端子の前記基板材と反対側にある第２の端子表面は、少なくとも前記第１および第２の導体基板の真上において前記樹脂に覆われる、請求項１～７のいずれか１項に記載の半導体装置。
  9. 　前記半導体素子は、スイッチとしての機能と、還流用ダイオードとしての機能との双方を有する、請求項１～８のいずれか１項に記載の半導体装置。
  10. 　前記半導体素子はワイドバンドギャップ半導体からなる、請求項１～９のいずれか１項に記載の半導体装置。
  11. 　前記半導体素子はシリコンとカーボンとを主成分とする化合物からなる、請求項１～１０のいずれか１項に記載の半導体装置。
  12. 　前記基板材は、前記絶縁基板の前記一方の主表面上に、前記第１および第２の導体基板と互いに間隔をあけて配置された第４の導体基板をさらに含み、さらに、
    　前記第４の導体基板の前記絶縁基板と反対側に接続される他の半導体素子と、
    　前記他の半導体素子の前記第４の導体基板と反対側に接続される他の端子とを備え、
    　前記第１の導体基板は、前記半導体素子が接続された第１領域と、前記第１領域以外の第２領域とを含み、
    　前記他の端子は前記他の半導体素子上の領域から前記第１の導体基板上の前記第２領域まで延びるとともに、前記第１の導体基板の前記第２領域と接続される、請求項１～１１のいずれか１項に記載の半導体装置。
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JP7392319B2 (ja) 2019-08-13 2023-12-06 富士電機株式会社 半導体装置
JP2022110873A (ja) * 2021-01-19 2022-07-29 三菱電機株式会社 半導体装置
JP7480715B2 (ja) 2021-01-19 2024-05-10 三菱電機株式会社 半導体装置

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CN209150089U (zh) 2019-07-23

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