WO2012026418A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2012026418A1 WO2012026418A1 PCT/JP2011/068851 JP2011068851W WO2012026418A1 WO 2012026418 A1 WO2012026418 A1 WO 2012026418A1 JP 2011068851 W JP2011068851 W JP 2011068851W WO 2012026418 A1 WO2012026418 A1 WO 2012026418A1
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Definitions
- the present invention relates to a semiconductor device, and more particularly to a semiconductor device including a semiconductor element that generates heat during operation and a substrate on which the semiconductor element is mounted.
- a substrate having a low thermal resistance is used as a substrate for mounting a semiconductor element in order to efficiently release heat generated from a semiconductor element provided therein.
- low thermal resistance substrates that are currently in practical use include metal base substrates composed of metal plates with high thermal conductivity, and HTCC (High-Temperature-Co-fired-Ceramic) substrates such as aluminum nitride substrates and alumina substrates. There is.
- Patent Document 1 discloses that a heat radiating fin (metal plate) having a convex portion is fitted in a hole in a perforated ceramic multilayer wiring board and integrated, It is described that the heat dissipation of the semiconductor element is improved by mounting the semiconductor element on the convex portion of the metal plate.
- Patent Document 1 cannot be applied when mounting a semiconductor element that requires signal input / output on the lower surface, such as an FET (field effect transistor). This is because when a plurality of semiconductor elements are directly mounted on one radiating fin (metal plate), signals cannot be input / output on the lower surface of each semiconductor element.
- FET field effect transistor
- Patent Document 2 discloses that a second substrate having a high thermal conductivity is accommodated in a hole or notch provided in the first insulating substrate, and a semiconductor is formed on the second substrate. It is described that heat dissipation is improved by mounting an element. According to the technique described in Patent Document 2, when an insulating substrate is used as the second substrate, it is possible to mount a semiconductor element that needs to input and output signals on the lower surface.
- Patent Document 2 cannot sufficiently cope with the large current demanded in recent years. That is, in recent years, in the case of an FET configured with a SiC semiconductor or a GaN semiconductor, the heat-resistant temperature reaches 300 ° C. or 500 ° C., and therefore, although a large current can be supplied, it is described in Patent Document 2 The thing cannot cope with this enough. The reason is as follows.
- the insulating substrate used in Patent Document 2 is an HTCC substrate made of aluminum nitride, alumina, or the like whose sintering temperature is about 1600 ° C., and the wiring conductor material provided there can be fired simultaneously.
- a metal having a relatively high melting point such as tungsten or molybdenum must be used.
- these metals having a relatively high melting point such as tungsten and molybdenum have high electrical resistivity and are not suitable for increasing the current.
- the cross-sectional area of the wiring conductor In order to realize the supply of a large current with a metal having a high electrical resistivity, the cross-sectional area of the wiring conductor must be increased. In this case, downsizing of the semiconductor device is hindered.
- a metal having a relatively low electrical resistivity such as silver or copper
- a large current can be supplied with a relatively small cross-sectional area, but the melting point is lower than the sinterable temperature of the HTCC substrate. Therefore, simultaneous firing with the HTCC substrate is impossible.
- a metal such as silver or copper can be used as its material.
- the substrate area is increased, leading to an increase in the size of the semiconductor device.
- an object of the present invention is to provide a semiconductor device that has high heat dissipation and can cope with a large current and a small size.
- the semiconductor device has a relatively high thermal conductivity in which at least one main surface is configured with an electrical insulator and an external conductor is formed on the electrical insulator. And a wiring conductor which is mounted on the one main surface of the heat dissipation board and has a lower thermal conductivity than the heat dissipation board and which contains silver or copper as a main component.
- the wiring board and the lower surface mounted on the one main surface of the heat dissipation board and electrically connected to the wiring conductor via the external conductor, which are formed inside while being electrically connected to the wiring board.
- the electrode includes a semiconductor element that is formed on a mounting surface facing the one main surface of the heat dissipation substrate and generates heat during operation.
- the present invention in simple terms, uses a material suitable for each of the heat dissipation substrate and the wiring substrate by sharing the function as the substrate between the heat dissipation substrate and the wiring substrate. It is intended to solve the above-mentioned problems.
- the heat dissipation substrate is composed of, for example, an aluminum nitride substrate, an alumina substrate, a silicon nitride substrate, or a metal base substrate in which an insulating layer made of ceramic or resin is formed on at least one main surface of a metal plate.
- the wiring board is composed of, for example, a low-temperature sintered ceramic (Low-Temperature-Co-fired-Ceramic: -LTCC) substrate or a resin substrate.
- the wiring substrate and the semiconductor element may be separately disposed on the heat dissipation substrate, but preferably the wiring substrate has a through hole penetrating in a direction orthogonal to the main surface direction.
- the semiconductor element is accommodated in the through hole.
- the semiconductor element has an upper surface electrode on a surface facing the mounting surface, and the upper surface electrode is electrically connected to the wiring conductor through a wire.
- the present invention is more advantageously applied when the heat-resistant temperature of the semiconductor element is 200 ° C. or higher.
- the semiconductor element is a bare type
- the present invention is applied more advantageously.
- the present invention is applied more advantageously when electronic components are mounted on the main surface of the wiring board.
- the semiconductor element is mounted on the heat dissipation substrate having a relatively high thermal conductivity, high heat dissipation can be ensured.
- the external conductor provided on the heat dissipation board is formed on the electrical insulator and is electrically connected to the wiring conductor provided on the wiring board. Signals to the electrodes can be drawn or sent through the outer conductor.
- the external conductor is electrically connected to the wiring conductor of the wiring board, and the wiring conductor is mainly composed of silver or copper, so that low resistance wiring can be realized and it is possible to sufficiently cope with a large current. It becomes.
- the wiring conductor is formed inside the wiring board, the wiring conductor that must be disposed on the surface can be reduced, and it can sufficiently cope with downsizing.
- heat from the semiconductor element is substantially dissipated from the heat dissipation substrate, it is difficult to be transmitted to the wiring substrate, and the wiring substrate has a lower thermal conductivity than the heat dissipation substrate. For this reason, the temperature rise does not occur much on the outer surface of the wiring board. Therefore, heat-sensitive electronic components can be mounted without any problem on the outer surface of the wiring board.
- the entire peripheral region of the through hole in the wiring substrate is defined with respect to the semiconductor element. It can be used for wiring, and efficient wiring can be formed on the wiring board. In addition, since the lateral space of the semiconductor element can be effectively used, the semiconductor element can be reduced in size.
- a plurality of semiconductor elements and a plurality of through holes are provided, and each of the plurality of semiconductor elements is accommodated in each of the plurality of through holes. Wiring between elements can be efficiently realized on the wiring board.
- the semiconductor element has a top electrode on a surface facing the mounting surface, and the top electrode is electrically connected to the wiring conductor via a wire, the top surface of the semiconductor element is not increased without causing an increase in the size of the semiconductor device. Connection between the electrode and the wiring conductor can also be achieved.
- the wiring board has a wiring conductor mainly composed of silver or copper showing a relatively low electrical resistivity, so that it can sufficiently cope with an increase in current, and the wiring conductor Since it can be arranged inside the wiring board, it can sufficiently cope with downsizing.
- an electronic component when an electronic component is mounted on the main surface of the wiring board, heat conduction generated from the semiconductor element can be suppressed by the wiring board having a relatively low thermal conductivity. Therefore, an electronic component having a low heat-resistant temperature can be disposed near the semiconductor element.
- FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. It is a top view which shows the board
- FIG. 3 is a bottom view of the heat dissipation substrate shown in FIG. 2. It is a bottom view which shows the board
- FIG. 1 is shown enlarged as compared with FIGS. 2 to 4. Further, the cross section shown in FIG. 1 corresponds to a cross section taken along line AA in FIG.
- the semiconductor device 1 includes a plurality of semiconductor elements 2 and a substrate 3 on which the semiconductor elements 2 are mounted.
- the substrate 3 has a structure in which the heat dissipation substrate 4 and the wiring substrate 5 are combined and integrated.
- the wiring substrate 5 is provided with a plurality of through holes 6 penetrating in a direction orthogonal to the main surface direction.
- each of the plurality of through holes 6 is provided in each of the plurality of semiconductor elements 2 . Contained.
- four through holes 6 are provided in the wiring board 5.
- the planar dimension of the semiconductor element 2 is 10 mm ⁇ 10 mm
- the through hole 6 is made larger than the semiconductor element 2 so that the planar dimension of the through hole 6 is 11 mm ⁇ 11 mm, thereby defining the through hole 6.
- a predetermined gap 7 is formed between the inner peripheral surface and the outer peripheral surface of the semiconductor element 2.
- the semiconductor element 2 generates heat during operation, and is, for example, a bare type field effect transistor (FET).
- FET bare type field effect transistor
- a lower surface electrode 10 serving as a drain electrode is formed on the mounting surface 9 facing the upper main surface 8 of the heat dissipation substrate 4, that is, the lower surface, and a source electrode and a gate are respectively disposed on the surface facing the mounting surface 9, that is, the upper surface.
- Two upper surface electrodes 11 and 12 serving as electrodes are formed.
- the heat dissipation substrate 4 is composed of, for example, an HTCC substrate such as an aluminum nitride substrate, an alumina substrate, or a silicon nitride substrate, and preferably has a thermal conductivity of 10 W / (m ⁇ K) or more. Since the heat dissipating substrate 4 is composed of the HTCC substrate as described above, the upper main surface 8 and the lower main surface 13 are composed of an electrical insulator.
- FIGS. 1 and 2 As shown in FIGS. 1 and 2, four outer conductors 14 are formed on the upper main surface 8 of the heat dissipation substrate 4, and four junctions for joining to the wiring substrate 5 are formed. A pad 15 is formed. The four outer conductors 14 are electrically insulated from each other. As shown in FIGS. 1 and 3, a bonding pad 16 for bonding to a mother board or chassis (not shown) is formed on the lower main surface 13 over substantially the entire surface.
- the thickness of the heat dissipation substrate 4 is 0.635 mm, and the thickness of each of the outer conductor 14 and the bonding pads 15 and 16 is 0.3 mm.
- the outer conductor 14 and the bonding pads 15 and 16 are mainly composed of, for example, copper or aluminum.
- the semiconductor element 2 is mounted on the upper main surface 8 of the heat dissipation board 4. More specifically, the lower surface electrode 10 of each of the four semiconductor elements 2 is electrically connected to the corresponding external conductor 14 of the heat dissipation board 4 via a conductive bonding material 17 such as solder. Yes.
- the wiring board 5 is mounted on the upper main surface 8 of the heat dissipation board 4.
- the wiring substrate 5 is composed of, for example, an LTCC substrate or a resin substrate, and has a thermal conductivity lower than that of the heat dissipation substrate 4, for example, 5 W / (m ⁇ K) or less, preferably 3 W / (m ⁇ K) or less.
- a wiring conductor 18 mainly composed of silver or copper is formed on the wiring substrate 5.
- the wiring substrate 5 preferably has a laminated structure, and many portions of the wiring conductor 18 are disposed inside the wiring substrate 5.
- the wiring conductor 18 has a lead portion 20 formed on the lower main surface 19 of the wiring substrate 5 and in the vicinity of each of the through holes 6.
- the conductive conductor 21 is electrically connected to the outer conductor 14 on the heat dissipation board 4.
- the bonding pad 22 is mainly composed of, for example, copper or silver. As shown in FIG. 1, the bonding pad 22 is bonded to the bonding pad 15 via a conductive bonding material 23 such as solder, so that the wiring substrate 5 is mechanically connected to the heat dissipation substrate 4. Fixed to.
- the wiring conductor 18 has lead portions 25 and 26 on the upper main surface 24 of the wiring substrate 5 and in the vicinity of each of the through holes 6.
- the upper surface electrode 11 serving as one of the source electrode and the gate electrode of the semiconductor element 2 is electrically connected to the lead portion 25 of the wiring conductor 18 via the wire 27, and the upper surface electrode 12 serving as the other is connected to the wire It is electrically connected to the lead-out portion 26 of the wiring conductor 18 through 28.
- a plurality of electronic components 29 are mounted on the upper main surface 24 of the wiring board 5. Although not shown, these electronic components 29 are electrically connected to the wiring conductor 18.
- the electronic component 29 is, for example, a capacitor, a resistor, an IC, or the like.
- the semiconductor element 2 is mounted on the heat dissipation substrate 4.
- a solder paste is applied on the outer conductor 14 on the heat dissipation substrate 4, and then the semiconductor element 2 is disposed at a predetermined position on the heat dissipation substrate 4.
- a high temperature solder paste such as Bi-0.15Cu solder is used.
- the reflow process is performed at a temperature of 320 ° C., for example.
- SiC semiconductor or a GaN semiconductor having a heat resistant temperature of up to 300 ° C. it is preferable to use high-temperature solder for mounting the semiconductor element 2 as described above.
- the wiring substrate 5 is mounted on the heat dissipation substrate 4, and the electronic component 29 is mounted on the upper main surface 24 of the wiring substrate 5.
- a solder paste is applied on the outer conductor 14 and the bonding pad 15 on the heat dissipation board 4 and on predetermined conductive pads on the upper main surface 24 of the wiring board 5.
- the wiring board 5 and the electronic component 29 are disposed thereon.
- the solder paste for example, a low-temperature solder paste such as M705 solder is used. Then, the reflow treatment is performed at a temperature of 240 ° C., for example.
- wire bonding is performed between the semiconductor element 2 and the wiring substrate 5, and connection by the wires 27 and 28 is achieved.
- the semiconductor device 1 is manufactured as described above.
- the temperature rise of the semiconductor element 2 is suppressed. Since the semiconductor element 2 is mounted on the heat dissipation substrate 4 having a low thermal resistance, the heat generated during operation is efficiently transmitted to the heat dissipation substrate 4, and the temperature rise of the semiconductor element 2 is suppressed. The accompanying characteristic deterioration is suppressed.
- the semiconductor element 2 is an FET composed of, for example, a SiC semiconductor or a GaN semiconductor
- the heat-resistant temperature may reach 200 ° C. or higher, or even 300 ° C. or 500 ° C.
- Such a high heat-resistant temperature means that a large current can be supplied to the semiconductor element 2.
- the semiconductor device 1 includes a wiring substrate 5, and the wiring substrate 5 can be composed of an LTCC substrate or a resin substrate. Therefore, silver or copper having a relatively low melting point but a relatively low melting point is a main component.
- the wiring conductor 18 can be arranged inside.
- the wiring conductor 18 can be disposed inside the wiring board 5, and thus the size can be reduced. Note that, in the wiring conductor 18, a wiring having a thickness of, for example, 100 ⁇ m or more is formed at a location where a large current needs to flow.
- the semiconductor device 1 it is possible to cope with the semiconductor element 2 in which the lower surface electrode 10 is formed on the mounting surface 9 that is the lower surface thereof and the lower surface has an electrical flow. .
- the heat dissipation substrate 4 on which the semiconductor element 2 is mounted has at least one main surface made of an electrical insulator, and is connected to the lower surface electrode 10 of each of the plurality of semiconductor elements 2 on the electrical insulator.
- the outer conductors 14 are formed in a state of being electrically insulated from each other.
- FIG. 5 elements corresponding to the elements shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.
- the semiconductor device 31 shown in FIG. 5 is different from that of the first embodiment in the configuration of the heat dissipation substrate 34 among the heat dissipation substrate 34 and the wiring substrate 5 constituting the substrate 3. Other configurations are the same as those in the first embodiment.
- the heat dissipation substrate 34 includes a metal plate 35 made of a metal having a relatively high thermal conductivity such as silver or copper, and a metal base having ceramic insulating layers 36 and 37 formed on both main surfaces of the metal plate 35. Consists of a substrate.
- the heat dissipation substrate 34 preferably has a thermal conductivity of 50 W / (m ⁇ K) or more. The heat dissipation substrate 34 can easily achieve higher thermal conductivity than the heat dissipation substrate 4 in the first embodiment.
- the outer conductor 14 and the bonding pad 15 are formed on the ceramic insulating layer 36 constituting the upper main surface 8 of the heat dissipation substrate 34, and the bonding pad is formed on the ceramic insulating layer 37 constituting the lower main surface 13. 16 is formed.
- ceramic insulating layers 36 and 37 made of LTCC having a thickness of 100 ⁇ m are formed on both main surfaces of a metal plate 35 made of a copper plate having a thickness of 0.80 mm, and the ceramic insulating layers 36 and 37 are further formed.
- the outer conductor 14, the bonding pad 15, and the bonding pad 16 made of copper having a thickness of 0.3 mm are formed thereon.
- the heat dissipation substrate 34 a structure in which the ceramic insulating layer 37 and the bonding pad 16 described above are omitted and the lower main surface of the metal plate 35 is exposed may be employed. Further, as the insulating layer formed on the main surface of the metal plate 35, a resin insulating layer may be used instead of the ceramic insulating layer. As the resin used in that case, a resin having high heat resistance such as polyimide is preferable, and a filler having high thermal conductivity is preferably contained in the resin.
Abstract
Description
2 半導体素子
4,34 放熱用基板
5 配線用基板
6 貫通孔
9 実装面
10 下面電極
11,12 上面電極
14 外部導体
15,16,22 接合用パッド
17,21,23 導電性接合材
27,28 ワイヤ
29 電子部品
35 金属板
36,37 セラミック絶縁層
Claims (8)
- 少なくとも一方の主面が電気絶縁体をもって構成され、かつ前記電気絶縁体上に外部導体が形成された、比較的高い熱伝導率を有する放熱用基板と、
前記放熱用基板の前記一方の主面上に実装され、前記放熱用基板よりも低い熱伝導率を有し、かつ銀または銅を主成分とする配線導体が前記外部導体に電気的に接続された状態で内部に形成された、配線用基板と、
前記放熱用基板の前記一方の主面上に実装され、かつ前記配線導体に前記外部導体を介して電気的に接続された下面電極が前記放熱用基板の前記一方の主面に対向する実装面上に形成された、動作時に発熱を生じる半導体素子と
を備える、半導体装置。 - 前記配線用基板は主面方向に直交する方向に貫通する貫通穴を有し、前記半導体素子は前記貫通穴内に収容されている、請求項1に記載の半導体装置。
- 複数個の前記半導体素子を備え、前記配線用基板は複数個の前記貫通穴を有し、前記複数個の半導体素子の各々は前記複数個の貫通穴の各々内に収容されている、請求項2に記載の半導体装置。
- 前記半導体素子は、前記実装面に対向する面に上面電極を有し、前記上面電極はワイヤを介して前記配線導体と電気的に接続されている、請求項1ないし3のいずれかに記載の半導体装置。
- 前記半導体素子は、耐熱温度が200℃以上である、請求項1ないし4のいずれかに記載の半導体装置。
- 前記半導体素子は、ベアタイプのものである、請求項1ないし5のいずれかに記載の半導体装置。
- 前記放熱用基板は、窒化アルミニウム基板、アルミナ基板、窒化珪素基板、または金属板の少なくとも一方主面にセラミックまたは樹脂からなる絶縁層が形成された金属ベース基板のいずれかからなり、前記配線用基板は、低温焼結セラミック基板または樹脂基板からなる、請求項1ないし6のいずれかに記載の半導体装置。
- 前記配線用基板の主面に実装された電子部品をさらに備える、請求項1ないし7のいずれかに記載の半導体装置。
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CN2011800413719A CN103081099A (zh) | 2010-08-27 | 2011-08-22 | 半导体装置 |
JP2012530656A JP5672305B2 (ja) | 2010-08-27 | 2011-08-22 | 半導体装置 |
US13/776,752 US9030005B2 (en) | 2010-08-27 | 2013-02-26 | Semiconductor device |
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JP2019506753A (ja) * | 2016-02-24 | 2019-03-07 | アーベーベー・シュバイツ・アーゲー | 多層回路基板に基づくパワーモジュール |
JP2020178057A (ja) * | 2019-04-19 | 2020-10-29 | シチズン時計株式会社 | 回路基板及びその回路基板を用いた発光装置 |
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