CN103081099A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN103081099A
CN103081099A CN2011800413719A CN201180041371A CN103081099A CN 103081099 A CN103081099 A CN 103081099A CN 2011800413719 A CN2011800413719 A CN 2011800413719A CN 201180041371 A CN201180041371 A CN 201180041371A CN 103081099 A CN103081099 A CN 103081099A
Authority
CN
China
Prior art keywords
substrate
wiring
semiconductor element
heat transmission
interarea
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011800413719A
Other languages
English (en)
Inventor
守屋要一
金森哲雄
八木幸弘
杉本安隆
高田隆裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Publication of CN103081099A publication Critical patent/CN103081099A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48101Connecting bonding areas at the same height, e.g. horizontal bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48153Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/48155Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48157Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01019Potassium [K]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]

Abstract

本发明涉及具备在动作时会发热的半导体元件和安装该半导体元件的基板的半导体装置,在该半导体装置中,能实现小型化且提高电流强度,并且能通过朝向基板的下表面来实现半导体元件的电连接。通过散热用基板(4)和布线用基板(5)来分担作为基板的功能,其中,该散热用基板(4)具有较高的导热率,且该散热用基板的两个主面(8,13)由电绝缘体来构成,在电绝缘体上形成有外部导体(14);该布线用基板(5)安装于该散热用基板(4)的上方主面(8)上,且该布线用基板(5)具有比散热用基板(4)低的导热率,在该布线用基板(5)的内部形成有布线导体(18),该布线导体(18)以银或铜为主要成分且与外部导体(14)电连接。在散热用基板(4)的上方主面(8)上、且在设于布线用基板(5)的通孔(6)内,安装半导体元件(2)。半导体元件(2)具有下表面电极(10),该下表面电极(10)经由外部导体(14)与布线导体(18)电连接。

Description

半导体装置
技术领域
本发明涉及半导体装置,特别涉及具备在动作时会发热的半导体元件和安装该半导体元件的基板的半导体装置。
背景技术
在半导体装置中,为了有效地排出由该半导体装置中所具备的半导体元件产生的热,使用热阻较低的基板来作为用于安装半导体元件的基板。作为当前实际使用的热阻较低的基板,例如有:由导热率较高的金属板构成的金属基底基板、氮化铝基板、铝基板等HTCC(High Temperature Co-firedCeramic:高温共烧陶瓷)基板。
例如日本专利公开昭61-212045号公报(专利文献1)中记载了如下技术:即,在开孔的陶瓷多层布线基板的孔内嵌入具有凸部的散热片(金属板)以形成为一体,通过在散热片(金属板)的凸部装载半导体元件,由此提高了半导体元件的散热性。
然而,专利文献1所记载的技术并不适用于如下情况:即,例如安装像FET(场效应晶体管)那样,需要在下表面进行信号的输入输出的半导体元件的情况。这是因为,在一块散热片(金属板)上直接装载多个半导体元件,在此情况下,无法在各个半导体元件的下表面进行信号的输入输出。
关于这一点,日本专利公开平5-315467号公报(专利文献2)记载了如下技术:即,在设于第1绝缘基板的孔部或切口部,容纳有导热率较高的第2基板,通过在第2基板上安装半导体元件,由此提高散热性。根据该专利文献2所记载的技术,在应用绝缘基板来作为第2基板的情况下,能安装需要在下表面进行信号的输入输出的半导体元件。
但是,专利文献2所记载的技术无法充分地应对近年来对于提高电流强度的要求。也就是说,近年来,在由SiC半导体或GaN半导体构成的FET的情况下,由于其耐热温度达到了300℃或500℃,尽管能提供高强度电流,但是专利文献2所记载的技术无法充分地与此应对。其理由如下所述。
在专利文献2中所使用的绝缘基板是以烧结温度大约为1600℃的氮化铝或铝等为材料的HTCC基板,作为设于该HTCC基板上的布线导体的材料,为了能同时进行烧结,必须使用钨或钼等有较高熔点的金属。但是,诸如钨或钼等有较高熔点的金属,其电阻率较高,无法应对提高电流强度的要求。
此外,为了使用电阻率较高的金属来实现高强度电流的提供,必须扩大布线导体的截面积,在这种情况下,阻碍了半导体装置的小型化。
另一方面,在银或铜等具有较低电阻率的金属的情况下,虽然能以较小的截面积来提供高强度电流,但是由于熔点比HTCC基板的可烧结温度更低,不能与HTCC基板同时进行烧结。此外,如果是附加在基板表面的布线导体,则可以使用银或铜等金属作为其材料。但是,只在基板表面使用银或铜等金属来形成布线导体,在此情况下,导致基板面积变大,且导致半导体装置的尺寸变大。
在专利文献1中所记载的方案中也同样具有上述问题。由于在专利文献1所记载的陶瓷多层布线基板中使用了铝基板,因此,在内部的布线导体中无法使用银或铜等低电阻金属。
现有技术文献
专利文献
专利文献1:日本专利公开昭61-212045号公报
专利文献2:日本专利公开平5-315467号公报
发明内容
发明所要解决的问题
由此,本发明的目的在于提供一种散热性强、且能应对提高电流强度和小型化要求的半导体装置。
解决技术问题所采用的技术方案
为了解决上述技术问题,本发明所涉及的半导体装置具备:散热用基板,该散热用基板具有较高的导热率,且该散热用基板的至少一个主面由电绝缘体构成,在电绝缘体上形成有外部导体;布线用基板,该布线用基板安装于该散热用基板的所述一个主面上,且该布线用基板具有比所述散热用基板低的导热率,在该布线用基板的内部形成有布线导体,该布线导体以银或铜为主要成分且与所述外部导体电连接;以及半导体元件,该半导体元件在动作时会发热,该半导体元件安装于散热用基板的所述一个主面上且具有下表面电极,该下表面电极经由外部导体与布线导体电连接且形成在与散热用基板的上述一个主面相对的安装面上。
如上所述,简单来说,本发明通过散热用基板和布线用基板来分担作为基板的功能,从而能使用散热用基板和布线用基板采用各自适宜的材料,解决了上述问题。
散热用基板例如由氮化铝基板、铝基板、氮化硅基板、或在金属板的至少一个主面形成有由陶瓷或树脂组成的绝缘层的金属基底基板中的任一个基板所构成。另一方面,布线用基板由例如低温烧结陶瓷(LowTemperature Co-fired Ceramic:LTCC)基板或树脂基板所构成。
在本发明中,可以在散热用基板上分别配置布线用基板和半导体元件,但是也可优选为布线用基板具有沿着与主面方向垂直的方向贯穿的通孔,半导体元件容纳于通孔内。在这种情况下,进一步优选为具有多个半导体元件和多个通孔,多个半导体元件分别容纳于多个通孔内。
另外,优选为半导体元件在与所述安装面相对的面上具有上表面电极,上表面电极经由引线与布线导体电连接。
当半导体元件的耐热温度在200℃以上时,能更有利地应用于本发明。
另外,当半导体元件为裸片型时,能更有利地应用于本发明。
另外,在布线用基板的主面安装电子元器件时,能更有利地应用于本发明。
发明的效果
根据本发明,由于半导体元件安装在具有较高的导热率的散热用基板上,因此,能确保较高的散热性。
另外,由于设于散热用基板的外部导体形成在电绝缘体上,另外,与设于布线用基板的布线导体电连接,因此,来自半导体元件的下表面电极的信号或者发送给下表面电极的信号能通过所述外部导体引出或送入。
另外,由于所述外部导体与布线用基板的布线导体电连接,且布线导体以银或铜为主要成分,因此,能实现低电阻布线,充分应对提高电流强度的要求。
另外,由于所述布线导体形成于布线用基板的内部,因此,能减少必须配置于表面的布线导体,充分应对小型化的要求。
另外,由于来自半导体元件的热量实质上从散热用基板进行散热,因此,难以传导到布线用基板,而且,布线用基板具有比散热用基板更低的导热率。由此,在布线用基板的外表面温度不太会上升。因此,在布线用基板的外表面上无疑能够装载抗热能力较差的电子元器件。
在本发明中,若布线用基板具有沿着与主面方向垂直的方向贯穿的通孔,且半导体元件容纳于通孔内,则布线用基板中的通孔的整个周围区域能用于对半导体元件进行布线,能在布线用基板上形成有效的布线。另外,由于能有效利用半导体元件的侧面的空间,因此,能使半导体元件小型化。
在上述情况下,具有多个半导体元件和多个通孔,且多个半导体元件分别容纳于多个通孔内,在此情况下,在布线用基板上能有效地实现多个半导体元件相互之间的布线。
若半导体元件在与安装面相对的面上具有上表面电极,且上表面电极经由引线与布线导体电连接,则不会致使半导体元件的尺寸变大,而且能实现上表面电极和布线导体之间的连接。
在半导体元件为例如由SiC半导体或GaN半导体所构成的FET那样,在半导体元件的耐热温度在200℃以上的情况下,虽然能对半导体元件特别提供高强度电流,但即使是在这种情况下,由于布线用基板具有以电阻率较低的银或铜为主要成分的布线导体,因此,能充分地应对提高电流强度的要求,另外,由于布线导体配置于布线用基板的内部,因此,能充分地应对小型化的要求。
另外,在布线用基板的主面安装电子元器件的情况下,具有较低的导热率的布线用基板能抑制由半导体元件所产生的热量的传导。因此,能将耐热温度较低的电子元器件配置在半导体元件的附近。
附图说明
图1是示出本发明的实施方式1所涉及的半导体装置的剖视图。
图2是示出图1中示出的半导体装置所具备的散热用基板的俯视图。
图3是图2中示出的散热用基板的仰视图。
图4是示出图1中示出的半导体装置所具备的布线用基板的俯视图。
图5是示出本发明的实施方式2所涉及的半导体装置的剖视图。
具体实施方式
参照图1至图4,对本发明的实施方式1所涉及的半导体装置1进行说明。此外,图1是用于与图2至图4进行比较而进行放大后的图示。另外,图1中示出的截面相当于图2中沿着线A-A的截面。
如图1所示,半导体装置1具备多个半导体元件2和用于安装半导体元件2的基板3。基板3具有将散热用基板4和布线用基板5集成为一体的结构。
在布线用基板5上设有沿着与其主面方向垂直的方向而贯穿的多个通孔6,多个半导体元件2分别容纳于这些多个通孔6内。此外,在图示的实施方式中,由图4可知,在布线基板5上设有4个通孔6。例如,当半导体元件2的平面尺寸为10mm×10mm时,通孔6的平面尺寸为11mm×11mm,通孔6比半导体元件2更大,在对通孔6进行限定的内周面和半导体元件的外周面之间,形成有规定的间隙7。
半导体元件2在动作时会发热、且例如为裸片型的场效应晶体管(FET)。在与散热用基板4的上方主面8相对的安装面9即下表面,形成成为漏极电极的下表面电极10,在与安装面9相对的面即上表面,分别形成成为源极电极和栅极电极的2个上表面电极11和12。
散热用基板4例如由氮化铝基板、铝基板、或氮化硅基板那样的HTCC基板来构成,优选为具有10W/(m·k)以上的导热率。由于散热用基板4如上所述由HTCC基板来构成,因此,其上方主面8和下方主面13由电绝缘体来构成。
散热用基板4的上方主面8上,如图1和图2所示,形成有4个外部导体14,另外还形成有用于与布线用基板5进行接合的4个接合用焊盘15。4个外部导体14相互之间形成为电绝缘状态。在下方主面13上,如图1和图3所示,形成横跨几乎整个面的、且用于与未图示母板或底板的进行接合的接合用焊盘16。
作为一个示例,散热用基板4的厚度为0.635mm,外部导体14、以及接合用焊盘15和16各自的厚度为0.3mm。另外,外部导体14、以及接合用焊盘15和16以例如铜或铝为主要成分。
在散热用基板4的上方主面8上安装半导体元件2。更详细而言,对于4个半导体元件2中的每一个,其下表面电极10经由例如焊锡那样的导电性接合材料17,与散热用基板4的对应的外部导体14进行电连接。
在散热用基板4的上方主面8上安装布线用基板5。布线用基板5由例如LTCC基板或树脂基板来构成,具有比散热用基板4更低的、例如5W/(m·k)以下的导热率,该导热率优选为3W/(m·k)以下。在布线用基板5上,形成以银或铜为主要成分的布线导体18。布线用基板5优选为具有层叠结构,布线导体18的大部分配置于布线用基板5的内部。
另外,布线导体18如图1和图4所示,在布线用基板5的下方主面19上、且在各个通孔6的附近形成引出部20,经由例如焊锡那样的导电性接合材料21,与位于散热用基板4的外部导体14进行电连接。
另外,在布线用基板5的下方主面19上,形成与上述散热用基板4上的4个接合用焊盘15成对的4个接合用焊盘22。接合用焊盘22以例如铜或银为主要成分。如图1所示,接合用焊盘22经由例如焊锡那样的导电性接合材料23,与接合用焊盘15接合,由此,布线用基板5与散热用基板4进行机械式的固定。
布线导体18在布线用基板5的上方主面24上、且在各个通孔6的附近具有引出部25和26。成为半导体元件2的源极电极和栅极电极中的任一个电极的上表面电极11经由引线27,与布线导体18的引出部25进行电连接,成为另一个电极的上表面电极12经由引线28,与布线导体18的引出部26进行电连接。
在布线用基板5的上方主面24上安装多个电子元器件29。虽未图示,但是这些电子元器件29与布线导体18进行电连接。电子元器件29例如是电容器、电阻器、IC等。
为了制造以上所说明的半导体装置1,实施例如如下工序。
首先,在散热用基板4上安装半导体元件2。为此,在散热用基板4的外部导体14上涂敷焊料糊料,接着,在散热用基板4上的规定位置配置半导体元件2。使用例如Bi-0.15Cu焊锡等高温糊料糊剂来作为所述焊料糊剂。然后,例如以320℃的温度进行回流处理。在使用耐热温度达到了300℃的SiC半导体或GaN半导体来作为半导体元件2的情况下,如上所述,优选为在安装半导体元件2时使用高温焊料糊剂。
接着,在散热用基板4上装载布线用基板5,并且,在布线用基板5的上方主面上安装电子元器件29。为此,在散热用基板4的外部导体14和接合用焊盘15以及布线用基板5的上方主面24上的规定的导电焊盘上,涂敷焊料糊剂。接着,在其上配置布线用基板5和电子元器件29。使用例如M705焊锡等低温焊料糊剂来作为上述焊料糊剂。然后,例如以240℃的温度进行回流处理。由此,若在安装布线用基板5和电子元器件29时使用低温焊料糊剂,则能防止在回流时在安装半导体元件2所使用的高温焊料糊剂因再次熔化而向外流出。另外,若以低温焊料糊剂同时对布线用基板5和电子元器件29进行回流处理,则能防止在分别进行回流处理的情况下先使用的低温焊料糊剂因再次熔化而向外流出。而且,若是低温焊料糊剂,则即使是在使用树脂基板来作为布线用基板5的情况下,也能抑制基板的恶化。
接着,在半导体元件2和布线用导体5之间实施引线接合,通过引线27和28实现连接。
如上所述,制造半导体装置1。
根据上述的半导体装置1,能起到以下的作用效果。
首先,能抑制半导体元件2的温度上升。由于半导体元件2安装于热阻较低的散热用基板4上,因此,动作时所产生的热量能有效地传导至散热用基板4,抑制半导体元件2的温度上升,抑制伴随着该温度上升而导致的特性降低。
另外,能应对提高电流强度和小型化的要求。在半导体元件2为例如由SiC半导体或GaN半导体而构成的FET的情况下,耐热温度在200℃以上,而且有时还能达到300℃或500℃。如此高的耐热温度意味着能向半导体元件2提供高强度电流。该半导体装置1具备布线用基板5,由于布线用基板5是由LTCC基板或树脂基板所构成的,因此,能在内部配置布线导体18,其中,布线导体18以具有较低的电阻率、但是熔点较低的银或铜为主要成分。因此,能应对提高电流强度的要求,另外,由于布线导体18能配置于布线用基板5的内部,因此,能实现小型化。此外,在布线导体18中,特别在需要流过高强度电流的位置,形成例如100μm以上的厚度的布线。
另外,根据半导体装置1,也能应对半导体元件2那样的,在其下表面即安装面9上形成下表面电极10,在该下表面还有电流过的元件。这是因为,安装有半导体元件2的散热用基板4的至少一个主面由电绝缘体构成,在该电绝缘体上以相互之间电绝缘的状态来形成多个外部导体14,该外部导体14与半导体元件2的各个下表面电极相连接。
接着,参照图5,对本发明的实施方式2所涉及的半导体装置31进行说明。在图5中,对于与图1中示出的要素相当的要素赋予相同的参考标号,省略重复的说明。
在图5示出的半导体装置31中,在构成基板3的散热用基板34和布线用基板5之中,散热用基板34的结构与实施方式1有所不同。其他结构与实施方式1的情况相同。
散热用基板34由金属基底基板所构成,其中,该金属基底基板具备由例如银或铜那样的导热率较高的金属组成的金属板35,且在该金属板35的两个主面上形成有陶瓷绝缘层36和37。优选为散热用基板34具有50W/(m·k)以上的导热率。与实施方式1中的散热用基板4相比,散热用基板34容易实现更高的导热率。
在散热用基板34的构成上方主面8的陶瓷绝缘层36上形成外部导体14和接合用焊盘15,在构成下方主面13的陶瓷绝缘层37上形成接合用焊盘16。
作为一个示例,散热用基板34具有如下结构:即,在由厚度为0.80mm的铜板组成的金属板35的两个主面上形成由厚度为100μm的LTCC组成的陶瓷绝缘层36和37,而且,在陶瓷绝缘层36和37上形成由厚度为0.3mm的铜组成的外部导体14和接合用焊盘15以及接合用焊盘16。
此外,在散热用基板34上也可以采用如下结构:即,省略上述陶瓷绝缘层37和接合用焊盘16,且使金属板35的下方主面露出。另外,也可以使用树脂绝缘层来代替陶瓷绝缘层,以作为形成在金属板35的主面上的绝缘层。优选为使用聚酰亚胺那样的抗高温的树脂来作为这种情况下所使用的树脂。另外,优选为在树脂中含有导热率高的填料。
标号说明
1、31 半导体装置
2 半导体元件
4、44 散热用基板
5 布线用基板
6 通孔
9 安装面
10 下表面电极
11、12 上表面电极
14 外部导体
15、16、22 接合用焊盘
17、21、23 导电性接合材料
27、28 引线
29 电子元器件
35 金属板
36、37 陶瓷绝缘层

Claims (8)

1.一种半导体装置,其特征在于,具备:
散热用基板,该散热用基板具有较高的导热率,且该散热用基板的至少一个主面由电绝缘体构成,在所述电绝缘体上形成有外部导体;
布线用基板,该布线用基板安装于所述散热用基板的所述一个主面上,且该布线用基板具有比所述散热用基板低的导热率,在该布线用基板的内部形成有布线导体,该布线导体以银或铜为主要成分且与所述外部导体电连接;以及
半导体元件,该半导体元件在动作时会发热,该半导体元件安装于所述散热用基板的所述一个主面上且具有下表面电极,该下表面电极经由所述外部导体与所述布线导体电连接且形成在与所述散热用基板的所述一个主面相对的安装面上。
2.如权利要求1所述的半导体装置,其特征在于,
所述布线用基板具有沿着与主面方向垂直的方向贯穿的通孔,所述半导体元件容纳于所述通孔内。
3.如权利要求2所述的半导体装置,其特征在于,
具备多个所述半导体元件,所述布线用基板具有多个所述通孔,多个所述半导体元件分别容纳于多个所述通孔内。
4.如权利要求1至3中任一项所述的半导体装置,其特征在于,
所述半导体元件在与所述安装面相对的面上具有上表面电极,所述上表面电极经由引线与所述布线导体电连接。
5.如权利要求1至4中任一项所述的半导体装置,其特征在于,
所述半导体元件的耐热温度在200℃以上。
6.如权利要求1至5中任一项所述的半导体装置,其特征在于,
所述半导体元件为裸片型。
7.如权利要求1至6中任一项所述的半导体装置,其特征在于,
所述散热用基板是利用氮化铝基板、铝基板、氮化硅基板、或在金属板的至少一个主面形成有由陶瓷或树脂组成的绝缘层的金属基底基板之中的任意一个所构成的,所述布线用基板由低温烧结陶瓷基板或树脂基板所构成。
8.如权利要求1至7中任一项所述的半导体装置,其特征在于,
还具备安装于所述布线用基板的主面的电子元器件。
CN2011800413719A 2010-08-27 2011-08-22 半导体装置 Pending CN103081099A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010190332 2010-08-27
JP2010-190332 2010-08-27
PCT/JP2011/068851 WO2012026418A1 (ja) 2010-08-27 2011-08-22 半導体装置

Publications (1)

Publication Number Publication Date
CN103081099A true CN103081099A (zh) 2013-05-01

Family

ID=45723418

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011800413719A Pending CN103081099A (zh) 2010-08-27 2011-08-22 半导体装置

Country Status (4)

Country Link
US (1) US9030005B2 (zh)
JP (1) JP5672305B2 (zh)
CN (1) CN103081099A (zh)
WO (1) WO2012026418A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109148411A (zh) * 2018-08-15 2019-01-04 乐健科技(珠海)有限公司 散热基板及其制备方法
CN111033724A (zh) * 2017-09-07 2020-04-17 株式会社村田制作所 电路块集合体
CN112259507A (zh) * 2020-10-21 2021-01-22 北京轩宇空间科技有限公司 一种异质集成的系统级封装结构及封装方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014219759A1 (de) * 2014-09-30 2016-03-31 Siemens Aktiengesellschaft Leistungsmodul
JP6305362B2 (ja) * 2015-03-06 2018-04-04 三菱電機株式会社 電力用半導体モジュール
JP7145075B2 (ja) * 2016-02-24 2022-09-30 ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト 多層回路基板に基づくパワーモジュール
WO2018030192A1 (ja) * 2016-08-10 2018-02-15 株式会社村田製作所 セラミック電子部品
TWI611538B (zh) * 2016-10-25 2018-01-11 旭德科技股份有限公司 封裝載板及其製作方法
CN110462826B (zh) * 2017-03-29 2023-09-19 株式会社村田制作所 功率模块以及功率模块的制造方法
JP6440917B1 (ja) * 2018-04-12 2018-12-19 三菱電機株式会社 半導体装置
CN110798991B (zh) * 2018-08-01 2021-11-16 宏启胜精密电子(秦皇岛)有限公司 埋嵌式基板及其制作方法,及具有该埋嵌式基板的电路板
JP2020178057A (ja) * 2019-04-19 2020-10-29 シチズン時計株式会社 回路基板及びその回路基板を用いた発光装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02177589A (ja) * 1988-12-28 1990-07-10 Fujitsu Ltd セラミック回路基板
US20020185718A1 (en) * 2001-03-13 2002-12-12 Kazuyuki Mikubo Semiconductor device packaging structure
US20030146508A1 (en) * 2002-02-05 2003-08-07 Eing-Chieh Chen Cavity-down ball grid array package with semiconductor chip solder ball
CN100449753C (zh) * 2006-11-17 2009-01-07 陈桂芳 发光二级体封装结构
CN100449745C (zh) * 2003-03-05 2009-01-07 英特尔公司 具有外部连接器侧管芯的热增强电子倒装芯片封装和方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61212045A (ja) 1985-03-18 1986-09-20 Hitachi Ltd 半導体装置
JPH04142068A (ja) * 1990-10-01 1992-05-15 Ibiden Co Ltd 電子部品搭載用基板及びその製造方法
JPH05315467A (ja) 1992-05-06 1993-11-26 Mitsubishi Electric Corp 混成集積回路装置
US5739586A (en) * 1996-08-30 1998-04-14 Scientific-Atlanta, Inc. Heat sink assembly including a printed wiring board and a metal case
US5838545A (en) * 1996-10-17 1998-11-17 International Business Machines Corporation High performance, low cost multi-chip modle package
US6890798B2 (en) * 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
JP3830726B2 (ja) * 2000-04-26 2006-10-11 松下電器産業株式会社 熱伝導基板とその製造方法およびパワーモジュール
JP2003338579A (ja) * 2002-05-22 2003-11-28 Kyocera Corp 放熱板付き配線基板
JP2004063655A (ja) * 2002-07-26 2004-02-26 Toyota Industries Corp 放熱システム、放熱方法、熱緩衝部材、半導体モジュール、ヒートスプレッダおよび基板
JP4114148B2 (ja) * 2002-10-01 2008-07-09 日立金属株式会社 セラミック積層基板および高周波電子部品
JP2004253736A (ja) * 2003-02-21 2004-09-09 Ngk Insulators Ltd ヒートスプレッダモジュール
JP4014528B2 (ja) * 2003-03-28 2007-11-28 日本碍子株式会社 ヒートスプレッダモジュールの製造方法及びヒートスプレッダモジュール
US7579629B2 (en) * 2003-04-01 2009-08-25 Sharp Kabushiki Kaisha Light-emitting apparatus package, light-emitting apparatus, backlight apparatus, and display apparatus
TWI253701B (en) * 2005-01-21 2006-04-21 Via Tech Inc Bump-less chip package
JP4617209B2 (ja) * 2005-07-07 2011-01-19 株式会社豊田自動織機 放熱装置
DE102005053974B3 (de) * 2005-11-11 2007-03-01 Siemens Ag Elektronische Schaltungsanordnung und Verfahren zur Herstellung einer elektronischen Schaltungsanordnung
JP5105042B2 (ja) * 2006-03-23 2012-12-19 イビデン株式会社 多層プリント配線板
JP5100081B2 (ja) * 2006-10-20 2012-12-19 新光電気工業株式会社 電子部品搭載多層配線基板及びその製造方法
JP5294065B2 (ja) * 2009-02-12 2013-09-18 日立金属株式会社 多層セラミック基板およびそれを用いた電子部品並びに多層セラミック基板の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02177589A (ja) * 1988-12-28 1990-07-10 Fujitsu Ltd セラミック回路基板
US20020185718A1 (en) * 2001-03-13 2002-12-12 Kazuyuki Mikubo Semiconductor device packaging structure
US20030146508A1 (en) * 2002-02-05 2003-08-07 Eing-Chieh Chen Cavity-down ball grid array package with semiconductor chip solder ball
CN100449745C (zh) * 2003-03-05 2009-01-07 英特尔公司 具有外部连接器侧管芯的热增强电子倒装芯片封装和方法
CN100449753C (zh) * 2006-11-17 2009-01-07 陈桂芳 发光二级体封装结构

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111033724A (zh) * 2017-09-07 2020-04-17 株式会社村田制作所 电路块集合体
CN111033724B (zh) * 2017-09-07 2023-04-18 株式会社村田制作所 电路块集合体
CN109148411A (zh) * 2018-08-15 2019-01-04 乐健科技(珠海)有限公司 散热基板及其制备方法
CN112259507A (zh) * 2020-10-21 2021-01-22 北京轩宇空间科技有限公司 一种异质集成的系统级封装结构及封装方法
CN112259507B (zh) * 2020-10-21 2024-03-08 北京轩宇空间科技有限公司 一种异质集成的系统级封装结构及封装方法

Also Published As

Publication number Publication date
US9030005B2 (en) 2015-05-12
US20140070394A1 (en) 2014-03-13
WO2012026418A1 (ja) 2012-03-01
JPWO2012026418A1 (ja) 2013-10-28
JP5672305B2 (ja) 2015-02-18

Similar Documents

Publication Publication Date Title
CN103081099A (zh) 半导体装置
EP2391192A1 (en) Multilayer circuit substrate
CN102593081A (zh) 包括散热器的半导体器件
CN108292656B (zh) 半导体模块
US9466542B2 (en) Semiconductor device
US20150206864A1 (en) Semiconductor Device
JPH08148839A (ja) 混成集積回路装置
CN106252332B (zh) 热敏电阻搭载装置及热敏电阻部件
US20220051960A1 (en) Power Semiconductor Module Arrangement and Method for Producing the Same
JP6698301B2 (ja) 配線基板、電子装置および電子モジュール
JP3818310B2 (ja) 多層基板
CN111834307A (zh) 半导体模块
JPWO2020175541A1 (ja) 配線基板、電子装置および電子モジュール
JP2015141952A (ja) 半導体パワーモジュール
TWI831247B (zh) 功率模組及其製作方法
JP6060053B2 (ja) パワー半導体装置
WO2023157604A1 (ja) 半導体装置および半導体装置の実装構造体
JP6818457B2 (ja) 配線基板、電子装置および電子モジュール
JP6973023B2 (ja) 半導体装置
JP6777440B2 (ja) 回路基板および電子装置
JP6538484B2 (ja) 回路基板および電子装置
JP4574071B2 (ja) 放熱部材および半導体素子収納用パッケージ
CN116711074A (zh) 半导体装置
TW202415165A (zh) 內埋式具有陶瓷基板及功率電晶體的熱電分離電路板
TW202402111A (zh) 功率模組及其製作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130501