JP6824913B2 - 電力用半導体装置及びその製造方法 - Google Patents
電力用半導体装置及びその製造方法 Download PDFInfo
- Publication number
- JP6824913B2 JP6824913B2 JP2017566447A JP2017566447A JP6824913B2 JP 6824913 B2 JP6824913 B2 JP 6824913B2 JP 2017566447 A JP2017566447 A JP 2017566447A JP 2017566447 A JP2017566447 A JP 2017566447A JP 6824913 B2 JP6824913 B2 JP 6824913B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- power
- sealing resin
- semiconductor element
- power semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 155
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 229920005989 resin Polymers 0.000 claims description 153
- 239000011347 resin Substances 0.000 claims description 153
- 238000007789 sealing Methods 0.000 claims description 147
- 229910052751 metal Inorganic materials 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 28
- 239000010954 inorganic particle Substances 0.000 claims description 14
- 239000002245 particle Substances 0.000 claims description 12
- 238000000748 compression moulding Methods 0.000 claims description 8
- 239000000945 filler Substances 0.000 description 22
- 230000017525 heat dissipation Effects 0.000 description 8
- 238000009413 insulation Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000001721 transfer moulding Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 5
- 230000020169 heat generation Effects 0.000 description 5
- 235000014676 Phragmites communis Nutrition 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910001111 Fine metal Inorganic materials 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000004519 grease Substances 0.000 description 3
- 230000002706 hydrostatic effect Effects 0.000 description 3
- 239000011231 conductive filler Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000005096 rolling process Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3737—Organic materials with or without a thermoconductive filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48105—Connecting bonding areas at different heights
- H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Description
図1は、本発明の実施の形態1に係る電力用半導体装置を示す下面図である。電力用半導体装置は、上下面ともに封止樹脂1によって封止され、装置両端部からアウターリード2,3が突出したDIPタイプのパッケージである。アウターリード2は電力用アウターリードであり、アウターリード3は制御用アウターリードである。
図14は、本発明の実施の形態2に係る電力用半導体装置を示す断面図である。封止樹脂1の上面には、制御用ダイパッド8の真上であって金属細線12及び制御用半導体素子10が無い領域に第2の窪み22が設けられている。
図16〜20は、本発明の実施の形態3に係る電力用半導体装置の製造方法を示す断面図である。図16〜19は金属細線11〜13が無い領域の断面図であり、図20は金属細線11〜13に沿った断面図である。
図21〜27は、本発明の実施の形態4に係る電力用半導体装置の製造方法を示す断面図である。図21〜26は金属細線11〜13が無い領域の断面図であり、図27は金属細線11〜13に沿った断面図である。
図28は、本発明の実施の形態5に係る電力用半導体装置を示す断面図である。無機物粒子の含有濃度の高い第1の封止樹脂1aが電力用ダイパッド7の周囲に局所的に設けられている。従って、絶縁部15に含まれる無機物粒子の濃度は電力用ダイパッド7の下面において局所的に高くなっている。
Claims (11)
- インナーリードと、前記インナーリードに接続されたアウターリードと、電力用ダイパッドと、制御用ダイパッドとを有し、前記制御用ダイパッドより下側に前記電力用ダイパッドが配置されるように段差が設けられたリードフレームと、
前記電力用ダイパッド上に接合された電力用半導体素子と、
前記インナーリードと前記電力用半導体素子を電気的に接続する第1の金属細線と、
前記制御用ダイパッド上に前記電力用半導体素子の上面より上側に位置するように接合され、前記電力用半導体素子を制御する制御用半導体素子と、
前記電力用半導体素子と前記制御用半導体素子を電気的に接続する第2の金属細線と、
前記インナーリード、前記電力用ダイパッド、前記制御用ダイパッド、前記電力用半導体素子、前記第1の金属細線、前記制御用半導体素子及び前記第2の金属細線を封止する封止樹脂とを備え、
前記封止樹脂は、前記電力用ダイパッドの真下に絶縁部を有し、
前記絶縁部の厚みは前記封止樹脂内の無機物粒子の最大粒径の1〜4倍かつ220μm以下であり、
前記封止樹脂の上面には、前記電力用ダイパッドの真上であって、前記電力用半導体素子に対して前記制御用ダイパッド側に、前記第1の金属細線、前記第2の金属細線及び前記電力用半導体素子が無い領域に第1の窪みが設けられていることを特徴とする電力用半導体装置。 - 前記第1の窪みは、前記電力用ダイパッドの真上であって、前記電力用半導体素子に対して前記制御用ダイパッド側にのみ設けられていることを特徴とする請求項1に記載の電力用半導体装置。
- 前記封止樹脂の上面には、前記制御用ダイパッドの真上であって前記第2の金属細線及
び前記制御用半導体素子が無い領域に第2の窪みが設けられていることを特徴とする請求項1または請求項2に記載の電力用半導体装置。 - 前記絶縁部に含まれる無機物粒子の濃度は、前記電力用ダイパッドの下面から前記封止樹脂の下面に向かって高くなることを特徴とする請求項1〜3の何れか1項に記載の電力用半導体装置。
- 前記封止樹脂は、前記封止樹脂の下面から電力用ダイパッドの上面までの領域における無機物粒子の濃度が、前記電力用半導体素子より上側の領域における無機物粒子の濃度より高いことを特徴とする請求項1〜3の何れか1項に記載の電力用半導体装置。
- 前記絶縁部に含まれる無機物粒子の濃度は、前記電力用ダイパッドの下面において局所的に高くなることを特徴とする請求項1〜3の何れか1項に記載の電力用半導体装置。
- インナーリードと、前記インナーリードに接続されたアウターリードと、電力用ダイパ
ッドと、制御用ダイパッドとを有し、前記制御用ダイパッドより下側に前記電力用ダイパッドが配置されるように段差が設けられたリードフレームを準備する工程と、
前記電力用ダイパッド上に電力用半導体素子を接合させる工程と、
前記制御用ダイパッド上に前記電力用半導体素子の上面より上側に位置するように前記電力用半導体素子を制御する制御用半導体素子を接合させる工程と、
前記インナーリードと前記電力用半導体素子を第1の金属細線により電気的に接続させ
る工程と、
前記電力用半導体素子と前記制御用半導体素子を第2の金属細線により電気的に接続さ
せる工程と、
上金型の第1の摺動部から第1の金型ピンを突出させて、前記電力用ダイパッドの真下に封止樹脂内の無機物粒子の最大粒径の1〜4倍かつ220μm以下の厚みの絶縁部を形成するように、前記電力用半導体素子に対して前記制御用ダイパッド側の前記電力用ダイパッドの上面に接触させた状態で前記リードフレームを前記上金型と下金型で挟み、圧縮モールド成型により前記電力用ダイパッドの下面から前記封止樹脂を充填して、前記インナーリード、前記電力用ダイパッド、前記電力用半導体素子、前記第1の金属細線及び前記第2の金属細線を封止する工程と、
前記第1の金型ピンを引き抜いて、前記第1の摺動部から前記上金型と前記下金型の間
にある揮発分を脱気し、前記封止樹脂を硬化させる工程とを備えることを特徴とする電力
用半導体装置の製造方法。 - 前記第1の金型ピンは、前記電力用半導体素子に対して前記制御用ダイパッド側のみの前記電力用ダイパッドの上面に接触させることを特徴とする請求項7に記載の電力用半導体装置の製造方法。
- 前記上金型の第2の摺動部から第2の金型ピンを突出させて前記制御用ダイパッドの上
面に接触させた状態で前記封止樹脂による封止を行い、
前記第2の金型ピンを引き抜いて前記封止樹脂を硬化させることを特徴とする請求項7又は請求項8に記載の電力用半導体装置の製造方法。 - 前記封止樹脂として、第1の封止樹脂と、前記第1の封止樹脂上に前記第1の封止樹脂
よりも無機物粒子の含有濃度の低い第2の封止樹脂とを供給することを特徴とする請求項7〜9の何れか1項に記載の電力用半導体装置の製造方法。 - 前記第1の封止樹脂を前記下金型に供給し、前記リードフレームを前記下金型上に配置
した状態で前記第2の封止樹脂を供給することを特徴とする請求項10に記載の電力用半
導体装置の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2016/053808 WO2017138092A1 (ja) | 2016-02-09 | 2016-02-09 | 電力用半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2017138092A1 JPWO2017138092A1 (ja) | 2018-06-21 |
JP6824913B2 true JP6824913B2 (ja) | 2021-02-03 |
Family
ID=59562923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017566447A Active JP6824913B2 (ja) | 2016-02-09 | 2016-02-09 | 電力用半導体装置及びその製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US11107746B2 (ja) |
JP (1) | JP6824913B2 (ja) |
CN (1) | CN108604578B (ja) |
DE (1) | DE112016006381T5 (ja) |
WO (1) | WO2017138092A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6824913B2 (ja) * | 2016-02-09 | 2021-02-03 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法 |
US10600724B2 (en) * | 2016-05-10 | 2020-03-24 | Texas Instruments Incorporated | Leadframe with vertically spaced die attach pads |
US10763193B2 (en) * | 2018-10-30 | 2020-09-01 | Hamilton Sundstrand Corporation | Power control modules |
DE102018133456A1 (de) * | 2018-12-21 | 2020-06-25 | Rogers Germany Gmbh | Verfahren zum Verkapseln mindestens eines Trägersubstrats, Elektronikmodul und Werkzeug zum Verkapseln eines Trägersubstrats |
DE102018133434B4 (de) * | 2018-12-21 | 2021-03-25 | Rogers Germany Gmbh | Verfahren zum Verkapseln mindestens eines Trägersubstrats |
DE102018133420A1 (de) * | 2018-12-21 | 2020-06-25 | Rogers Germany Gmbh | Verfahren zum Verkapseln mindestens eines Trägersubstrats, Elektronikmodul und Werkzeug zum Verkapseln eines Trägersubstrats |
CN111834350B (zh) * | 2019-04-18 | 2023-04-25 | 无锡华润安盛科技有限公司 | Ipm的封装方法以及ipm封装中的键合方法 |
JP7156155B2 (ja) * | 2019-04-19 | 2022-10-19 | 三菱電機株式会社 | 半導体モジュール |
JP7359581B2 (ja) * | 2019-07-10 | 2023-10-11 | 株式会社デンソー | 半導体装置 |
CN115763381B (zh) * | 2022-11-17 | 2024-03-08 | 海信家电集团股份有限公司 | 智能功率模块和设备 |
Family Cites Families (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0543475Y2 (ja) | 1987-07-20 | 1993-11-02 | ||
JPH01268159A (ja) | 1988-04-20 | 1989-10-25 | Nec Corp | 樹脂封止半導体装置及び成型用金型 |
JP2752677B2 (ja) | 1989-01-11 | 1998-05-18 | 日本電気株式会社 | 半導体装置の製造方法 |
US5309027A (en) * | 1992-06-15 | 1994-05-03 | Motorola, Inc. | Encapsulated semiconductor package having protectant circular insulators |
JP3014900B2 (ja) | 1993-07-26 | 2000-02-28 | 日東電工株式会社 | 半導体装置 |
JP3378374B2 (ja) | 1993-09-14 | 2003-02-17 | 株式会社東芝 | 樹脂封止型半導体装置の製造方法、樹脂封止型半導体装置及び封止用樹脂シート |
US5641997A (en) * | 1993-09-14 | 1997-06-24 | Kabushiki Kaisha Toshiba | Plastic-encapsulated semiconductor device |
JP3345241B2 (ja) * | 1995-11-30 | 2002-11-18 | 三菱電機株式会社 | 半導体装置 |
JPH10116847A (ja) | 1996-10-15 | 1998-05-06 | Hitachi Ltd | 半導体装置の製造方法およびトランスファモールド装置 |
JPH11307721A (ja) * | 1998-04-23 | 1999-11-05 | Toshiba Corp | パワーモジュール装置およびその製造方法 |
JP3062691B1 (ja) * | 1999-02-26 | 2000-07-12 | 株式会社三井ハイテック | 半導体装置 |
JP3581268B2 (ja) * | 1999-03-05 | 2004-10-27 | 株式会社東芝 | ヒートシンク付半導体装置およびその製造方法 |
KR100403608B1 (ko) | 2000-11-10 | 2003-11-01 | 페어차일드코리아반도체 주식회사 | 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법 |
KR100723454B1 (ko) * | 2004-08-21 | 2007-05-30 | 페어차일드코리아반도체 주식회사 | 높은 열 방출 능력을 구비한 전력용 모듈 패키지 및 그제조방법 |
US7061080B2 (en) * | 2001-06-11 | 2006-06-13 | Fairchild Korea Semiconductor Ltd. | Power module package having improved heat dissipating capability |
JP3740116B2 (ja) * | 2002-11-11 | 2006-02-01 | 三菱電機株式会社 | モールド樹脂封止型パワー半導体装置及びその製造方法 |
JP2005109100A (ja) * | 2003-09-30 | 2005-04-21 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3854957B2 (ja) | 2003-10-20 | 2006-12-06 | 三菱電機株式会社 | 半導体装置の製造方法および半導体装置 |
JP4463146B2 (ja) * | 2005-05-18 | 2010-05-12 | 三菱電機株式会社 | 半導体装置の製造方法 |
US7923827B2 (en) * | 2005-07-28 | 2011-04-12 | Infineon Technologies Ag | Semiconductor module for a switched-mode power supply and method for its assembly |
DE102007017641A1 (de) * | 2007-04-13 | 2008-10-16 | Infineon Technologies Ag | Aushärtung von Schichten am Halbleitermodul mittels elektromagnetischer Felder |
KR101418397B1 (ko) * | 2007-11-05 | 2014-07-11 | 페어차일드코리아반도체 주식회사 | 반도체 패키지 및 그의 제조방법 |
KR101469770B1 (ko) * | 2007-11-21 | 2014-12-09 | 페어차일드코리아반도체 주식회사 | 전력 소자 패키지 및 그 제조 방법 |
KR101524544B1 (ko) * | 2008-03-28 | 2015-06-02 | 페어차일드코리아반도체 주식회사 | 펠티어 효과를 이용한 열전기 모듈을 포함하는 전력 소자패키지 및 그 제조 방법 |
JP5415823B2 (ja) | 2008-05-16 | 2014-02-12 | 株式会社デンソー | 電子回路装置及びその製造方法 |
US7754533B2 (en) * | 2008-08-28 | 2010-07-13 | Infineon Technologies Ag | Method of manufacturing a semiconductor device |
JP2010232578A (ja) | 2009-03-30 | 2010-10-14 | Sanken Electric Co Ltd | 半導体装置の製造方法 |
JP4766162B2 (ja) * | 2009-08-06 | 2011-09-07 | オムロン株式会社 | パワーモジュール |
EP2581937B1 (en) * | 2010-06-11 | 2017-09-06 | Panasonic Intellectual Property Management Co., Ltd. | Resin-sealed semiconductor device and method for manufacturing same |
JP5674346B2 (ja) | 2010-06-15 | 2015-02-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法、半導体装置、半導体装置の保管方法、半導体製造装置 |
JPWO2012011210A1 (ja) * | 2010-07-22 | 2013-09-09 | パナソニック株式会社 | 半導体装置及びその製造方法 |
US9102511B2 (en) * | 2012-06-08 | 2015-08-11 | Texas Instruments Incorporated | Hermetic plastic molded MEMS device package and method of fabrication |
WO2014013697A1 (ja) * | 2012-07-16 | 2014-01-23 | 株式会社デンソー | 電子装置およびその製造方法 |
KR20150060045A (ko) * | 2013-11-25 | 2015-06-03 | 삼성전기주식회사 | 전력 모듈 패키지 및 그 제조 방법 |
KR102041644B1 (ko) * | 2014-01-08 | 2019-11-07 | 삼성전기주식회사 | 전력 모듈 패키지와 이의 제작방법 |
JP6183226B2 (ja) * | 2014-01-17 | 2017-08-23 | 三菱電機株式会社 | 電力用半導体装置の製造方法 |
US10043738B2 (en) * | 2014-01-24 | 2018-08-07 | Silergy Semiconductor Technology (Hangzhou) Ltd | Integrated package assembly for switching regulator |
JP6356456B2 (ja) | 2014-03-27 | 2018-07-11 | デクセリアルズ株式会社 | 熱伝導性シートの製造方法 |
DE112015000183B4 (de) * | 2014-04-30 | 2022-05-05 | Fuji Electric Co., Ltd. | Halbleitermodul und Verfahren zu dessen Herstellung |
CN104617058B (zh) * | 2015-01-23 | 2020-05-05 | 矽力杰半导体技术(杭州)有限公司 | 用于功率变换器的封装结构及其制造方法 |
CN107078067A (zh) * | 2015-03-30 | 2017-08-18 | 瑞萨电子株式会社 | 半导体装置及其制造方法 |
JP6791621B2 (ja) * | 2015-09-11 | 2020-11-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6824913B2 (ja) * | 2016-02-09 | 2021-02-03 | 三菱電機株式会社 | 電力用半導体装置及びその製造方法 |
WO2018154744A1 (ja) * | 2017-02-27 | 2018-08-30 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法 |
US10629520B2 (en) * | 2017-05-29 | 2020-04-21 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing the same |
US10622274B2 (en) * | 2017-10-06 | 2020-04-14 | Industrial Technology Research Institute | Chip package |
-
2016
- 2016-02-09 JP JP2017566447A patent/JP6824913B2/ja active Active
- 2016-02-09 WO PCT/JP2016/053808 patent/WO2017138092A1/ja active Application Filing
- 2016-02-09 CN CN201680081114.0A patent/CN108604578B/zh active Active
- 2016-02-09 US US15/763,232 patent/US11107746B2/en active Active
- 2016-02-09 DE DE112016006381.4T patent/DE112016006381T5/de active Granted
Also Published As
Publication number | Publication date |
---|---|
DE112016006381T5 (de) | 2018-10-18 |
CN108604578A (zh) | 2018-09-28 |
CN108604578B (zh) | 2021-07-16 |
WO2017138092A1 (ja) | 2017-08-17 |
JPWO2017138092A1 (ja) | 2018-06-21 |
US11107746B2 (en) | 2021-08-31 |
US20190057928A1 (en) | 2019-02-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6824913B2 (ja) | 電力用半導体装置及びその製造方法 | |
JP4286465B2 (ja) | 半導体装置とその製造方法 | |
US9716072B2 (en) | Power semiconductor device and method of manufacturing the same | |
US8624408B2 (en) | Circuit device and method of manufacturing the same | |
US10312178B2 (en) | Semiconductor device | |
US10262912B2 (en) | Semiconductor device | |
US11862542B2 (en) | Dual side cooling power module and manufacturing method of the same | |
WO2016125419A1 (ja) | 半導体装置 | |
JP6279162B2 (ja) | 半導体装置およびその製造方法 | |
CN109616460B (zh) | 电力用半导体装置 | |
JP6469660B2 (ja) | 半導体装置の製造方法 | |
JP2010192591A (ja) | 電力用半導体装置とその製造方法 | |
JP6667401B2 (ja) | 電力用半導体装置の製造方法 | |
KR101490751B1 (ko) | 반도체장치 및 그 제조방법 | |
JP2017191826A (ja) | 半導体装置およびその製造方法 | |
JP7072624B1 (ja) | 電力用半導体装置および電力用半導体装置の製造方法 | |
JP2017191807A (ja) | パワー半導体装置およびパワー半導体装置の製造方法 | |
JP5607447B2 (ja) | 回路装置 | |
US20230154811A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
JP2023071502A (ja) | 半導体装置及び半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180228 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190319 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190517 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20191001 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191211 |
|
C60 | Trial request (containing other claim documents, opposition documents) |
Free format text: JAPANESE INTERMEDIATE CODE: C60 Effective date: 20191211 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20191220 |
|
C21 | Notice of transfer of a case for reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C21 Effective date: 20200107 |
|
A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20200117 |
|
C211 | Notice of termination of reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C211 Effective date: 20200121 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20200616 |
|
C22 | Notice of designation (change) of administrative judge |
Free format text: JAPANESE INTERMEDIATE CODE: C22 Effective date: 20200818 |
|
C13 | Notice of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: C13 Effective date: 20200901 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200918 |
|
C23 | Notice of termination of proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C23 Effective date: 20201208 |
|
C03 | Trial/appeal decision taken |
Free format text: JAPANESE INTERMEDIATE CODE: C03 Effective date: 20210112 |
|
C30A | Notification sent |
Free format text: JAPANESE INTERMEDIATE CODE: C3012 Effective date: 20210112 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20210113 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6824913 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |