JP6667401B2 - 電力用半導体装置の製造方法 - Google Patents
電力用半導体装置の製造方法 Download PDFInfo
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- JP6667401B2 JP6667401B2 JP2016161092A JP2016161092A JP6667401B2 JP 6667401 B2 JP6667401 B2 JP 6667401B2 JP 2016161092 A JP2016161092 A JP 2016161092A JP 2016161092 A JP2016161092 A JP 2016161092A JP 6667401 B2 JP6667401 B2 JP 6667401B2
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- 239000004065 semiconductor Substances 0.000 title claims description 69
- 238000000034 method Methods 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229920005989 resin Polymers 0.000 claims description 165
- 239000011347 resin Substances 0.000 claims description 165
- 238000007789 sealing Methods 0.000 claims description 101
- 239000000945 filler Substances 0.000 claims description 42
- 238000002347 injection Methods 0.000 claims description 41
- 239000007924 injection Substances 0.000 claims description 41
- 230000006835 compression Effects 0.000 claims description 35
- 238000007906 compression Methods 0.000 claims description 35
- 239000002245 particle Substances 0.000 claims description 15
- 238000009826 distribution Methods 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 230000005855 radiation Effects 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000001721 transfer moulding Methods 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- 239000010954 inorganic particle Substances 0.000 description 2
- 238000011417 postcuring Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
発明の実施の形態の説明に先立って、一般的なフルモールド構造の電力用半導体装置の構成について説明する。
以下、図1〜図5を用いて本発明に係る実施の形態1について説明する。図1はRC−IGBT5およびICチップ6を搭載し、アルミワイヤ7および細線ワイヤ8をワイヤボンディングしたリードフレーム状態の電力用半導体装置を示す断面図である。なお、以下においては図19および図20を用いて説明した電力用半導体装置90と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、図6〜図8を用いて本発明に係る実施の形態2について説明する。なお、以下においては図19および図20を用いて説明した電力用半導体装置90と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、図9〜図14を用いて本発明に係る実施の形態3について説明する。なお、以下においては図19および図20を用いて説明した電力用半導体装置90と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、図15を用いて本発明に係る実施の形態4について説明する。なお、以下においては図19および図20を用いて説明した電力用半導体装置90と同一の構成については同一の符号を付し、重複する説明は省略する。
次に、図16〜図18を用いて本発明に係る実施の形態5について説明する。なお、以下においては図19および図20を用いて説明した電力用半導体装置90と同一の構成については同一の符号を付し、重複する説明は省略する。
Claims (6)
- 電力用デバイスが搭載されたダイパッドと、
前記ダイパッドに対向して配置され、制御用デバイスが搭載されたリードと、を有した
リードフレームを樹脂で封止した電力用半導体装置の製造方法であって、
(a)下金型の底面に、粒状樹脂を温度と圧力により圧縮し板状に成型された圧縮絶縁板を搭載し、前記電力用デバイスが搭載された主面とは反対側の前記ダイパッドの裏面が前記圧縮絶縁板に接するように前記リードフレームを前記下金型に搭載する工程と、
(b)前記下金型上に上金型を被せ、前記下金型と前記上金型とで構成されるキャビテ
ィ内に、前記キャビティの対向する2つの側面のうち、前記電力用デバイス側となる一方
の側面から溶融した状態の第1の封止樹脂を注入し、前記制御用デバイス側となる他方の
側面から溶融した状態の第2の封止樹脂を注入する工程と、を備え、
前記工程(b)は、
前記第2の封止樹脂として、前記第1の封止樹脂よりも粘度の小さい樹脂を準備する工程を含む、電力用半導体装置の製造方法。 - 前記圧縮絶縁板は、前記ダイパッドと接する主面を覆うように設けられた樹脂膜を備えた請求項1記載の電力用半導体装置の製造方法。
- 前記圧縮絶縁板は、前記リードフレームの封止樹脂に含まれるフィラーの最大粒径の1〜4倍に相当する厚さを備えた請求項1または請求項2に記載の電力用半導体装置の製造方法。
- 前記圧縮絶縁板は、前記ダイパッドの前記裏面から遠ざかるにつれてフィラー濃度が増加し、樹脂濃度が減少するフィラー分布を備えた請求項1から請求項3のいずれか1項に記載の電力用半導体装置の製造方法。
- フィラー量の調整により、前記第2の封止樹脂の粘度は、前記第1の封止樹脂の粘度より小さいことを特徴とする請求項1から請求項4のいずれか1項に記載の電力用半導体装置の製造方法。
- 前記第2の封止樹脂の注入速度は、前記第1の封止樹脂の注入速度より遅いことを特徴とする請求項1から請求項5のいずれか1項に記載の電力用半導体装置の製造方法。
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JP7172338B2 (ja) | 2018-09-19 | 2022-11-16 | 富士電機株式会社 | 半導体装置及び半導体装置の製造方法 |
CN115763381B (zh) * | 2022-11-17 | 2024-03-08 | 海信家电集团股份有限公司 | 智能功率模块和设备 |
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JP4046120B2 (ja) * | 2005-01-27 | 2008-02-13 | 三菱電機株式会社 | 絶縁シートの製造方法およびパワーモジュールの製造方法 |
JP4463146B2 (ja) * | 2005-05-18 | 2010-05-12 | 三菱電機株式会社 | 半導体装置の製造方法 |
TWI462831B (zh) * | 2010-10-06 | 2014-12-01 | Hitachi Chemical Co Ltd | 多層樹脂片及其製造方法、樹脂片層合體及其製造方法、多層樹脂片硬化物、附金屬箔之多層樹脂片、以及半導體裝置 |
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