CN105161474A - 扇出型封装结构及其生产工艺 - Google Patents

扇出型封装结构及其生产工艺 Download PDF

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CN105161474A
CN105161474A CN201510397494.6A CN201510397494A CN105161474A CN 105161474 A CN105161474 A CN 105161474A CN 201510397494 A CN201510397494 A CN 201510397494A CN 105161474 A CN105161474 A CN 105161474A
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dielectric material
blind hole
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CN105161474B (zh
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郭学平
于中尧
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National Center for Advanced Packaging Co Ltd
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • HELECTRICITY
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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Abstract

本发明涉及一种扇出型封装结构及其生产工艺,其特征是:包括芯板,芯板上的槽体中设置芯片,芯片的正面具有焊盘,焊盘上设置凸点;所述芯板、芯片以及位于芯片正面和背面的介质材料压合在一起,芯片正面的焊盘和凸点嵌入介质材料中,芯片与槽体之间的空隙中填充介质材料;所述芯片背面的介质材料外表面设有金属层,在芯片正面的介质材料外表面设有阻焊层,在阻焊层中布置RDL线路层,RDL线路层的焊盘上设有BGA球;在所述芯片正面的介质材料上设有激光盲孔,激光盲孔中填充电镀金属,RDL线路层通过激光盲孔中的电镀金属与芯片正面的凸点互连。本发明排除了有机基板埋置有源芯片对芯片的限制条件,提高器件封装的良率,降低了扇出型封装成本。

Description

扇出型封装结构及其生产工艺
技术领域
本发明涉及一种扇出型封装结构及其生产工艺,属于微电子先进封装技术领域。
背景技术
目前主流的扇出型封装还是基于晶圆工艺基础上的注塑(molding)方式,其中主要的扇出的RDL应用溅射金属薄膜作为种子层或圆片的方式,该结构所制作的封装热管理性能有很大的限制,另外工艺方面也具有成本高,工艺复杂等特点,所以导致了成本高和性能不高等特点。
目前基于基板的芯片埋置的过程中使用化学镀种子层的工艺进行盲孔的金属化,但是在化学镀的过程中对芯片的焊盘(pad)材料有一定的限制。
发明内容
本发明的目的是克服现有技术中存在的不足,提供一种扇出型封装结构及其生产工艺,排除了基板埋置有源芯片对芯片的限制条件,扩大了应用的领域;并且提高器件封装过程中的良率,进一步降低扇出型封装成本。
按照本发明提供的技术方案,所述扇出型封装结构,其特征是:包括芯板,芯板上开设有连通芯板正反面的槽体,槽体中设置芯片,芯片的正面具有焊盘,焊盘上设置凸点;所述芯板、芯片以及位于芯片正面和背面的介质材料压合在一起,芯片正面的焊盘和凸点嵌入介质材料中,芯片与槽体之间的空隙中填充介质材料;所述芯片背面的介质材料外表面设有金属层,在芯片正面的介质材料外表面设有阻焊层,在阻焊层中布置RDL线路层,RDL线路层的焊盘上设有BGA球;在所述芯片正面的介质材料上设有激光盲孔,激光盲孔中填充电镀金属,RDL线路层通过激光盲孔中的电镀金属与芯片正面的凸点互连。
进一步的,所述槽体的高度和宽度与芯片相匹配。
进一步的,所述凸点的表面为平面。
所述扇出型封装结构的生产工艺,其特征是,包括以下步骤:
(1)在芯片的焊盘上植上凸点;
(2)将凸点进行平坦化;
(3)压合备料:使用和芯片厚度相匹配的芯板,在芯板上制作与芯片相匹配的槽体,将芯片嵌入到槽体内;将已经嵌入芯片的芯板放置于两层介质材料中间,介质材料的表面具有铜箔;
(4)将步骤(3)的压合备料层叠好后进行层压,将嵌入有芯片的芯板埋置在两层介质材料中间;
(5)在芯片正面的介质材料上对应芯片焊盘的位置制作激光盲孔,激光盲孔由介质材料的表面延伸至芯片焊盘的表面;
(6)在激光盲孔的内壁进行金属化再通过电镀的方式将激光盲孔全部填充引出芯片上I/O;
(7)在芯片正面介质材料表面的铜箔上制作扇出的RDL线路层;
(8)在芯片正面的介质材料外表面压合阻焊层,在阻焊层上开窗口,露出用于植球的焊盘;
(9)在步骤(8)露出的焊盘上进行植BGA球,从形成整个封装结构。
进一步的,所述凸点为金凸点或铜凸点。
进一步的,所述步骤(4)中,芯片与槽体之间的间隙由介质材料填充,芯片正面的焊盘和凸点嵌入介质材料中。
本发明具有以下优点:
(1)本发明具有很广泛的适用性,能够更好的应用于各类型的芯片;更能够和现有晶圆工艺的扇出型封装技术进行竞争,增强了该技术的市场应用竞争力;
(2)本发明的芯片采用凸点的方式嵌入到封装的介质材料中,然后通过化铜电镀盲孔的方式进行扇出,通过这种方式能够很好地控制良率和可靠性,另外该结构采用的是嵌入式的结构,从而可以解决器件封装过程对贴片工艺设备的依赖,可以节约其设备的成本也适合于大尺寸板级封装;
(3)本发明基于有机基板工艺开展的板级扇出型封装技术,具有成本低,可适用于大规模生产等特点。
附图说明
图1为芯片植球后的示意图。
图2为凸点平坦化后的示意图。
图3为压合备料的示意图。
图4为层压后的示意图。
图5为制作激光盲孔的示意图。
图6为填充激光盲孔的示意图。
图7为制作RDL线路层的示意图。
图8为制作阻焊层的示意图。
图9为本发明的结构示意图。
图中序号:芯板1、槽体2、芯片3、介质材料4、焊盘5、金属层6、阻焊层7、RDL线路层8、BGA球9、激光盲孔10、凸点11。
具体实施方式
下面结合具体附图对本发明作进一步说明。
下文将参考附图更完整地描述本公开内容,其中在附图中显示了本公开内容的实施方式。但是这些实施方式可以用许多不同形式来实现并且不应该被解释为限于本文所述的实施方式。相反地,提供这些实例以使得本公开内容将是透彻和完整的,并且将全面地向本领域的熟练技术人员表达本公开内容的范围。应当注意,虽然在下文将描述一个相对完整的芯片封装器件的制作工艺,但是其中有的工艺步骤是可选的,并且存在替换的实施方式。
如图9所示:所述扇出型封装结构,包括芯板1,芯板1上开设有连通芯板1正反面的槽体2,槽体2中设置芯片3,槽体2的高度和宽度与芯片3相匹配;所述芯片3的正面具有焊盘5和凸点11,凸点11的表面为平面;所述芯板1、芯片3以及位于芯片3正面和背面的介质材料4压合在一起,芯片3正面的焊盘5和凸点11嵌入介质材料4中,芯片3与槽体2之间的空隙中填充介质材料;所述芯片3背面的介质材料4的表面设有金属层6,在芯片3正面的介质材料4的表面设有阻焊层7,在阻焊层7中布置RDL线路层8,RDL线路层8的焊盘上设有BGA球9;在所述芯片3正面的介质材料4上设有激光盲孔10,激光盲孔10中填充电镀金属,RDL线路层8通过激光盲孔10中的电镀金属与芯片3正面的凸点11互连。
所述扇出型封装结构的生产工艺,包括以下步骤:
(1)芯片植球:如图1所示,在芯片3的焊盘5上通过引线键合设备或其他设备植上凸点11,凸点11为金凸点或铜凸点,但并不限制于这两种材料,主要是能够适用于后面的化铜电镀的基板工艺流程;
(2)凸点平坦化:如图2所示,将通过引线键合设备植的凸点11上面留下的尾线通过机械打磨等方式进行平坦化,将凸点11表面制作成平面,从而可以更好的在凸点上面进行激光钻孔以及盲孔电镀等工艺;
(3)压合备料:如图3所示,使用和芯片3厚度相匹配的芯板1,通过激光等方式在芯板1上制作与芯片3相匹配的槽体2,将芯片3嵌入到槽体2内;该槽体2一方面能够将芯片3很好地固定,另一方面也可以保证芯片3的贴装精度;将已经嵌入芯片3的芯板1放置于两层介质材料4中间,介质材料的表面具有铜箔;具体的,介质材料4可以采用半固化片或带铜箔的RCC材料等;
(4)层压:如图4所示,使用高温压机或真空压机将步骤(3)的压合备料层叠好后进行层压,将嵌入有芯片3的芯板1埋置在两层介质材料4中间,芯片3与槽体2之间的间隙由介质材料4填充,从而形成嵌入式埋置的有源芯片的结构;其中,芯片3正面的焊盘5和凸点11嵌入芯片3正面的介质材料4中;
(5)激光盲孔:如图5所示,在芯片3正面的介质材料上对应芯片3焊盘5的位置制作激光盲孔10,激光盲孔10由介质材料4的表面延伸至芯片3焊盘7的表面;
(6)填孔电镀:如图6所示,通过化铜方式在激光盲孔10的内壁进行金属化然后再通过电镀的方式将激光盲孔10全部填充引出芯片上I/O;
(7)扇出线路制作:如图7所示,在芯片3正面介质材料4表面的铜箔上制作扇出的RDL线路层8;
(8)阻焊压合:如图8所示,在芯片3正面的介质材料4外表面压合阻焊层7,阻焊层7可以采用阻焊绿油;在阻焊层7上开窗口,露出用于植球的焊盘;
(9)植球:如图9所示,在步骤(8)露出的焊盘上进行植BGA球9,从形成整个封装结构。
本发明主要是通过在芯片上进行凸点的制作并将凸点平坦化之后进行后续的激光盲孔以及盲孔电镀的工艺,排除了基于有机基板埋置有源芯片对芯片的限制条件,扩大了该技术应用的领域。另外凸点的制作还能够有效的提高器件封装过程中的良率从而进一步降低了扇出型封装成本,更好的支撑该技术应用于更广泛的应用。本发明能够适合于绝大多数芯片的应用,如Al焊盘芯片等等。

Claims (6)

1.一种扇出型封装结构,其特征是:包括芯板(1),芯板(1)上开设有连通芯板(1)正反面的槽体(2),槽体(2)中设置芯片(3),芯片(3)的正面具有焊盘(5),焊盘(5)上设置凸点(11);所述芯板(1)、芯片(3)以及位于芯片(3)正面和背面的介质材料(4)压合在一起,芯片(3)正面的焊盘(5)和凸点(11)嵌入介质材料(4)中,芯片(3)与槽体(2)之间的空隙中填充介质材料;所述芯片(3)背面的介质材料(4)外表面设有金属层(6),在芯片(3)正面的介质材料(4)外表面设有阻焊层(7),在阻焊层(7)中布置RDL线路层(8),RDL线路层(8)的焊盘上设有BGA球(9);在所述芯片(3)正面的介质材料(4)上设有激光盲孔(10),激光盲孔(10)中填充电镀金属,RDL线路层(8)通过激光盲孔(10)中的电镀金属与芯片(3)正面的凸点(11)互连。
2.如权利要求1所述的扇出型封装结构,其特征是:所述槽体(2)的高度和宽度与芯片(3)相匹配。
3.如权利要求1所述的扇出型封装结构,其特征是:所述凸点(11)的表面为平面。
4.一种扇出型封装结构的生产工艺,其特征是,包括以下步骤:
(1)在芯片(3)的焊盘(5)上植上凸点(11);
(2)将凸点(11)进行平坦化;
(3)压合备料:使用和芯片(3)厚度相匹配的芯板(1),在芯板(1)上制作与芯片(3)相匹配的槽体(2),将芯片(3)嵌入到槽体(2)内;将已经嵌入芯片(3)的芯板(1)放置于两层介质材料(4)中间,介质材料的表面具有铜箔;
(4)将步骤(3)的压合备料层叠好后进行层压,将嵌入有芯片(3)的芯板(1)埋置在两层介质材料(4)中间;
(5)在芯片(3)正面的介质材料(4)上对应芯片(3)焊盘(5)的位置制作激光盲孔(10),激光盲孔(10)由介质材料(4)的表面延伸至芯片(3)焊盘(7)的表面;
(6)在激光盲孔(10)的内壁进行金属化再通过电镀的方式将激光盲孔(10)全部填充引出芯片上I/O;
(7)在芯片(3)正面介质材料(4)表面的铜箔上制作扇出的RDL线路层(8);
(8)在芯片(3)正面的介质材料(4)外表面压合阻焊层(7),在阻焊层(7)上开窗口,露出用于植球的焊盘;
(9)在步骤(8)露出的焊盘上进行植BGA球(9),从形成整个封装结构。
5.如权利要求4所述的扇出型封装结构的生产工艺,其特征是:所述凸点(11)为金凸点或铜凸点。
6.如权利要求4所述的扇出型封装结构的生产工艺,其特征是:所述步骤(4)中,芯片(3)与槽体(2)之间的间隙由介质材料(4)填充,芯片(3)正面的焊盘(5)和凸点(11)嵌入介质材料(4)中。
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