CN104538380A - 小间距PoP封装单体 - Google Patents

小间距PoP封装单体 Download PDF

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CN104538380A
CN104538380A CN201410759285.7A CN201410759285A CN104538380A CN 104538380 A CN104538380 A CN 104538380A CN 201410759285 A CN201410759285 A CN 201410759285A CN 104538380 A CN104538380 A CN 104538380A
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陈南南
王宏杰
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明涉及一种小间距PoP封装单体，包括芯片、塑封材料和焊球；其特征是：所述焊球包括铜核球，在铜核球表面镀覆镀层钎料。所述焊球为椭球形、矩形柱形或圆柱形，铜核球为椭球形、矩形柱形或圆柱形。所述封装单体可以采用扇出型晶圆级封装或者基板PoP封装结构。本发明能够解决PoP封装坍塌、偏移的问题，并进一步减小间距，提高I/O数量。

Description

小间距PoP封装单体
技术领域
本发明涉及一种小间距PoP封装单体，属于半导体封装技术领域。
背景技术
作为目前封装高密集成的主要方式，PoP（package on package，层叠封装）得到越来越多的重视。芯片的堆叠是提高电子封装高密化的主要途径之间，PoP设计已经在业界得到比较广泛的开发和应用。
现有技术中，一般采用锡球互连的PoP解决方案，这种结构在坍塌、位移（shift）等方面存在一定难度和不足。基板多层PoP芯片堆叠时，需将锡球与芯片一起塑封，不利于返修。传统的锡球X轴方向尺寸与Y轴尺寸相当，限制了间距时一步减小。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种小间距PoP封装单体，解决PoP封装坍塌、偏移的问题，并进一步减小间距，提高I/O数量。
按照本发明提供的技术方案，所述小间距PoP封装单体，包括芯片、塑封材料和焊球；其特征是：所述焊球包括铜核球，在铜核球表面镀覆镀层钎料。
进一步的，所述焊球为椭球形、矩形柱形或圆柱形，铜核球为椭球形、矩形柱形或圆柱形。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的背面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的正面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
进一步的，所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料全部覆盖基板的背面。
进一步的，所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料部分覆盖基板的背面。
本发明所述的小间距PoP封装单体及PoP封装结构，将非中心对称型球或柱应用于扇出型晶圆级封装或PoP封装，可以解决PoP封装坍塌、偏移的问题，并进一步减小间距，提高I/O数量。
附图说明
图1为本发明所述小间距PoP封装单体第一种实施例的示意图。
图2为本发明所述小间距PoP封装单体第二种实施例的示意图。
图3为本发明所述小间距PoP封装单体第三种实施例的示意图。
图4为本发明所述小间距PoP封装单体第四种实施例的示意图。
图5为本发明所述小间距PoP封装单体第五种实施例的示意图。
图6为本发明所述小间距PoP封装单体第六种实施例的示意图。
图7为本发明所述小间距PoP封装单体第七种实施例的示意图。
图8为本发明所述小间距PoP封装单体第八种实施例的示意图。
图9为本发明所述小间距PoP封装结构第一种实施例的示意图。
图10为本发明所述小间距PoP封装结构第二种实施例的示意图。
具体实施方式
下面结合具体附图对本发明作进一步说明。
实施例一：
如图1所示，本发明包括塑封材料1-1，塑封材料1-1中塑封芯片1-2，芯片1-2的正面与塑封材料1-1的正面平齐，芯片1-2的高度小于塑封材料1-1的高度；在所述塑封材料1-1的正面设置RDL层1-3，RDL层1-3中设置再布线金属走线层1-4，再布线金属走线层1-4上设置UBM层1-5，再布线金属走线层1-4连接UBM层1-5和芯片1-2上的电极；在所述UBM层1-5上设置焊球100，焊球100包括铜核球200，在铜核球200表面镀覆镀层钎料300，镀层钎料300可以采用镍或合金材料（如SAC合金钎料）；所述焊球100为椭球形、矩形柱形或圆柱形，铜核球200为椭球形、矩形柱形或圆柱形。
实施例一在制作时，采用现有技术中常规的方法（fan out WLP face down工艺）进行，具体为：在载体晶圆表面涂覆一层临时键合胶，将芯片1-2的电极面朝下贴片；采用塑封材料1-1将芯片1-2塑封并固化，然后将载体晶圆及塑封材料1-1翻转并去除载体晶圆及临时键合胶；在芯片1-2的电极一面制作RDL层1-3，在RDL层1-3上进行电镀、沉积，制作再布线金属走线层1-4和UBM层1-5；在UBM层1-5上植本发明所述的焊球100，将封装体切割成单个封装单体。
实施例二：
如图2所示，结构同实施例一，其中，在塑封材料1-1中还塑封有金属层2-1，金属层2-1的一表面与塑封材料1-1的正面平齐，金属层2-1的厚度小于塑封材料1-1的高度。
实施例三：
如图3所示，结构同实施例二，其中，在塑封材料1-1中还塑封有金属柱3-1，金属柱3-1的一端连接金属层2-1，另一端与塑封材料1-1的背面平齐。
实施例四：
如图4所示，结构同实施例一，其中，芯片1-2的背面与塑封材料1-1的背面平齐。
实施例四在制作时，采用现有技术（Fan out WLP face up工艺）进行，具体为：在载体晶圆表面涂覆一层临时键合胶，将芯片1-2的电极面朝上贴片；采用塑封材料1-1将芯片1-2塑封并固化，然后去除载体晶圆和临时键合胶；在芯片1-2的电极一面的表面制作RDL层1-3，在RDL层1-3上电镀、沉积，制作再布线金属走线层1-4和UBM层1-5；在UBM层1-5上植本发明所述的焊球100，将封装体切割成单个封装单体。
实施例五：
如图5所示，结构同实施例二，其中，芯片1-2的背面与塑封材料1-1的背面平齐，金属层2-1的一表面与塑封材料1-1的背面平齐，金属层2-1的厚度小于塑封材料1-1的高度。
实施例六：
如图6所示，结构同实施例三，其中，芯片1-2的背面与塑封材料1-1的背面平齐，金属层2-1的一表面与塑封材料1-1的背面平齐，金属层2-1的另一表面与金属柱3-1的一表面连接，金属柱3-1的另一表面与塑封材料1-1的正面平齐。
实施例七：
如图7所示，本发明为基板PoP封装结构，包括基板7-1，在基板7-1上采用塑封材料7-2塑封芯片7-3，在基板7-1的正面设置焊盘7-4，在焊盘7-4上设置焊球100；其中，塑封材料7-2全部覆盖基板7-1的背面。
实施例七在制作时，采用现有技术进行，具体为：在基板7-1进行贴片，将芯片7-3采用塑封材料7-2进行塑封并固化；再将基板7-1及塑封材料7-2翻转，在基板7-1正面的焊盘7-4上植本发明所述的焊球100，再将封装体切割成封装单体。
实施例八：
如图8所示，结构同实施例七，其中，塑封材料7-2部分覆盖基板7-1的背面。
如图9、图10所示，将本发明所述的小间距PoP封装单体进行堆叠、回流，可以得到小间距PoP封装结构；如图9所示，为将实施例四和实施例六所述的封装单体进行进堆叠；如图10所示，为将实施例七和实施例八所述的封装单体进行堆叠。
本发明案采用非中心对称型球（椭球形、矩形柱形、圆柱形等）取向排布应用于Fan out WLP（扇出型晶圆级封装）及PoP工艺，可以解决PoP堆叠加坍塌、偏移问题，并进一步减小间距，提高I/O数量；非对称型焊球的铜核球起到一定的支撑作用，在Y轴方向上达到PoP芯片堆叠的设计需求；同时，对比传统锡球，焊球在X轴方向可以设计很小，且回流前后变化较小，可以满足芯片小间距植球。这样的植球方法及结构，可以应用于PoP多层芯片互连堆叠，有效地解决坍塌、偏移等工艺问题。

Claims (10)

1.一种小间距PoP封装单体，包括芯片、塑封材料和焊球（100）；其特征是：所述焊球（100）包括铜核球（200），在铜核球（200）表面镀覆镀层钎料（300）。
2.如权利要求1所述的小间距PoP封装单体，其特征是：所述焊球（100）为椭球形、矩形柱形或圆柱形，铜核球（200）为椭球形、矩形柱形或圆柱形。
3.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
4.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
5.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的正面与塑封材料的正面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的正面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的背面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
6.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
7.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片和金属层，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的厚度小于塑封材料的高度；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
8.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体包括塑封材料，塑封材料中塑封芯片、金属层和金属柱，芯片的背面与塑封材料的背面平齐，芯片的高度小于塑封材料的高度；所述金属层的一表面与塑封材料的背面平齐，金属层的另一表面与金属柱的一端连接，金属柱的另一端与塑封材料的正面平齐；在所述塑封材料的正面设置RDL层，RDL层中设置再布线金属走线层，再布线金属走线层上设置UBM层，再布线金属走线层连接UBM层和芯片上的电极，在UBM层上设置焊球。
9.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料全部覆盖基板的背面。
10.如权利要求1所述的小间距PoP封装单体，其特征是：所述封装单体为基板PoP封装结构，包括基板，在基板上采用塑封材料塑封芯片，在基板的正面设置焊盘，在焊盘上设置焊球；所述塑封材料部分覆盖基板的背面。
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