CN105428260B - 一种基于载体的扇出2.5d/3d封装结构的制造方法 - Google Patents
一种基于载体的扇出2.5d/3d封装结构的制造方法 Download PDFInfo
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- CN105428260B CN105428260B CN201510970167.5A CN201510970167A CN105428260B CN 105428260 B CN105428260 B CN 105428260B CN 201510970167 A CN201510970167 A CN 201510970167A CN 105428260 B CN105428260 B CN 105428260B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201510970167.5A CN105428260B (zh) | 2015-12-22 | 2015-12-22 | 一种基于载体的扇出2.5d/3d封装结构的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201510970167.5A CN105428260B (zh) | 2015-12-22 | 2015-12-22 | 一种基于载体的扇出2.5d/3d封装结构的制造方法 |
Publications (2)
Publication Number | Publication Date |
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CN105428260A CN105428260A (zh) | 2016-03-23 |
CN105428260B true CN105428260B (zh) | 2017-12-19 |
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CN201510970167.5A Active CN105428260B (zh) | 2015-12-22 | 2015-12-22 | 一种基于载体的扇出2.5d/3d封装结构的制造方法 |
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CN (1) | CN105428260B (zh) |
Families Citing this family (23)
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WO2018044788A1 (en) * | 2016-09-02 | 2018-03-08 | R&D Circuits, Inc. | Method and structure for a 3d wire block |
US10636779B2 (en) | 2017-01-11 | 2020-04-28 | Sj Semiconductor (Jiangyin) Corporation | Packaging device for integrated power supply system and packaging method thereof |
WO2018129908A1 (zh) * | 2017-01-13 | 2018-07-19 | 中芯长电半导体(江阴)有限公司 | 一种双面扇出型晶圆级封装方法及封装结构 |
US10426030B2 (en) | 2017-04-21 | 2019-09-24 | International Business Machines Corporation | Trace/via hybrid structure multichip carrier |
CN107195607B (zh) * | 2017-07-03 | 2020-01-24 | 京东方科技集团股份有限公司 | 一种芯片封装方法及芯片封装结构 |
CN107768344B (zh) * | 2017-10-26 | 2019-01-11 | 长鑫存储技术有限公司 | 半导体封装系统整合装置及其制造方法 |
CN113228268B (zh) * | 2018-12-29 | 2023-09-29 | 华为技术有限公司 | 芯片封装结构、电子设备、芯片封装方法以及封装设备 |
CN110364445A (zh) * | 2019-06-03 | 2019-10-22 | 苏州通富超威半导体有限公司 | 半导体键合封装方法 |
CN112786540A (zh) * | 2019-11-06 | 2021-05-11 | 富泰华工业(深圳)有限公司 | 扇出型封装结构及其制作方法 |
CN110854111A (zh) * | 2019-11-25 | 2020-02-28 | 维沃移动通信有限公司 | 封装组件、电子设备及封装方法 |
CN114762103A (zh) * | 2019-12-16 | 2022-07-15 | 华为技术有限公司 | 一种芯片堆叠结构及其制作方法 |
CN111446177A (zh) * | 2020-04-13 | 2020-07-24 | 上海先方半导体有限公司 | 异质集成芯片的系统级封装方法及结构 |
CN113539978B (zh) * | 2020-04-17 | 2023-11-10 | 江苏长电科技股份有限公司 | 扇出封装结构 |
CN111739840B (zh) * | 2020-07-24 | 2023-04-11 | 联合微电子中心有限责任公司 | 一种硅转接板的制备方法及硅转接板的封装结构 |
CN111933590B (zh) * | 2020-09-11 | 2021-01-01 | 甬矽电子(宁波)股份有限公司 | 封装结构和封装结构制作方法 |
WO2022087894A1 (zh) * | 2020-10-28 | 2022-05-05 | 华为技术有限公司 | 多芯片封装结构、制造方法以及电子设备 |
CN112802761B (zh) * | 2021-01-07 | 2022-07-08 | 深圳市慧邦电子科技有限公司 | 一种集成电路封装结构和方法 |
CN112908870B (zh) * | 2021-02-01 | 2023-08-18 | 杭州晶通科技有限公司 | 一种能够消除芯片位移差的晶圆级扇出型封装方法 |
CN113053772A (zh) * | 2021-03-18 | 2021-06-29 | 西安电子科技大学 | 用于封装后硅通孔叠层芯片的测试结构 |
CN113192936B (zh) * | 2021-04-23 | 2024-02-13 | 泓林微电子(昆山)有限公司 | 一种双面芯片封装结构 |
CN113540016A (zh) * | 2021-05-28 | 2021-10-22 | 日月光半导体制造股份有限公司 | 半导体封装结构及其形成方法 |
CN114512589B (zh) * | 2022-04-21 | 2022-06-17 | 威海三维曲板智能装备有限公司 | 一种光电混合封装结构及其制造方法 |
CN114914196B (zh) * | 2022-07-19 | 2022-10-11 | 武汉大学 | 基于芯粒概念的局部中介层2.5d扇出封装结构及工艺 |
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CN103165479A (zh) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | 多芯片系统级封装结构的制作方法 |
CN103296008A (zh) * | 2012-02-22 | 2013-09-11 | 中国科学院微电子研究所 | Tsv或tgv转接板,3d封装及其制备方法 |
CN103794513A (zh) * | 2012-10-26 | 2014-05-14 | 中国科学院上海微系统与信息技术研究所 | 增强介质层PI和金属Cu层之间粘附性的方法 |
CN104538380A (zh) * | 2014-12-10 | 2015-04-22 | 华进半导体封装先导技术研发中心有限公司 | 小间距PoP封装单体 |
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- 2015-12-22 CN CN201510970167.5A patent/CN105428260B/zh active Active
Patent Citations (4)
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CN103296008A (zh) * | 2012-02-22 | 2013-09-11 | 中国科学院微电子研究所 | Tsv或tgv转接板,3d封装及其制备方法 |
CN103794513A (zh) * | 2012-10-26 | 2014-05-14 | 中国科学院上海微系统与信息技术研究所 | 增强介质层PI和金属Cu层之间粘附性的方法 |
CN103165479A (zh) * | 2013-03-04 | 2013-06-19 | 江苏物联网研究发展中心 | 多芯片系统级封装结构的制作方法 |
CN104538380A (zh) * | 2014-12-10 | 2015-04-22 | 华进半导体封装先导技术研发中心有限公司 | 小间距PoP封装单体 |
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Effective date of registration: 20210219 Address after: 214028 building D1, China Sensor Network International Innovation Park, No. 200, Linghu Avenue, New District, Wuxi City, Jiangsu Province Patentee after: National Center for Advanced Packaging Co.,Ltd. Address before: 2 / F, no.188-6, Zirui Avenue, high tech Zone, Chengdu, Sichuan 610041 Patentee before: CHENGDU RUIHUA OPTOELECTRONIC TECHNOLOGY Co.,Ltd. |
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Application publication date: 20160323 Assignee: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2022980027357 Denomination of invention: A Manufacturing Method of Fan out 2.5D/3D Packaging Structure Based on Carrier Granted publication date: 20171219 License type: Common License Record date: 20221213 |