CN114762103A - 一种芯片堆叠结构及其制作方法 - Google Patents

一种芯片堆叠结构及其制作方法 Download PDF

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Publication number
CN114762103A
CN114762103A CN201980102829.3A CN201980102829A CN114762103A CN 114762103 A CN114762103 A CN 114762103A CN 201980102829 A CN201980102829 A CN 201980102829A CN 114762103 A CN114762103 A CN 114762103A
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China
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wafer
bonding
layer
metal
chip
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Inventor
张晓东
李珩
王思敏
戚晓芸
王正波
牛瑞
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种芯片堆叠结构及其制作方法，其中，该芯片堆叠结构包括第一晶圆(100)和第二晶圆(200)，第一晶圆(100)的第一再布线层(130)设置有裸露的第一键合盘(133)，第一晶圆(100)的第一再布线层(130)和第一键合盘(133)与第二晶圆(200)的无源面(220)直接键合连接，不需要在键合表面制备额外的介电层，减小了第一晶圆(100)和第二晶圆(200)堆叠之后的厚度，使芯片封装后的尺寸更小，更轻薄。并且，第一晶圆(100)和第二晶圆(200)直接堆叠后的热阻更小，提高了芯片的散热性能。另外，第二晶圆(200)还设置有与第一键合盘(133)连接的硅通孔(233)，使得第一晶圆(100)和第二晶圆(200)可以通过硅通孔(233)直接电气互连，连接可靠性高。所提供的用于制作上述芯片堆叠结构的方法，工艺步骤简单，并且不会存在刻蚀选择比的问题，可实现性大大提高。

Description

PCT国内申请，说明书已公开。

Claims (14)

  1. PCT国内申请，权利要求书已公开。
CN201980102829.3A 2019-12-16 2019-12-16 一种芯片堆叠结构及其制作方法 Pending CN114762103A (zh)

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PCT/CN2019/125668 WO2021119924A1 (zh) 2019-12-16 2019-12-16 一种芯片堆叠结构及其制作方法

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CN114762103A true CN114762103A (zh) 2022-07-15

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WO (1) WO2021119924A1 (zh)

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* Cited by examiner, † Cited by third party
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CN113764288A (zh) * 2021-08-02 2021-12-07 苏州通富超威半导体有限公司 一种芯片封装方法及封装结构

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US8014166B2 (en) * 2008-09-06 2011-09-06 Broadpak Corporation Stacking integrated circuits containing serializer and deserializer blocks using through silicon via
CN103296008B (zh) * 2012-02-22 2016-06-01 华进半导体封装先导技术研发中心有限公司 Tsv或tgv转接板，3d封装及其制备方法
CN105428260B (zh) * 2015-12-22 2017-12-19 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构的制造方法
CN105428331B (zh) * 2015-12-22 2018-04-20 成都锐华光电技术有限责任公司 一种基于载体的扇出2.5d/3d封装结构
CN107195607B (zh) * 2017-07-03 2020-01-24 京东方科技集团股份有限公司 一种芯片封装方法及芯片封装结构
CN107768344B (zh) * 2017-10-26 2019-01-11 长鑫存储技术有限公司 半导体封装系统整合装置及其制造方法

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