CN104201168A - 一种芯片倾斜堆叠的圆片级封装单元及封装方法 - Google Patents
一种芯片倾斜堆叠的圆片级封装单元及封装方法 Download PDFInfo
- Publication number
- CN104201168A CN104201168A CN201410470282.1A CN201410470282A CN104201168A CN 104201168 A CN104201168 A CN 104201168A CN 201410470282 A CN201410470282 A CN 201410470282A CN 104201168 A CN104201168 A CN 104201168A
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- China
- Prior art keywords
- chip
- layer
- inclination
- wafer level
- packaged
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410470282.1A CN104201168B (zh) | 2014-09-16 | 2014-09-16 | 一种芯片倾斜堆叠的圆片级封装单元及封装方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410470282.1A CN104201168B (zh) | 2014-09-16 | 2014-09-16 | 一种芯片倾斜堆叠的圆片级封装单元及封装方法 |
Publications (2)
Publication Number | Publication Date |
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CN104201168A true CN104201168A (zh) | 2014-12-10 |
CN104201168B CN104201168B (zh) | 2017-01-25 |
Family
ID=52086439
Family Applications (1)
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CN201410470282.1A Active CN104201168B (zh) | 2014-09-16 | 2014-09-16 | 一种芯片倾斜堆叠的圆片级封装单元及封装方法 |
Country Status (1)
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CN (1) | CN104201168B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107958898A (zh) * | 2016-10-17 | 2018-04-24 | 深圳市中兴微电子技术有限公司 | 一种多芯片框架封装结构及其制造方法 |
CN111696983A (zh) * | 2020-06-24 | 2020-09-22 | 悦虎晶芯电路(苏州)股份有限公司 | 多芯片水平封装的芯片模组、晶圆结构和加工方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4107658A1 (de) * | 1991-03-09 | 1992-09-17 | Bosch Gmbh Robert | Montageverfahren fuer mikromechanische sensoren |
CN103927811B (zh) * | 2014-03-25 | 2016-09-14 | 江苏多维科技有限公司 | 一种磁电阻磁性图像识别传感器 |
CN204118064U (zh) * | 2014-09-16 | 2015-01-21 | 山东华芯半导体有限公司 | 一种芯片倾斜堆叠的圆片级封装单元 |
-
2014
- 2014-09-16 CN CN201410470282.1A patent/CN104201168B/zh active Active
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107958898A (zh) * | 2016-10-17 | 2018-04-24 | 深圳市中兴微电子技术有限公司 | 一种多芯片框架封装结构及其制造方法 |
CN107958898B (zh) * | 2016-10-17 | 2020-07-24 | 深圳市中兴微电子技术有限公司 | 一种多芯片框架封装结构及其制造方法 |
CN111696983A (zh) * | 2020-06-24 | 2020-09-22 | 悦虎晶芯电路(苏州)股份有限公司 | 多芯片水平封装的芯片模组、晶圆结构和加工方法 |
CN111696983B (zh) * | 2020-06-24 | 2024-03-15 | 悦虎晶芯电路(苏州)股份有限公司 | 多芯片水平封装的芯片模组、晶圆结构和加工方法 |
Also Published As
Publication number | Publication date |
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CN104201168B (zh) | 2017-01-25 |
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Effective date of registration: 20180614 Address after: 200120 C, 888, west two road, Nanhui new town, Pudong New Area, Shanghai Patentee after: Shanghai stratosphere Intelligent Technology Co.,Ltd. Address before: 250101 two floor of block B, Qilu Software Park, Ji'nan high tech Zone, Shandong. Patentee before: SHANDONG SINOCHIP SEMICONDUCTORS Co.,Ltd. |
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Effective date of registration: 20230506 Address after: Room 1125, Block M, 11th Floor, Building 1, No. 158 Shuanglian Road, Qingpu District, Shanghai, 200000 Patentee after: Shanghai Thermosphere Information Technology Co.,Ltd. Address before: 200120 C, 888, west two road, Nanhui new town, Pudong New Area, Shanghai Patentee before: Shanghai stratosphere Intelligent Technology Co.,Ltd. |