WO2018145413A1 - 硅通孔芯片的二次封装方法及其二次封装体 - Google Patents

硅通孔芯片的二次封装方法及其二次封装体 Download PDF

Info

Publication number
WO2018145413A1
WO2018145413A1 PCT/CN2017/094695 CN2017094695W WO2018145413A1 WO 2018145413 A1 WO2018145413 A1 WO 2018145413A1 CN 2017094695 W CN2017094695 W CN 2017094695W WO 2018145413 A1 WO2018145413 A1 WO 2018145413A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon via
via chip
solder ball
secondary package
bga solder
Prior art date
Application number
PCT/CN2017/094695
Other languages
English (en)
French (fr)
Inventor
吴宝全
龙卫
柳玉平
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to EP17896308.8A priority Critical patent/EP3422397A4/en
Priority to CN201780010390.2A priority patent/CN108780772B/zh
Publication of WO2018145413A1 publication Critical patent/WO2018145413A1/zh
Priority to US16/139,994 priority patent/US11183414B2/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1329—Protecting the fingerprint sensor against damage caused by the finger
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14698—Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the embodiments of the present invention relate to the field of semiconductor packaging technologies, and in particular, to a secondary packaging method of a through silicon via chip and a secondary package thereof.
  • the electronic products with fingerprint recognition function gradually develop toward miniaturization and thinning. Therefore, the thickness of the fingerprint identification chip is also higher and higher, and at the same time, the chip is satisfied. Under the requirements of package size, it is also required that the package has good mechanical structural strength and small low warpage.
  • the substrate 101 needs to be used as a carrier for secondary packaging (as shown in FIG. 1 is a schematic cross-sectional view of the through silicon via chip, as shown in FIG.
  • FIG. 1 is a schematic cross-sectional view of the through silicon via chip, as shown in FIG.
  • the thickness of the entire package generally exceeds 0.5 mm, and the warpage of the single package is also close to 50 ⁇ m.
  • Such a package size cannot be satisfied.
  • Electronic products are increasingly miniaturized and thinned for design needs.
  • the purpose of the embodiments of the present application is to provide a secondary encapsulation method of a through-silicon via chip and a secondary package thereof.
  • the secondary package does not need to use a substrate as a carrier, thereby ensuring a high mechanical structural strength of the through-silicon via chip.
  • the thickness of the secondary package is reduced, which is advantageous for thinning and miniaturization of electronic products.
  • an embodiment of the present application provides a method for secondary packaging of a through silicon via chip, the through silicon via chip having opposite positive and reverse surfaces, and a solder ball array package disposed on the reverse surface
  • the BGA solder ball, the secondary packaging method of the through silicon via chip comprises: placing at least one through silicon via chip on a base on which the release stress film layer is laid; wherein the positive surface of the through silicon via chip contacts the release stress film layer;
  • the silicon via chip is coated with a softened plastic sealant; after the plastic sealant is cured, the base is removed to obtain a secondary package of the through silicon via chip; and the surface of the secondary package is processed to expose the BGA solder ball; wherein
  • the surface of the secondary package being processed corresponds to the reverse surface of the through silicon via chip.
  • An embodiment of the present application further provides a secondary package of a through silicon via chip, comprising: a through silicon via chip and a molding compound; the through silicon via chip has a front surface, a reverse surface, and a plurality of lateral surfaces; The reverse surface of the via chip is provided with a solder ball; the plastic seal coats the reverse surface of the through silicon via chip and the plurality of lateral surfaces, and the solder ball is exposed on the surface of the plastic sealant.
  • the embodiment of the present application allows the secondary package of the through-silicon via chip to be separated from the base on which the stress-relieving film layer is laid, by using a release stress film layer. Obtaining a secondary package in the form of no substrate, on the basis of ensuring the high mechanical strength of the through silicon via chip, reducing the thickness of the through-silicon via chip secondary package compared to the substrate package form, contributing to electronic products Thin and compact design.
  • the use of the softened plastic encapsulated silicon via chip specifically comprising: pressing an injection mold having a cavity on the base such that the through silicon via chip is located in the cavity; and injecting a softened plastic sealant into the cavity, The plastic encapsulated plastic coated silicon via chip.
  • This embodiment provides a first specific implementation of using a softened plastic encapsulated silicon via chip, that is, a method of injecting a softened plastic seal using an injection mold.
  • the use of the softened plastic encapsulated silicon via chip specifically comprising: coating the softened plastic sealant on the through silicon via chip; using a press mold to press the softened plastic sealant and the through silicon via chip, The plastic encapsulated plastic coated silicon via chip.
  • This embodiment provides a second specific implementation of using a softened plastic encapsulated silicon via chip, that is, by direct coating and pressing.
  • processing the surface of the secondary package to expose the BGA solder ball specifically includes: grinding the surface of the secondary package to expose the BGA solder ball.
  • This embodiment provides a first specific implementation of exposing the BGA solder ball, that is, removing a part of the plastic encapsulant and a part of the BGA solder ball by grinding.
  • the exposed surface of the BGA solder ball is circular, and the distance between the exposed surface of the BGA solder ball and the reverse surface of the through-silicon via chip is equal to the radius of the circle. At this time, the exposed area of the BGA solder ball is the largest, and the BGA is improved. The reliability of the electrical connection between the solder ball and the outside world.
  • the method further includes: providing an auxiliary solder ball on the BGA solder ball; wherein the auxiliary solder ball is higher than the surface.
  • an auxiliary solder ball may be disposed on the BGA solder ball, which is equivalent to increasing the exposed area of the BGA solder ball, and further improving BGA The reliability of the electrical connection between the solder ball and the outside world.
  • the surface of the secondary package is processed to expose the BGA solder ball, and specifically includes: partially removing the plastic encapsulated portion corresponding to the BGA solder ball in the secondary package to expose the BGA solder ball; After the surface of the secondary package is processed to expose the BGA solder ball, the method further includes: providing an auxiliary solder ball on the BGA solder ball, and the auxiliary solder ball is higher or flush with the surface.
  • This embodiment provides a second specific implementation method of exposing the BGA solder ball, that is, a method of partially removing the plastic package and setting the auxiliary solder ball.
  • the manner of local removal includes one or any combination of laser laser, ion bombardment, and chemical etching.
  • the method further includes: cutting the secondary package to obtain a single through-silicon via chip Secondary package.
  • the exposed surface of the auxiliary solder ball is higher than the surface of the plastic sealant, the exposed surface of the auxiliary solder ball is higher than the surface of the plastic sealant by 50 um to 300 um, which enables the auxiliary solder ball to have a sufficient exposed area to ensure At the same time as the reliability of the electrical connection with the outside world, the overall thickness of the secondary package of the through silicon via chip is made as small as possible.
  • the through silicon via chip is a fingerprint identification chip
  • the front surface of the through silicon via chip includes a fingerprint recognition sensing area.
  • FIG. 1 is a schematic cross-sectional view of a through silicon via chip in accordance with the prior art
  • FIG. 2 is a schematic cross-sectional view of a secondary package of a through silicon via chip using a substrate according to the prior art
  • FIG. 3 is a specific flowchart of a method of secondary packaging of a through silicon via chip according to a first embodiment of the present application
  • FIG. 4 is a schematic cross-sectional view showing a through silicon via chip placed on a base according to a first embodiment of the present application
  • FIG. 5 is a cross-sectional view showing a secondary package of a through silicon via chip with a base removed in accordance with a first embodiment of the present application;
  • FIG. 6 is a specific flowchart of a method of secondary packaging of a through silicon via chip according to a second embodiment of the present application
  • FIG. 7 is a schematic structural view of a first specific implementation manner of using a softened plastic encapsulated silicon via chip according to a second embodiment of the present application;
  • FIG. 8 is a specific flowchart of a method of secondary packaging of a through silicon via chip according to a third embodiment of the present application.
  • FIG. 9 is a schematic structural view of a second specific implementation method of using a softened plastic encapsulated silicon via chip according to a third embodiment of the present application.
  • FIG. 10 is a specific flowchart of a method of secondary packaging of a through silicon via chip according to a fourth embodiment of the present application.
  • 11A is a schematic structural view of a first specific implementation manner of polishing a surface of a secondary package to expose a BGA solder ball according to a fourth embodiment of the present application;
  • 11B is a single cross section of a secondary package of a through silicon via chip in a fourth embodiment of the present application. schematic diagram;
  • FIG. 12 is a cross-sectional view showing a secondary package of a through-silicon via chip in which an auxiliary solder ball is provided on a BGA solder ball according to a fifth embodiment of the present application;
  • FIG. 13 is a schematic cross-sectional view showing a single package of a through-silicon via chip according to a fifth embodiment of the present application.
  • FIG. 14 is a detailed flowchart of a method of secondary packaging of a through silicon via chip according to a sixth embodiment of the present application.
  • FIG. 15 is a schematic structural view showing an implementation manner of partially removing a molding compound to expose a BGA solder ball according to a sixth embodiment of the present application;
  • 16 is a schematic structural view showing an implementation manner of partially removing a plastic sealant and adding an auxiliary solder ball according to a sixth embodiment of the present application;
  • 17 is a schematic cross-sectional view showing a unit of a secondary package of a through silicon via chip in a sixth embodiment of the present application.
  • a first embodiment of the present application relates to a method of secondary packaging of a through silicon via chip, and a specific process is shown in FIG. 3.
  • step 301 at least one through silicon via chip 1 is placed on the base 41 on which the stress relief film layer 3 is laid.
  • the through silicon via chip 1 has opposite front and back surfaces 11 and 12, and the reverse surface 12 is provided with a solder ball array package BGA solder ball 2.
  • the through silicon via chip For the fingerprint recognition chip, the forward surface 11 further includes a fingerprint recognition sensing area 13.
  • the base 41 is used to carry the through silicon via chip 1; when the through silicon via chip 1 is placed on the release stress film layer 3, the release stress layer 3 has a certain viscosity.
  • the function of the through silicon via chip 1 can be fixed; the front surface 11 of the through silicon via chip 1 includes the fingerprint recognition sensing region 13 without the plastic encapsulation, so that the front surface 11 is in contact with the release stress film layer 3.
  • the plurality of through-silicon via chips 1 can be re-packaged at the same time, and the rules for placing the plurality of through-silicon via chip 1 on the base 41 can be set according to actual requirements, for example, according to the size of the base 41 or the secondary package.
  • the size requirement determines the placement or placement of multiple through-silicon via chips.
  • the front surface 11 is further provided with a protective layer (not shown), and the protective layer covers the fingerprint recognition sensing area 13 to protect the fingerprint recognition sensing area 13.
  • the thickness of the protective layer may be greater than or equal to 5 micrometers and less than or equal to 50 micrometers, for example, the thickness of the protective layer may be 5 micrometers, or 25 micrometers, or 50 micrometers; the material of the protective layer may be an organic colloid, and It may be disposed on the front surface 11 in a coating manner.
  • this embodiment does not impose any limitation on the thickness, material, and arrangement of the protective layer.
  • Step 302 coating the through silicon via chip 1 with a softened plastic sealant.
  • the release stress film layer 3 is exposed, and the remaining five faces are molded by the softened plasticizer.
  • Softened plastic seal The glue generally contains organic and inorganic materials such as resins, silicone oils, and silica particles.
  • Step 303 after the plastic sealant is cured, the base 41 is removed to obtain the secondary package of the through silicon via chip 1.
  • step 304 the surface of the secondary package is processed to expose the BGA solder balls 2.
  • the BGA solder balls 2 are all buried in the cured plastic sealant, so the BGA solder balls 2 need to be exposed.
  • the surface of the secondary package may be treated by a specific processing process such that the surface of the processed secondary package corresponds to the reverse surface 12 of the through-silicon via chip 1, that is, the silicon via chip is disposed.
  • the BGA solder ball 2 of the reverse surface 12 is exposed, so that the through silicon via chip 1 is electrically interconnected with the outside only through the BGA solder ball 2.
  • part of the molding compound and part of the BGA solder ball are simultaneously removed; however, in some cases, only the molding compound may be removed.
  • the secondary package of the plurality of through-silicon via chips can be packaged.
  • the body is diced to obtain a secondary package of a single through silicon via chip.
  • the secondary encapsulation method of the through-silicon via chip provided by this embodiment is compared with the prior art, and by using the release stress film layer, when the plastic encapsulant is cured, the secondary package of the through-silicon via chip can be laid and laid.
  • the base of the release stress film layer is separated to obtain a secondary package in the form of no substrate.
  • the through silicon via chip secondary package is reduced compared to the substrate package form. The thickness contributes to the thinning and miniaturization of electronic products.
  • a second embodiment of the present application relates to a secondary packaging method of a through silicon via chip.
  • the second embodiment is a refinement of the first embodiment, and the main refinement is as follows: Referring to FIG. 6 and FIG. 7, this embodiment provides a method of coating the through silicon via chip 1 with the softened plasticizer 5.
  • a specific implementation that is, a method of injecting a molding compound using an injection mold.
  • Step 601 and step 301 are substantially the same, and steps 603 to 604 are substantially the same as steps 303 to 304, and are not described herein again.
  • step 302 is refined in this embodiment. described as follows:
  • Sub-step 6021 an injection mold 42 having a cavity is pressed against the base 41, and the through-silicon via chip 1 is placed in the cavity.
  • the release stress film layer 3 is laid on the base 41 in advance, and after the through silicon via chip 1 is placed, the injection mold 42 is closed; and the injection mold 42 is pressed against the base 41 by the pressing force applied to the injection mold 42 by the outside. Together.
  • Sub-step 6022 the softened molding compound 5 is injected into the cavity, so that the molding compound 5 covers the through-silicon via chip 1.
  • the injection mold 42 is actually provided with an injection port 44 and an exhaust port 43. At this time, the softened plastic seal 5 is injected into the cavity through the injection port 44; the exhaust port 43 is used to discharge the air in the cavity during the injection of the plastic seal 5, so that the plastic seal 5 can completely fill the cavity. To completely cover the through silicon via chip 1.
  • the secondary packaging method of the through silicon via chip provided in this embodiment is compared with the first embodiment,
  • the injection molding mold is used to inject a softened plastic sealant to cover a specific implementation of the through-silicon via chip, and the injection mold is more commonly used in the field, and the operation process is simple and convenient.
  • a third embodiment of the present application relates to a secondary packaging method of a through silicon via chip.
  • the third embodiment is a refinement of the first embodiment, and the main refinement is as follows: Referring to FIG. 8 and FIG. 9, the present embodiment provides a second specific example of using a softened plastic encapsulated silicon via chip.
  • the way of implementation is to use direct coating and pressing.
  • Step 801 and step 301 are substantially the same, and the steps 803 to 804 are substantially the same as the steps 303 to 304, and are not described herein again.
  • the difference is that the embodiment 302 refines the step 302. described as follows:
  • step 8021 the softened molding compound 5 is coated on the through silicon via chip 1.
  • the softened plastic sealant 5 is directly coated on the through silicon via chip 1.
  • step 8022 the softened plastic seal 5 and the through silicon via chip 1 are pressed by the press mold 45, so that the plastic sealant 5 covers the through silicon via chip.
  • the pressing mold 45 is directly pressed in the direction indicated by the arrow in FIG. 9. During the pressing process, the excess plastic sealing glue overflows, and after the pressing is completed, the plastic sealing glue 5 completely covers the through silicon through hole.
  • the chip 1 has the remaining five faces except the front surface 11, and completely fills the gap between the plurality of through silicon via chips, and a flat rubber surface can be obtained after the plastic sealant is cured.
  • press mold 45 in the present embodiment can realize the technical solution described in the embodiment by directly using the press-fitting mold 45 without the injection port and the exhaust port.
  • the present embodiment and the second embodiment of the present application respectively provide soft use.
  • a specific implementation of the plastic encapsulated silicon via chip is that in the second embodiment of the present application, the secondary packaging method of the through silicon via chip is to inject softened plastic sealant into the injection mold.
  • the softened plastic sealant is directly coated on the surface of the through silicon via chip and pressed by a press mold. In practical applications, any one of the modes may be selected. This example does not limit this.
  • the method for sub-packaging the through-silicon via chip provided in this embodiment provides a coating method of directly coating a softened plastic seal on a through-silicon via chip and pressing it with a press mold.
  • the pressing mold is more commonly used in the field, and the operation process is simple and convenient.
  • a fourth embodiment of the present application relates to a method of secondary packaging of a through silicon via chip.
  • the embodiment provides processing on the surface of the secondary package to expose the BGA tin.
  • the first specific implementation of the ball is the first specific implementation of the ball.
  • the steps 1001 to 1003 are substantially the same as the steps 301 to 303, and are not described here again.
  • the difference is that the step 304 is refined in the embodiment, and the details are as follows:
  • step 1004 the surface of the secondary package is ground to expose the BGA solder balls.
  • the BGA solder ball 2 is still buried in the cured molding compound 5, in this embodiment, the BGA solder ball 2 is exposed by grinding the cured molding compound.
  • a portion of the molding compound 5 and a portion of the BGA solder balls 2 may be ground.
  • the mechanical head of the polishing apparatus directly applies pressure to the surface of the secondary package (ie, the surface corresponding to the reverse surface 12 of the through-silicon via chip), and the mechanical head is energized and rotated at a high speed to polish the secondary package.
  • the height of a part of the surface, which is specifically polished off, actually depends on the height of the plastic seal 5 after curing. Degree, until the BGA solder ball 2 is exposed; in order to maximize the reliability of the BGA solder ball 2 when electrically connected to the outside, the exposed area of the BGA solder ball 2 can be maximized.
  • the round BGA solder ball is used.
  • the exposed surface of the BGA solder ball is circular
  • it is generally the best way to grind out half of the BGA solder ball 2 because the BGA solder ball 2 has the largest exposed area, that is, this
  • the distance between the exposed face of the BGA solder ball 2 and the reverse surface 12 of the through silicon via chip is equal to the radius of the circle.
  • FIG. 11B shows a monomer of a secondary package obtained by cutting a secondary package of a plurality of through-silicon via chips after polishing.
  • the method for sub-packaging the through-silicon via chip provided in this embodiment provides a first specific implementation method of exposing the surface of the secondary package to expose the BGA solder ball, and the grinding process is compared with the first embodiment. It is more commonly used in the field, and the operation is simple and convenient, and the cost is low.
  • a fifth embodiment of the present application relates to a secondary encapsulation method of a through silicon via chip.
  • This embodiment is an improvement of the fourth embodiment, and the main improvement is that: referring to FIG. 12 and FIG.
  • the auxiliary solder balls 6 are disposed on the BGA solder balls to further improve the reliability of the BGA solder balls 2 when electrically connected to the outside.
  • the auxiliary solder ball 6 can be placed on the BGA solder ball 2 by screen printing, and then the solder can be reflowed to obtain the secondary package of the through silicon via chip.
  • FIG. 13 shows a single package of the secondary package of the through silicon via chip which is cut after the auxiliary solder ball 6 is provided.
  • the secondary encapsulation method of the through silicon via chip provided in this embodiment further improves the reliability of the BGA solder ball when electrically connected to the outside by adding the auxiliary solder ball.
  • a sixth embodiment of the present application relates to a secondary packaging method of a through silicon via chip.
  • the fifth embodiment is a refinement of the first embodiment, and the main refinement is that, referring to FIG. 14 and FIG. 15, the embodiment provides processing on the surface of the secondary package to expose the BGA solder ball.
  • the specific process of the secondary packaging method of the through silicon via chip provided in this embodiment is as shown in FIG. 14 .
  • Steps 1401 to 1403 are substantially the same as steps 301 to 303, and are not described herein again. The difference is that step 304 is refined in the embodiment, and step 1405 is added, which is specifically described as follows:
  • step 1404 the plastic encapsulant portion corresponding to the BGA solder ball 2 in the secondary package is partially removed to expose the BGA solder ball 2.
  • part of the plastic encapsulant may be removed by one or any combination of laser laser, ion bombardment, and chemical etching. Due to process characteristics, only the BGA tin corresponding to the BGA is removed in this embodiment.
  • the plastic encapsulant portion of the ball 2 forms a cavity region 21 above the BGA solder ball 2.
  • Step 1405 an auxiliary solder ball 6 is disposed on the BGA solder ball, and the auxiliary solder ball 6 is higher or flush. On the surface.
  • auxiliary solder ball 6 is also required to be filled in the cavity region 21 corresponding to each BGA solder ball 2 in this embodiment.
  • the solder can be printed into the cavity region by a screen printing process, or the solder ball can be directly filled into the cavity region 21 by a ball drop process, and then the cavity region 21 is completely filled by a reflow process;
  • the auxiliary solder ball 6 needs to be higher or flush with the surface to facilitate electrical connection between the secondary package and the outside.
  • Fig. 17 is a view showing a single package of a secondary package of a through silicon via chip which is cut after the auxiliary solder ball 6 is provided.
  • the present embodiment and the fourth embodiment of the present application respectively provide a specific implementation manner of processing the surface of the secondary package to expose the BGA solder ball; the difference is: 1.
  • a grinding process is used, and part of the molding compound 5 and a part of the BGA solder ball 2 may be ground at the same time, or only the plastic sealing glue may be ground.
  • auxiliary solder ball 6 may be selected for use; in the present embodiment, the auxiliary solder ball 6 must be used.
  • the secondary encapsulation method of the through silicon via chip provided by this embodiment provides a second specific implementation method of exposing the surface of the secondary package to expose the BGA solder ball, and partially removing, compared with the first embodiment.
  • the process of molding plastic and the process of setting auxiliary solder balls are more commonly used in the field, and the realization is very simple.
  • the seventh embodiment of the present application relates to a secondary package of a through silicon via chip.
  • the secondary package of the through silicon via chip includes: referring to FIG. 11 , the through silicon via chip 1 and the plastic encapsulant 2 ; the through silicon via chip 1 has a front surface 11, a reverse surface 12 and a plurality of lateral surfaces; the reverse surface 12 of the through silicon via chip 1 is provided with a solder ball 2; the plastic seal 5 covers the reverse surface 12 of the through silicon via chip 1 and The solder balls 2 are exposed on the surface of the molding compound 5 on a plurality of lateral surfaces.
  • the through silicon via chip 1 is a fingerprint identification chip, and the front surface 11 of the through silicon via chip 1 further includes a fingerprint recognition sensing area 13;
  • the solder ball includes a BGA solder ball 2, and the BGA solder ball 2 is exposed to the plastic sealing glue 5 The surface of the BGA solder ball 2 is flush with the surface of the molding compound 5, thereby electrically interconnecting the BGA solder ball 2 with the outside.
  • a part of the plastic encapsulant and a portion of the BGA solder ball may be removed by a grinding process, so that the BGA solder ball 2 is exposed on the surface of the laminating adhesive 5.
  • the exposed surface of the BGA solder ball 2 is circular, and the distance between the exposed surface of the BGA solder ball 2 and the reverse surface 12 of the through silicon via chip 1 is equal to the radius of the circle, and the area of the exposed surface of the BGA solder ball 2 at this time. Maximum, try to improve the reliability of the BGA solder ball 2 electrical connection with the outside world.
  • the secondary package of the through-silicon via chip provided in this embodiment is compared with the prior art, and by using a release stress film layer, when the plastic encapsulant is cured, the secondary package of the through-silicon via chip can be laid with release stress.
  • the base of the film layer is separated to obtain a secondary package in the form of no substrate.
  • the thickness of the through-silicon via chip secondary package is reduced compared to the substrate package form. It contributes to the thinning and miniaturization of electronic products.
  • the eighth embodiment of the present application relates to a secondary package of a through silicon via chip.
  • This embodiment is substantially the same as the sixth embodiment.
  • the solder ball includes a BGA.
  • the solder ball 2, the BGA solder ball 2 is exposed on the surface of the plastic seal 5, and the exposed surface of the BGA solder ball 2 is flush with the surface of the molding compound 5; and in this embodiment, please refer to FIG. 13 or 17, the solder ball includes The BGA solder ball 2 and the auxiliary solder ball 6 are exposed on the surface of the plastic seal 5, and the exposed surface of the auxiliary solder ball 6 is higher than or flush with the surface of the plastic seal 5.
  • the BGA solder ball 2 is connected to the reverse surface 12 of the through silicon via chip.
  • the surface of the secondary package of the through silicon via chip needs to be processed to expose the BGA solder ball 2,
  • one or any combination of laser laser, ion bombardment, and chemical etching may be used to remove the plastic sealant corresponding to the BGA solder ball 2, which is not removed by using these processes due to process characteristics.
  • BGA solder ball so the exposed surface of the BGA solder ball is lower than the surface of the secondary package, so the auxiliary solder ball 6 is placed on the BGA solder ball 2, and the auxiliary solder ball 6 is connected to the BGA solder ball 2.
  • the auxiliary solder ball 6 is exposed on the surface of the molding compound 5, and the exposed surface of the auxiliary solder ball 6 is higher than or flush with the surface of the molding compound 5.
  • the exposed surface of the auxiliary solder ball 6 is higher than the surface of the molding compound 5
  • the exposed surface of the auxiliary solder ball 6 is higher than the surface of the molding compound 5 by a distance of 50 um to 300 um, which enables the auxiliary solder ball 6 to have
  • the exposed area is sufficient to ensure the reliability of the electrical connection with the outside world, and the overall thickness of the secondary package of the through silicon via chip is as small as possible.
  • the secondary package of the through-silicon via chip provided in this embodiment provides a specific implementation of the secondary package of the second through-silicon via chip: by providing auxiliary tin on the BGA solder ball The ball increases the contact area of the BGA solder ball with the outside to improve the reliability of the electrical connection.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种硅通孔芯片的二次封装方法及硅通孔芯片的二次封装体。硅通孔芯片（1）具有相对的正向表面（11）与反向表面（12），反向表面（12）上设置有焊球阵列封装BGA锡球（2），硅通孔芯片（1）的二次封装方法包括：将至少一硅通孔芯片（1）放置在铺设有释放应力膜层（3）的底座（41）上；使用软化的塑封胶（5）包覆硅通孔芯片（1）；待塑封胶（5）固化后去除底座（41），以获取硅通孔芯片（1）的二次封装体；对二次封装体的表面进行处理，以露出BGA锡球（2）。在二次封装中无需使用基板作为载体，在保证硅通孔芯片（1）具有较高机械结构强度的基础上，降低了二次封装体的厚度，有利于电子产品的薄型化和小型化设计。

Description

硅通孔芯片的二次封装方法及其二次封装体
交叉引用
本申请引用于2017年2月13日递交的名称为“硅通孔芯片的二次封装方法及其二次封装体”的第PCT/CN2017/073354号国际专利申请，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及半导体封装技术领域，特别涉及一种硅通孔芯片的二次封装方法及其二次封装体。
背景技术
带有指纹识别功能的电子产品随着整机设计的需要，逐步迈向小型化和薄型化方向发展，因此，对指纹识别芯片的厚度也提出了越来越高的要求，同时，在满足芯片封装尺寸的要求下，还需要封装体具有良好的机械结构强度以及较小的低翘曲度。
然而，发明人发现在现有的指纹识别芯片的封装方案中，至少存在以下技术问题：不论是采用trench挖槽工艺进行的wire bond打线封装还是TSV(Through Silicon Vias)硅通孔封装，均需要使用基板101作为载体进行二次封装(如图1所示为硅通孔芯片的剖面示意图，如图2所示为采用基板101进 行二次封装后的剖面示意图)，在使用基板作为载体进行封装后，整个封装体的厚度一般会超出0.5mm，单个封装体的翘曲度也会接近50um，这样的封装体尺寸是无法满足电子产品日趋小型化和薄型化的设计需求的。
发明内容
本申请实施例的目的在于提供一种硅通孔芯片的二次封装方法及其二次封装体，二次封装中无需使用基板作为载体，因此，在保证硅通孔芯片具有较高机械结构强度的基础上，降低了二次封装体的厚度，有利于电子产品的薄型化和小型化设计。
为解决上述技术问题，本申请的实施例提供了一种硅通孔芯片的二次封装方法，硅通孔芯片具有相对的正向表面与反向表面，反向表面上设置有焊球阵列封装BGA锡球，硅通孔芯片的二次封装方法包括：将至少一硅通孔芯片放置在铺设有释放应力膜层的底座上；其中，硅通孔芯片的正向表面接触释放应力膜层；使用软化的塑封胶包覆硅通孔芯片；待塑封胶固化后去除底座，以获取硅通孔芯片的二次封装体；对二次封装体的表面进行处理，以露出BGA锡球；其中，被处理的二次封装体的表面与硅通孔芯片的反向表面相对应。
本申请的实施例还提供了一种硅通孔芯片的二次封装体，包括：硅通孔芯片与塑封胶；硅通孔芯片具有正向表面、反向表面以及多个侧向表面；硅通孔芯片的反向表面设置有焊锡球；塑封胶包覆硅通孔芯片的反向表面与多个侧向表面，焊锡球外露于塑封胶的表面。
本申请实施例相对于现有技术而言，通过采用释放应力膜层，当塑封胶固化后，使得硅通孔芯片的二次封装体可以与铺设有释放应力膜层的底座分离， 得到无基板形式的二次封装体，在保证硅通孔芯片具有较高机械结构强度的基础上，相较于基板封装形式降低了硅通孔芯片二次封装体的厚度，有助于电子产品的薄型化和小型化设计。
另外，使用软化的塑封胶包覆硅通孔芯片中，具体包括：将具有空腔的注塑模具按压在底座上，使得硅通孔芯片位于空腔中；向空腔中注入软化的塑封胶，使得塑封胶包覆硅通孔芯片。本实施例提供了使用软化的塑封胶包覆硅通孔芯片的第一种具体实现方式，即采用注塑模具注入软化的塑封胶的方式。
另外，使用软化的塑封胶包覆硅通孔芯片中，具体包括：将软化的塑封胶涂布在硅通孔芯片上；利用压合模具对软化的塑封胶与硅通孔芯片进行压合，使得塑封胶包覆硅通孔芯片。本实施例提供了使用软化的塑封胶包覆硅通孔芯片的第二种具体实现方式，即采用直接涂布并压合的方式。
另外，对二次封装体的表面进行处理，以露出BGA锡球中，具体包括：对二次封装体的表面进行研磨，以露出BGA锡球。本实施例提供了露出BGA锡球的第一种具体实现方式，即采用研磨方式去除部分塑封胶与部分BGA锡球。
另外，BGA锡球的外露面为圆形，BGA锡球的外露面与硅通孔芯片的反向表面的距离等于圆形的半径，此时BGA锡球的外露面的面积最大，提高了BGA锡球与外界电气互连的可靠性。
另外，在对二次封装体的表面进行处理，以露出BGA锡球之后，还包括：在BGA锡球上设置辅助锡球；其中，辅助锡球高于表面。当研磨去除BGA锡球部分过多或者不足、或者BGA锡球的外露面的面积不够大时，可以在BGA锡球上设置辅助锡球，相当于增大了BGA锡球的外露面积，进一步提高了BGA 锡球与外界电气互连的可靠性。
另外，对二次封装体的表面进行处理，以露出BGA锡球中，具体包括：对二次封装体中对应于BGA锡球的塑封胶部分进行局部去除，以露出BGA锡球；在对二次封装体的表面进行处理，以露出BGA锡球之后，还包括：在BGA锡球上设置辅助锡球，且辅助锡球高于或齐平于表面。本实施例提供了露出BGA锡球的第二种具体实现方式，即采用局部去除塑封较并设置辅助锡球的方式。
另外，局部去除的方式包括激光镭射、离子轰击、化学腐蚀中的其中之一或任意组合。
另外，硅通孔芯片的数目为多个；在对二次封装体的表面进行处理，以露出BGA锡球之后，还包括：对二次封装体进行切割，以获取单个硅通孔芯片的二次封装体。
另外，当辅助锡球的外露面高于塑封胶的表面时，辅助锡球的外露面高出塑封胶的表面的距离是50um至300um之间，能够使得辅助锡球有足够的外露面积以确保与外界之间电性连接的可靠性的同时，使得硅通孔芯片的二次封装体的整体厚度尽可能小。
另外，硅通孔芯片为指纹识别芯片，硅通孔芯片的正向表面包括指纹识别感应区。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表 示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是根据现有技术中的硅通孔芯片的剖面示意图；
图2是根据现有技术中的采用基板的硅通孔芯片的二次封装体的剖面示意图；
图3是根据本申请第一实施例的硅通孔芯片的二次封装方法的具体流程图；
图4是根据本申请第一实施例中的硅通孔芯片放置于底座的剖面示意图；
图5是根据本申请第一实施例中去除底座的硅通孔芯片的二次封装体的剖面示意图；
图6是根据本申请第二实施例的硅通孔芯片的二次封装方法的具体流程图；
图7是根据本申请第二实施例中使用软化的塑封胶包覆硅通孔芯片的第一种具体实现方式的结构示意图；
图8是根据本申请第三实施例的硅通孔芯片的二次封装方法的具体流程图；
图9是根据本申请第三实施例中使用软化的塑封胶包覆硅通孔芯片的第二种具体实现方式的结构示意图；
图10是根据本申请第四实施例的硅通孔芯片的二次封装方法的具体流程图；
图11A是根据本申请第四实施例中对二次封装体的表面进行研磨以露出BGA锡球的第一种具体实现方式的结构示意图；
图11B是根据本申请第四实施例中硅通孔芯片的二次封装体的单体剖面 示意图；
图12是根据本申请第五实施例中在BGA锡球上设置辅助锡球的硅通孔芯片的二次封装体的剖面示意图；
图13是根据本申请第五实施例中的硅通孔芯片的二次封装体的单体剖面示意图；
图14是根据本申请第六实施例的硅通孔芯片的二次封装方法的具体流程图；
图15是根据本申请第六实施例中局部去除塑封胶以露出BGA锡球的实现方式的结构示意图；
图16是根据本申请第六实施例中局部去除塑封胶并增加辅助锡球的实现方式的结构示意图；
图17是根据本申请第六实施例中的硅通孔芯片的二次封装体的单体剖面示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请的第一实施例涉及一种硅通孔芯片的二次封装方法，具体流程如图3所示。
步骤301，将至少一硅通孔芯片1放置在铺设有释放应力膜层3的底座41上。
请参考图4所示，硅通孔芯片1具有相对的正向表面11与反向表面12，反向表面12上设置有焊球阵列封装BGA锡球2，本实施例中，硅通孔芯片为指纹识别芯片，正向表面11还包括指纹识别感应区13。
在本实施例提供的二次封装过程中，底座41用于承载硅通孔芯片1；当硅通孔芯片1放置在释放应力膜层3上后，由于释放应力膜层3具有一定的黏性，可以起到固定硅通孔芯片1的作用；硅通孔芯片1的正向表面11包括指纹识别感应区13，无需塑封胶封装，因此将正向表面11与释放应力膜层3接触。
可以同时对多个硅通孔芯片1进行二次封装，并可以根据实际需求设置多个硅通孔芯片1摆放在底座41上的规则，例如：可以根据底座41的尺寸或者对二次封装体尺寸的要求，决定多个硅通孔芯片之间的摆放间距或者摆放数量。
较佳的，正向表面11上还设置有保护层(图未示)，保护层覆盖指纹识别感应区13，以对指纹识别感应区13进行保护。其中，保护层的厚度可以是大于或等于5微米且小于或等于50微米，例如，保护层的厚度可以是5微米、或者25微米、或者50微米；该保护层的材料可以是有机胶体，且可以是以涂覆方式设置在正向表面11上。然，本实施例对保护层的厚度、材料以及设置方式，不作任何限制。
步骤302，使用软化的塑封胶包覆硅通孔芯片1。
本步骤中，硅通孔芯片1中除了正向表面11(包括指纹识别感应区13)接触释放应力膜层3外，其余的五个面均被软化的塑封胶所塑封。软化的塑封 胶一般含有树脂、硅油以及二氧化硅颗粒等有机和无机材料。
步骤303，待塑封胶固化后去除底座41，以获取硅通孔芯片1的二次封装体。
如图5所示，当多个硅通孔芯片1同时排列在基板上时，由于硅通孔芯片1的四周有固化的塑封胶环绕支撑，固化后的塑封胶具有一定的强度，因此能形成整片的连体的多个硅通孔芯片1的二次封装体；由于释放应力膜层3与塑封胶之间结合力不会过强，待塑封胶固化后，可以使二次封装体与铺设有释放应力膜层3的底座41分离，从而得到无基板形式的硅通孔芯片的二次封装体。
步骤304，对二次封装体的表面进行处理，以露出BGA锡球2。
此时，BGA锡球2全部埋在固化的塑封胶内，因此需使BGA锡球2露出来。可以采用特定的处理工艺对二次封装体的表面进行处理，以使被处理的二次封装体的表面与硅通孔芯片1的反向表面12相对应，也就是让设置于硅通孔芯片1反向表面12的BGA锡球2外露，使得硅通孔芯片1仅通过BGA锡球2与外界进行电气互连。
需要说明的是，一般来说，在对二次封装体的表面进行处理时，会同时去除部分塑封胶与部分BGA锡球；然而，在有些情况下，也可以仅去除塑封胶。
当获得的是多个硅通孔芯片的二次封装体时，在对二次封装体的表面进行处理露出BGA锡球后，可以对这一连体的多个硅通孔芯片的二次封装体进行切割，以获取单个硅通孔芯片的二次封装体。
本实施例提供的硅通孔芯片的二次封装方法与现有技术相比，通过采用释放应力膜层，当塑封胶固化后，使得硅通孔芯片的二次封装体可以与铺设有 释放应力膜层的底座分离，得到无基板形式的二次封装体，在保证硅通孔芯片具有较高机械结构强度的基础上，相较于基板封装形式降低了硅通孔芯片二次封装体的厚度，有助于电子产品的薄型化和小型化设计。
本申请的第二实施例涉及一种硅通孔芯片的二次封装方法。第二实施例是对第一实施例的细化，主要细化之处在于：请参考图6和图7，本实施例提供了使用软化的塑封胶5以包覆硅通孔芯片1的第一种具体实现方式，即，使用注塑模具注入塑封胶的方式。
本实施例提供的硅通孔芯片的二次封装方法的具体流程如图6所示。
其中，步骤601与步骤301对应大致相同，步骤603至步骤604与步骤303至步骤304对应大致相同，在此处不再赘述；不同之处在于：本实施例对步骤302进行了细化，具体说明如下：
子步骤6021，将具有空腔的注塑模具42按压在底座41上，硅通孔芯片1位于空腔中。
事先将释放应力膜层3铺设在底座41上，摆放好硅通孔芯片1后，合上注塑模具42；通过外界施加给注塑模具42的压紧力，将注塑模具42与底座41压合在一起。
子步骤6022，向空腔中注入软化的塑封胶5，使得塑封胶5包覆硅通孔芯片1。
注塑模具42实际上还设置有注塑口44与排气口43。此时，通过注塑口44向空腔中注入软化的塑封胶5；排气口43用于在注入塑封胶5的过程中排掉空腔内的空气，使得塑封胶5能够完全填充空腔，以完全覆盖硅通孔芯片1。
本实施例提供的硅通孔芯片的二次封装方法与第一实施例相比，提供了 使用注塑模具注塑软化的塑封胶以包覆硅通孔芯片的一种具体实现方式，且注塑模具在本领域内较为常用，操作工艺简单、方便。
本申请的第三实施例涉及一种硅通孔芯片的二次封装方法。第三实施例是对第一实施例的细化，主要细化之处在于：请参考图8和图9，本实施例提供了使用软化的塑封胶包覆硅通孔芯片的第二种具体实现方式，即采用直接涂布并压合的方式。
本实施例提供的硅通孔芯片的二次封装方法的具体流程如图8所示。
其中，步骤801与步骤301对应大致相同，步骤803至步骤804与步骤303至步骤304对应大致相同，在此处不再赘述；不同之处在于：本实施例对步骤302进行了细化，具体说明如下：
步骤8021，将软化的塑封胶5涂布在硅通孔芯片1上。
本实施例中，将硅通孔芯片1摆放在铺设有释放应力膜层3的底座41上后，直接将软化的塑封胶5涂布在硅通孔芯片1上。
步骤8022，利用压合模具45对软化的塑封胶5与硅通孔芯片1进行压合，使得塑封胶5包覆硅通孔芯片。
本实施例中，直接将压合模具45按照如图9中箭头所示方向压合，在压合过程中，多余的塑封胶会溢出，压合完成后，塑封胶5完整包覆硅通孔芯片1除了正向表面11外其余的五个面，并完全填充多个硅通孔芯片之间的缝隙，待塑封胶固化后即能够得到平整的胶面。
需要说明的是，本实施例中的压合模具45可以不设置注塑口与排气口，直接利用压合模具45的压合作用即可实现本实施例记载的技术方案。
由上述分析可以看出，本实施例与本申请第二实施例分别提供了使用软 化的塑封胶包覆硅通孔芯片的一种具体实现方式；区别之处在于：在本申请第二实施例中，硅通孔芯片的二次封装方法为向注塑模具内注入软化的塑封胶以包覆硅通孔芯片；而在本实施例中，直接在硅通孔芯片表面涂布软化的塑封胶并利用压合模具压合，于实际应用中，可以选择任一种方式，本实施例对此不作限制。
本实施例提供的硅通孔芯片的二次封装方法与第一实施例相比，提供了一种直接在硅通孔芯片上涂布软化的塑封胶并利用压合模具压合的包覆方式，且压合模具在本领域内较为常用，操作工艺简单、方便。
本申请的第四实施例涉及一种硅通孔芯片的二次封装方法，请参考图10、图11A和图11B，本实施例提供了对二次封装体的表面进行处理，以露出BGA锡球的第一种具体实现方式。
本实施例提供的硅通孔芯片的二次封装方法具体流程如图10所示。
其中，步骤1001至步骤1003与步骤301至步骤303对应大致相同，在此处不再赘述；不同之处在于：本实施例对步骤304进行了细化，具体说明如下：
步骤1004，对二次封装体的表面进行研磨，以露出BGA锡球。
由于BGA锡球2仍然埋在固化的塑封胶5里面，本实施例通过对固化的塑封胶进行研磨，使BGA锡球2露出来。
如图11A所示，于实际中，可以研磨掉部分塑封胶5与部分BGA锡球2。研磨时，使研磨设备的机械头直接对二次封装体的表面(即硅通孔芯片的反向表面12所对应的表面)施加压力，机械头通电后高速旋转从而可以打磨掉二次封装体表面的一部分，具体打磨掉的高度实际上取决于塑封胶5固化后的高 度，直至BGA锡球2露出来；为了尽量提高BGA锡球2与外界电气连接时的可靠性，可以使BGA锡球2露出的面积最大化，本实施例中，以圆形的BGA锡球(即BGA锡球的外露面为圆形)为例，一般是研磨掉BGA锡球2的一半为最佳的实现方式，因为此时BGA锡球2露出来的面积最大，也就是说，此时，BGA锡球2的外露面与硅通孔芯片的反向表面12的距离等于圆形的半径。如图11B为研磨后对多个硅通孔芯片的二次封装体进行切割得到的二次封装体的单体。
值得一提的是，本实施例记载的技术方案也可基于本申请第二或者第三实施例的基础上实施。
本实施例提供的硅通孔芯片的二次封装方法与第一实施例相比，提供了对二次封装体的表面进行处理，以露出BGA锡球的第一种具体实现方式，且研磨工艺在本领域内较为常用，操作简单方便、成本低廉。
本申请的第五实施例涉及一种硅通孔芯片的二次封装方法，本实施例是对第四实施例的改进，主要改进之处在于：请参考图12和图13，在对二次封装体的表面进行处理，以露出BGA锡球2之后，还包括：在BGA锡球上设置辅助锡球6，以进一步提高BGA锡球2与外界电气连接时的可靠性。
于实际中，如果研磨时研磨去除BGA锡球2的部分过多或者不足导致BGA锡球2外露面面积不足时、或者虽然BGA锡球2的外露面面积已经最大化了但是依然无法满足电子产品的实际设计需求(即BGA锡球2的外露面积依然不够大)时，可以采用丝网印刷工艺在BGA锡球2上设置辅助锡球6，再经过焊锡回流得到硅通孔芯片的二次封装体，其中，辅助锡球6高于二次封装体的表面，相当于增大了BGA锡球2的外露面积，从而进一步提高了BGA锡 球2与外界电气连接时的可靠性。如图13为设置辅助锡球6后切割得到的硅通孔芯片的二次封装体的单体。
值得一提的是，本实施例记载的技术方案也可基于本申请第二或者第三实施例的基础上实施。
本实施例提供的硅通孔芯片的二次封装方法与第四实施例相比，通过增加辅助锡球，进一步提高了BGA锡球与外界电气连接时的可靠性。
本申请的第六实施例涉及一种硅通孔芯片的二次封装方法。第五实施例是对第一实施例的细化，主要细化之处在于：请参考图14和图15，本实施例提供了对二次封装体的表面进行处理，以露出BGA锡球的第二种具体实现方式。
本实施例提供的硅通孔芯片的二次封装方法具体流程如图14所示。
其中，步骤1401至步骤1403与步骤301至步骤303对应大致相同，在此处不再赘述；不同之处在于：本实施例对步骤304进行了细化，并增加步骤1405，具体说明如下：
步骤1404，对二次封装体中对应于BGA锡球2的塑封胶部分进行局部去除，以露出BGA锡球2。
如图15所示，本实施例中，可以采用激光镭射、离子轰击、化学腐蚀中的其中之一或任意组合去除部分塑封胶，由于工艺特性所致，本实施例中仅去除对应于BGA锡球2的塑封胶部分，使BGA锡球2上方形成一个空腔区域21，这几种工艺可以用于去除二次封装体中不需要的材料，但是并不去除BGA锡球2。
步骤1405，在BGA锡球上设置辅助锡球6，且辅助锡球6高于或齐平 于表面。
如图16所示，由于BGA锡球2的外露面低于二次封装体的表面，所以本实施例中还需要设置辅助锡球6，填充到每个BGA锡球2对应的空腔区域21中，于实际中，可以采用丝网印刷工艺把焊锡印刷到空腔区域，或者采用落球工艺直接填充锡球到腔区域21，再经过回流工艺使得空腔区域21被完全填充；在设置辅助锡球6时，需使辅助锡球6高于或齐平于表面，以方便二次封装体与外界实现电气连接。图17为设置辅助锡球6后切割得到的硅通孔芯片的二次封装体的单体。
由上述分析可以看出，本实施例与本申请第四实施例分别提供了对二次封装体的表面进行处理，以露出所述BGA锡球的一种具体实现方式；区别之处在于：第一，在本申请第四实施例中，对二次封装体的表面进行处理时，采用的是研磨工艺，可以同时研磨掉部分塑封胶5与部分BGA锡球2，也可以仅研磨掉塑封胶5；而在本实施例中，对二次封装体的表面进行处理时，仅去除对应于BGA锡球2的塑封胶5部分，并不去除BGA锡球2；第二，在本申请第四实施例中，可以选择适用辅助锡球6；而在本实施例中，必须使用辅助锡球6。
值得一提的是，本实施例记载的技术方案也可基于本申请第二或者第三实施例的基础上实施。
本实施例提供的硅通孔芯片的二次封装方法与第一实施例相比，提供了对二次封装体的表面进行处理，以露出BGA锡球的第二种具体实现方式，且局部去除塑封胶的工艺与设置辅助锡球的工艺在本领域内较为常用，实现非常简单。
上面各种工艺方法的步骤划分，只是为了描述清楚，于实际操作中可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤。
本申请的第七实施例涉及一种硅通孔芯片的二次封装体，硅通孔芯片的二次封装体包括：请参考图11，硅通孔芯片1与塑封胶2；硅通孔芯片1具有正向表面11、反向表面12以及多个侧向表面；硅通孔芯片1的反向表面12设置有焊锡球2；塑封胶5包覆硅通孔芯片1的反向表面12与多个侧向表面，焊锡球2外露于塑封胶5的表面。
本实施例中，硅通孔芯片1为指纹识别芯片，硅通孔芯片1的正向表面11还包括指纹识别感应区13；焊锡球包括BGA锡球2，BGA锡球2外露于塑封胶5的表面，且BGA锡球2的外露面与塑封胶5的表面齐平，从而使BGA锡球2与外界实现电气互连。
于实际中，在对硅通孔芯片的二次封装体的表面进行处理时，可以采用研磨工艺去除部分塑封胶与部分BGA锡球，从而使BGA锡球2外露于塑封胶5的表面。
优选地，BGA锡球2的外露面为圆形，BGA锡球2的外露面与硅通孔芯片1的反向表面12的距离等于圆形的半径，此时BGA锡球2外露面的面积最大，尽量提高BGA锡球2与外界电气连接的可靠性。
本实施例提供的硅通孔芯片的二次封装体与现有技术相比，通过采用释放应力膜层，当塑封胶固化后，使得硅通孔芯片的二次封装体可以与铺设有释放应力膜层的底座分离，得到无基板形式的二次封装体，在保证硅通孔芯片具有较高机械结构强度的基础上，相较于基板封装形式降低了硅通孔芯片二次封装体的厚度，有助于电子产品的薄型化和小型化设计。
本申请的第八实施例涉及一种硅通孔芯片的二次封装体，本实施例与第六实施例大致相同，主要区别之处在于：在本申请第七实施例中，焊锡球包括BGA锡球2，BGA锡球2外露于塑封胶5的表面，且BGA锡球2的外露面与塑封胶5的表面齐平；而在本实施例中，请参考图13或17，焊锡球包括BGA锡球2与辅助锡球6，辅助锡球6外露于塑封胶5的表面，且辅助锡球6的外露面高于或者齐平于塑封胶5的表面。
本实施例中，BGA锡球2连接于硅通孔芯片的反向表面12，获得二次封装体后需要对硅通孔芯片的二次封装体的表面进行处理以使BGA锡球2外露，于实际中，可以采用激光镭射、离子轰击、化学腐蚀中的其中之一或任意组合，以去除对应于BGA锡球2的塑封胶，由于工艺特性所致，采用这几种工艺时并不去除BGA锡球，所以此时BGA锡球的外露面是低于二次封装体的表面的，因此需在BGA锡球2上设置辅助锡球6，使辅助锡球6连接于BGA锡球2，并使辅助锡球6外露于塑封胶5的表面，且辅助锡球6的外露面高于或者齐平于塑封胶5的表面。
优选地，当辅助锡球6的外露面高于塑封胶5的表面时，辅助锡球6的外露面高出塑封胶5的表面的距离是50um至300um之间，能够使得辅助锡球6有足够的外露面积以确保与外界之间电性连接的可靠性的同时，使得硅通孔芯片的二次封装体的整体厚度尽可能小。
本实施例提供的硅通孔芯片的二次封装体与第七实施例相比，提供了第二种硅通孔芯片的二次封装体的具体实现方式：通过在BGA锡球上设置辅助锡球以增大BGA锡球与外界的接触面积，以提高电气连接的可靠性。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实 施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (17)

  1. 一种硅通孔芯片的二次封装方法，其特征在于，所述硅通孔芯片具有相对的正向表面与反向表面，所述反向表面上设置有焊球阵列封装BGA锡球，所述硅通孔芯片的二次封装方法包括：
    将至少一硅通孔芯片放置在铺设有释放应力膜层的底座上；其中，所述硅通孔芯片的正向表面接触所述释放应力膜层；
    使用软化的塑封胶包覆所述硅通孔芯片；
    待所述塑封胶固化后去除所述底座，以获取所述硅通孔芯片的二次封装体；
    对所述二次封装体的表面进行处理，以露出所述BGA锡球；其中，被处理的所述二次封装体的表面与所述硅通孔芯片的反向表面相对应。
  2. 根据权利要求1所述的硅通孔芯片的二次封装方法，其特征在于，所述使用软化的塑封胶包覆所述硅通孔芯片中，具体包括：
    将具有空腔的注塑模具按压在所述底座上，使得所述硅通孔芯片位于所述空腔中；
    向所述空腔中注入软化的所述塑封胶，使得所述塑封胶包覆所述硅通孔芯片。
  3. 根据权利要求1所述的硅通孔芯片的二次封装方法，其特征在于，所述使用软化的塑封胶包覆所述硅通孔芯片中，具体包括：
    将软化的所述塑封胶涂布在所述硅通孔芯片上；
    利用压合模具对软化的所述塑封胶与所述硅通孔芯片进行压合，使得所述塑封胶包覆所述硅通孔芯片。
  4. 根据权利要求1至3中任一项所述的硅通孔芯片的二次封装方法，其特征在于，所述对所述二次封装体的表面进行处理，以露出所述BGA锡球中，具体包括：
    对所述二次封装体的表面进行研磨，以露出所述BGA锡球。
  5. 根据权利要求4所述的硅通孔芯片的二次封装方法，其特征在于，所述BGA锡球的外露面为圆形，所述BGA锡球的外露面与所述硅通孔芯片的反向表面的距离等于所述圆形的半径。
  6. 根据权利要求4或5所述的硅通孔芯片的二次封装方法，其特征在于，在所述对所述二次封装体的表面进行处理，以露出所述BGA锡球之后，还包括：
    在所述BGA锡球上设置辅助锡球；其中，所述辅助锡求高于所述表面。
  7. 根据权利要求1至3中任一项所述的硅通孔芯片的二次封装方法，其特征在于，所述对所述二次封装体的表面进行处理，以露出所述BGA锡球中，具体包括：
    对所述二次封装体中对应于所述BGA锡球的塑封胶部分进行局部去除，以露出所述BGA锡球；
    在所述对所述二次封装体的表面进行处理，以露出所述BGA锡球之后，还包括：
    在所述BGA锡球上设置辅助锡球，且所述辅助锡球高于或齐平于所述表面。
  8. 根据权利要求7所述的硅通孔芯片的二次封装方法，其特征在于，所述局部去除的方式包括激光镭射、离子轰击、化学腐蚀中的其中之一或任意组合。
  9. 根据权利要求1至8中任一项所述的硅通孔芯片的二次封装方法，其特征在于，所述硅通孔芯片的数目为多个；在所述对所述二次封装体的表面进行处理，以露出所述BGA锡球之后，还包括：
    对所述二次封装体进行切割，以获取单个所述硅通孔芯片的二次封装体。
  10. 一种硅通孔芯片的二次封装体，其特征在于，包括：硅通孔芯片与塑封胶；
    所述硅通孔芯片具有正向表面、反向表面以及多个侧向表面；所述硅通孔芯片的反向表面设置有焊锡球；
    所述塑封胶包覆所述硅通孔芯片的反向表面与多个侧向表面，所述焊锡球外露于所述塑封胶的表面。
  11. 根据权利要求10所述的硅通孔芯片的二次封装体，其特征在于，所述焊锡球包括BGA锡球；
    所述BGA锡球外露于所述塑封胶的表面，且所述BGA锡球的外露面与所述塑封胶的表面齐平。
  12. 根据权利要求11所述的硅通孔芯片的二次封装体，其特征在于，所述BGA锡球的外露面为圆形，所述BGA锡球的外露面与所述硅通孔芯片的反向表面的距离等于所述圆形的半径。
  13. 根据权利要求10所述的硅通孔芯片的二次封装体，其特征在于，所述焊锡球包括BGA锡球与辅助锡球，所述BGA锡球连接于所述硅通孔芯片的反向表面，所述辅助锡球连接于所述BGA锡球；
    所述辅助锡球外露于所述塑封胶的表面，且所述辅助锡球的外露面高于或者齐平于所述塑封胶的表面。
  14. 根据权利要求13所述的硅通孔芯片的二次封装体，其特征在于，当所述辅助锡球的外露面高于所述塑封胶的表面时，所述辅助锡球的外露面高出所述塑封胶的表面的距离为50um至300um之间。
  15. 根据权利要求10至14中任一项所述的硅通孔芯片的二次封装体，其特征在于，所述硅通孔芯片为指纹识别芯片，所述硅通孔芯片的正向表面包括指纹识别感应区。
  16. 根据权利要求15所述的硅通孔芯片的二次封装体，其特征在于，所述硅通孔芯片的正向表面设置有保护层，且所述保护层覆盖所述指纹识别感应区。
  17. 根据权利要求16所述的硅通孔芯片的二次封装体，其特征在于，所述保护层的厚度大于或等于5微米且小于或等于50微米。
PCT/CN2017/094695 2017-02-13 2017-07-27 硅通孔芯片的二次封装方法及其二次封装体 WO2018145413A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP17896308.8A EP3422397A4 (en) 2017-02-13 2017-07-27 METHOD FOR SECONDARY ENCLOSURE OF INTERCONNECTION HOLE CHIP THROUGH SILICON AND ITS SECONDARY HOUSING
CN201780010390.2A CN108780772B (zh) 2017-02-13 2017-07-27 硅通孔芯片的二次封装方法及其二次封装体
US16/139,994 US11183414B2 (en) 2017-02-13 2018-09-24 Secondary packaging method and secondary package of through silicon via chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CNPCT/CN2017/073354 2017-02-13
CNPCT/CN2017/073354 2017-02-13

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CNPCT/CN2017/073354 Continuation 2017-02-13 2017-02-13

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/139,994 Continuation US11183414B2 (en) 2017-02-13 2018-09-24 Secondary packaging method and secondary package of through silicon via chip

Publications (1)

Publication Number Publication Date
WO2018145413A1 true WO2018145413A1 (zh) 2018-08-16

Family

ID=63107896

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/094695 WO2018145413A1 (zh) 2017-02-13 2017-07-27 硅通孔芯片的二次封装方法及其二次封装体

Country Status (4)

Country Link
US (1) US11183414B2 (zh)
EP (1) EP3422397A4 (zh)
CN (1) CN108780772B (zh)
WO (1) WO2018145413A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331568B (zh) * 2020-11-04 2022-12-23 青岛歌尔微电子研究院有限公司 芯片防溢胶封装方法
TWM612841U (zh) * 2021-02-19 2021-06-01 安帝司股份有限公司 指紋辨識智慧卡
CN114055711B (zh) * 2021-11-18 2024-05-28 江苏芯德半导体科技有限公司 一种芯片塑封模具及其二次塑封工艺方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101465299A (zh) * 2007-12-20 2009-06-24 南茂科技股份有限公司 芯片重新配置的封装结构中使用研磨的制造方法
CN104485320A (zh) * 2014-12-30 2015-04-01 华天科技（西安）有限公司 一种有垂直通孔的埋入式传感芯片封装结构及其制备方法
CN104576424A (zh) * 2014-12-10 2015-04-29 华进半导体封装先导技术研发中心有限公司 通过预先在芯片上制备凸点实现扇出型晶圆封装的方法
CN105390429A (zh) * 2015-11-05 2016-03-09 南通富士通微电子股份有限公司 封装方法
CN105590911A (zh) * 2014-11-12 2016-05-18 精材科技股份有限公司 晶片封装体及其制造方法
CN105810599A (zh) * 2014-12-30 2016-07-27 深南电路有限公司 埋入指纹识别芯片的基板及其加工方法

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100246333B1 (ko) 1997-03-14 2000-03-15 김영환 비 지 에이 패키지 및 그 제조방법
JP4702586B2 (ja) * 2001-09-10 2011-06-15 日本電気株式会社 指紋センサ及び指紋センサ実装構造並びに該指紋センサを備えた指紋検出器
TW506097B (en) * 2001-10-17 2002-10-11 Apack Technologies Inc Wafer level chip scale package structure and its manufacturing method
US7626269B2 (en) * 2006-07-06 2009-12-01 Micron Technology, Inc. Semiconductor constructions and assemblies, and electronic systems
CN100565828C (zh) 2007-04-16 2009-12-02 日月光半导体制造股份有限公司 传感器芯片的封胶方法
US8236609B2 (en) * 2008-08-01 2012-08-07 Freescale Semiconductor, Inc. Packaging an integrated circuit die with backside metallization
US9196571B2 (en) * 2010-01-13 2015-11-24 Xintec Inc. Chip device packages and fabrication methods thereof
US8362612B1 (en) 2010-03-19 2013-01-29 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8717775B1 (en) * 2010-08-02 2014-05-06 Amkor Technology, Inc. Fingerprint sensor package and method
KR101789765B1 (ko) * 2010-12-16 2017-11-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8642385B2 (en) * 2011-08-09 2014-02-04 Alpha & Omega Semiconductor, Inc. Wafer level package structure and the fabrication method thereof
US8922013B2 (en) 2011-11-08 2014-12-30 Stmicroelectronics Pte Ltd. Through via package
CN103208430B (zh) 2012-01-17 2015-09-30 万国半导体股份有限公司 利用热压焊球在晶圆级塑封工艺中实现超薄芯片的方法
JP5728423B2 (ja) 2012-03-08 2015-06-03 株式会社東芝 半導体装置の製造方法、半導体集積装置及びその製造方法
KR101902996B1 (ko) * 2012-07-09 2018-10-01 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
JP6364626B2 (ja) * 2013-07-29 2018-08-01 パナソニックＩｐマネジメント株式会社 回折光学素子、回折光学素子の製造方法および回折光学素子の製造方法に用いられる型
KR20150121759A (ko) 2014-04-21 2015-10-30 에스티에스반도체통신 주식회사 적층형 패키지 및 그 제조방법
US9437566B2 (en) 2014-05-12 2016-09-06 Invensas Corporation Conductive connections, structures with such connections, and methods of manufacture
CN104102902B (zh) * 2014-07-04 2017-07-04 京东方科技集团股份有限公司 一种半导体指纹识别传感器及其制造方法
CN204011397U (zh) 2014-08-26 2014-12-10 南昌欧菲生物识别技术有限公司 电容式的指纹传感器封装结构
CN104201115A (zh) * 2014-09-12 2014-12-10 苏州晶方半导体科技股份有限公司 晶圆级指纹识别芯片封装结构及封装方法
CN104538373B (zh) 2014-12-30 2017-05-03 华天科技（昆山）电子有限公司 三维集成传感芯片封装结构及封装方法
CN104495741B (zh) 2014-12-30 2018-05-01 华天科技（昆山）电子有限公司 表面传感芯片封装结构及制作方法
CN107039369A (zh) 2015-01-23 2017-08-11 三星半导体(中国)研究开发有限公司 封装、包括该封装的封装堆叠结构及其制造方法
TWI614881B (zh) * 2015-01-28 2018-02-11 精材科技股份有限公司 感光模組及其製造方法
US9966358B2 (en) * 2015-06-17 2018-05-08 Xintec Inc. Chip package
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
TWI584418B (zh) * 2016-05-16 2017-05-21 Egis Tech Inc 指紋感測器及其封裝方法
CN106098717B (zh) 2016-08-05 2023-07-18 华天科技（昆山）电子有限公司 高可靠性芯片封装方法及结构
CN207038516U (zh) 2017-02-13 2018-02-23 深圳市汇顶科技股份有限公司 硅通孔芯片的二次封装体

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101465299A (zh) * 2007-12-20 2009-06-24 南茂科技股份有限公司 芯片重新配置的封装结构中使用研磨的制造方法
CN105590911A (zh) * 2014-11-12 2016-05-18 精材科技股份有限公司 晶片封装体及其制造方法
CN104576424A (zh) * 2014-12-10 2015-04-29 华进半导体封装先导技术研发中心有限公司 通过预先在芯片上制备凸点实现扇出型晶圆封装的方法
CN104485320A (zh) * 2014-12-30 2015-04-01 华天科技（西安）有限公司 一种有垂直通孔的埋入式传感芯片封装结构及其制备方法
CN105810599A (zh) * 2014-12-30 2016-07-27 深南电路有限公司 埋入指纹识别芯片的基板及其加工方法
CN105390429A (zh) * 2015-11-05 2016-03-09 南通富士通微电子股份有限公司 封装方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3422397A4 *

Also Published As

Publication number Publication date
CN108780772B (zh) 2023-07-14
EP3422397A4 (en) 2019-07-31
US11183414B2 (en) 2021-11-23
US20190027390A1 (en) 2019-01-24
EP3422397A1 (en) 2019-01-02
CN108780772A (zh) 2018-11-09

Similar Documents

Publication Publication Date Title
US11855029B2 (en) Semiconductor die connection system and method
KR100665777B1 (ko) 반도체장치 및 그 제조방법
US20170098628A1 (en) Semiconductor package structure and method for forming the same
US20100159643A1 (en) Bonding ic die to tsv wafers
TW202213677A (zh) 半導體裝置之製造方法
WO2001015223A1 (fr) Dispositif semi-conducteur et son procede de fabrication
JP2015504608A (ja) マイクロ表面実装デバイスパッケージング
WO2018145413A1 (zh) 硅通孔芯片的二次封装方法及其二次封装体
US8691625B2 (en) Method for making a chip package
US20140377886A1 (en) Method of manufacturing semiconductor device including grinding semiconductor wafer
TWI713849B (zh) 半導體製程及半導體結構
US7858446B2 (en) Sensor-type semiconductor package and fabrication method thereof
CN113270375A (zh) 半导体装置及其制造方法
US8652939B2 (en) Method and apparatus for die assembly
JP5840003B2 (ja) ウエーハの加工方法
CN101847588B (zh) 半导体工艺
JP7127680B2 (ja) 半導体装置及びその製造方法
US10290556B2 (en) High reliability wafer level semiconductor packaging
JP3330890B2 (ja) 樹脂封止型半導体装置及びその製造方法
TWI747404B (zh) 半導體封裝方法及封裝結構
JP3544655B2 (ja) 半導体装置
KR20210133898A (ko) 반도체 패키지 및 이의 제조방법
JP2013162022A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2017896308

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2017896308

Country of ref document: EP

Effective date: 20180925

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17896308

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE