JP2015504608A - マイクロ表面実装デバイスパッケージング - Google Patents
マイクロ表面実装デバイスパッケージング Download PDFInfo
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- JP2015504608A JP2015504608A JP2014543559A JP2014543559A JP2015504608A JP 2015504608 A JP2015504608 A JP 2015504608A JP 2014543559 A JP2014543559 A JP 2014543559A JP 2014543559 A JP2014543559 A JP 2014543559A JP 2015504608 A JP2015504608 A JP 2015504608A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 45
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 71
- 229910000679 solder Inorganic materials 0.000 claims abstract description 40
- 239000004033 plastic Substances 0.000 claims abstract description 28
- 239000000565 sealant Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 88
- 239000000463 material Substances 0.000 claims description 33
- 238000000227 grinding Methods 0.000 claims description 15
- 238000007789 sealing Methods 0.000 claims description 13
- 238000007650 screen-printing Methods 0.000 claims description 11
- 238000007639 printing Methods 0.000 claims description 5
- 239000003566 sealing material Substances 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 3
- 238000001721 transfer moulding Methods 0.000 claims description 3
- 239000012812 sealant material Substances 0.000 claims description 2
- 238000013459 approach Methods 0.000 abstract description 17
- 239000010410 layer Substances 0.000 description 47
- 235000012431 wafers Nutrition 0.000 description 10
- 239000000969 carrier Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000000608 laser ablation Methods 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- 238000000465 moulding Methods 0.000 description 5
- 239000000945 filler Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract
Description
Claims (15)
- 集積回路をパッケージする方法であって、
プラスチックキャリア上に複数のダイを搭載することであって、前記ダイの各々が、それに固定されるワイヤボンディングされたコンタクトスタッドを有する複数のI/Oパッドを含むこと、
封止材キャリア構造を形成するため前記ダイを封止材材料で覆うことであって、前記封止材材料がスクリーン印刷及びステンシル印刷の一方により付けられること、
前記コンタクトスタッドの露出された部分が、滑らかで、且つ、前記封止材の第1の表面と実質的に同一平面にあるように、前記封止材の前記第1の表面及び前記コンタクトスタッドをグラインドすること、
前記封止材キャリア構造の上に導電性再分配構造を形成することであって、前記コンタクトスタッドの少なくとも幾つかが前記導電性再分配構造と電気的に通信しており、前記導電性再分配構造が複数のはんだパッドを含み、前記はんだパッドの各々が関連するコンタクトスタッドに電気的に接続され、前記はんだパッドの少なくとも幾つかが、それらの関連するコンタクトスタッドの中心に対してオフセットされる中心を有すること、
前記はんだパッド上にはんだバンプをつくること、及び
前記コンタクトバンプの少なくとも一部を埋め込み、且つ、前記再分配構造を覆う、前記封止材キャリア構造の上に第2の封止層を付けること、
を含む、方法。 - 請求項1に記載の方法であって、
前記キャリアの裏面の前記グラインドの前に、前記第2の封止材層の露出された頂部表面から前記キャリアへ延びるシンギュレーション溝を切り込むこと、及び
前記シンギュレーション溝の形成後、前記キャリアを薄化するように、しかし前記キャリアを完全には犠牲にしないように前記キャリアの裏面をグラインドすることであって、それにより、その裏面グラインドの後、前記キャリア及び前記封止材材料の関連する部分により各ダイが囲まれるようにして、前記ダイのいかなる部分も周囲光に露出されないようにすること、
を更に含み、
前記キャリアの裏面の前記グラインドが、前記シンギュレーション溝を露出させるために充分な前記キャリアを犠牲にし、それにより、複数の個別のパッケージを形成するため前記封止材キャリア構造のシンギュレーションを達成する、
方法。 - 請求項1に記載の方法であって、前記第2の封止材が付けられた後、はんだバンプの一部をレーザーデフラッシュすることを更に含む、方法。
- 請求項1に記載の方法であって、前記キャリアがトランスファモールディングにより形成される、方法。
- 請求項1に記載の方法であって、前記第2の封止材層がスクリーン印刷により付けられる、方法。
- 集積回路をパッケージングする方法であって、
キャリア上に複数のダイを搭載することであって、前記ダイの各々が、それに固定されるワイヤボンディングされたコンタクトスタッドを有する複数のI/Oパッドを含むこと、
封止材キャリア構造を形成するため前記ダイと前記コンタクトスタッドの少なくとも一部とを封止材材料で覆うこと、及び
前記コンタクトスタッドの露出された部分が、滑らかで、且つ、実質的に前記封止材と同一平面上となるように、前記封止材の第1の表面及び前記コンタクトスタッドをグラインドすること、
を含む、方法。 - 請求項6に記載の方法であって、前記封止材材料が、スクリーン印刷及びステンシル印刷の一方により付けられる、方法。
- 請求項6に記載の方法であって、
前記封止材キャリア構造の上に導電性再分配構造を形成することであって、前記コンタクトスタッドの少なくとも幾つかが前記導電性再分配構造と電気的に通信しており、前記導電性再分配構造が複数のはんだパッドを含み、前記はんだパッドの各々が関連するコンタクトスタッドに電気的に接続され、前記はんだパッドの少なくとも幾つかが、それらの関連するコンタクトスタッドの中心に対してオフセットされる中心を有すること、及び
前記はんだパッド上にはんだバンプをつくること、
を更に含む、方法。 - 請求項8に記載の方法であって、はんだバンプの少なくとも一部を埋め込み、且つ、前記再分配構造を覆う前記封止材キャリア構造の上に第2の封止材を付けることを更に含む、方法。
- 請求項9に記載の方法であって、前記第2の封止材を付けた後、前記キャリアを薄化するように、しかし前記キャリアを完全には犠牲にしないように前記キャリアの裏面をグラインドすることであって、それにより、その裏面グラインドの後、各ダイが前記キャリア及び前記封止材材料の関連する部分により囲まれるようにし、そのため、前記ダイのどの部分も周囲光に露出されないようにすることを更に含む、方法。
- 請求項10に記載の方法であって、
前記封止材キャリア構造の頂部表面から前記キャリアへ延びるシンギュレーション溝を切り込むことを更に含み、
前記シンギュレーション溝が、前記第2の封止材を付けた後であり、且つ、前記キャリアの前記裏面の前記グラインド前に切り込まれ、
前記キャリアの前記裏面の前記グラインドが、前記シンギュレーション溝を露出させるために充分な前記キャリアを犠牲にし、それにより、複数の個別のパッケージを形成するため前記封止材キャリア構造のシンギュレーションを達成する、
方法。 - 請求項6に記載の方法であって、前記キャリアを薄化するように、しかし前記キャリアを完全には犠牲にしないように前記キャリアの裏面をグラインドすることであって、それにより、その裏面グラインドの後、前記キャリア及び前記封止材材料の関連する部分により各ダイが囲まれるようにして、前記ダイのいかなる部分も周囲光に露出されないようにすることを更に含む、方法。
- 請求項12に記載の方法であって、
前記キャリアの前記裏面の前記グラインドの前に、前記封止材キャリア構造の頂部表面から前記キャリアへ延びるシンギュレーション溝を切り込むことを更に含み、
前記キャリアの前記裏面のグラインドが、前記シンギュレーション溝を露出させるために充分な前記キャリアを犠牲にし、それにより、複数の個別のパッケージを形成するため前記封止材キャリア構造のシンギュレーションを達成する、
方法。 - 請求項6に記載の方法であって、前記キャリアがプラスチックから形成される、方法。
- マイクロ表面実装集積回路パッケージであって、
プラスチックベース、
前記プラスチックベース上に搭載され、上に複数のボンドパッドを有するダイ、
各々関連するボンドパッドに取り付けられる複数のワイヤボンディングされたスタッドバンプ、
前記ダイを覆い、且つ、前記ダイのどの部分も周囲光に露出されないように前記ダイを入れるため前記プラスチックベースと協働するプラスチック封止材材料であって、前記スタッドバンプの頂部表面が、滑らかで、且つ、前記プラスチック封止材材料の頂部表面と実質的に平行である、前記プラスチック封止材材料、
前記プラスチック封止材材料の上に形成される導電性再分配層であって、前記再分配層が複数のはんだパッドを含み、前記再分配層が、関連するスタッドバンプを関連するはんだパッドに電気的に接続するトレースを含み、前記はんだパッドの少なくとも幾つかが、それらの関連するスタッドバンプに対して横方向にオフセットされる、前記導電性再分配層、
各々関連するはんだパッドに電気的に接続される複数のはんだコンタクト、及び
前記導電性再分配層を覆うコンタクト封止材層であって、前記はんだコンタクトが少なくとも部分的に前記コンタクト封止材層に埋め込まれる、前記コンタクト封止材層、
を含む、マイクロ表面実装集積回路パッケージ。
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