CN110867414B - 保形虚设管芯 - Google Patents

保形虚设管芯 Download PDF

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CN110867414B
CN110867414B CN201910795126.5A CN201910795126A CN110867414B CN 110867414 B CN110867414 B CN 110867414B CN 201910795126 A CN201910795126 A CN 201910795126A CN 110867414 B CN110867414 B CN 110867414B
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die
dummy
wafer
dummy die
semiconductor
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CN110867414A (zh
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安托尼斯·亨德里库斯·尤立夫·坎菲斯
阿马尔·阿肖克·马维库夫
耶斯特·德威特
安德瑞-亚历山大·戴米安
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NXP BV
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Abstract

本文提供了封装半导体装置和其制造方法的实施例，所述封装半导体装置包括：半导体管芯，所述半导体管芯在有源侧上具有多个焊盘；虚设管芯，所述虚设管芯具有多个从第一主表面延伸到与所述第一主表面相对的第二主表面的开口，其中所述多个开口与所述多个焊盘对齐；以及硅基胶水，所述硅基胶水将所述虚设管芯附接到所述半导体管芯的所述有源侧，其中所述半导体管芯的多个可接合表面通过所述虚设管芯的所述多个开口暴露。

Description

保形虚设管芯
技术领域
本公开总体上涉及封装半导体装置，并且更具体地说，涉及保护包括在封装半导体装置中的半导体管芯的敏感区域。
背景技术
半导体管芯是形成于如硅晶片等半导体晶片上的小型集成电路(IC)。这种管芯通常从晶片上切割而来并且通常使用引线框架进行封装。引线框架是支撑管芯并且为封装管芯提供外部电连接的金属框架。引线框架通常包括管芯标记和引线指(lead finger)(或引线)。半导体管芯附接到所述标记，并且管芯上的接合焊盘用接合线电连接到引线框架的引线。管芯和接合线用包封剂覆盖以形成半导体管芯封装体。引线从包封体(encapsulation)向外凸出或至少与包封体齐平以便可以将引线用作端，从而允许封装管芯电连接到其它装置或印刷电路板(PCB)。
发明内容
根据本发明的第一方面，提供一种封装半导体装置，所述封装半导体装置包括：
半导体管芯，所述半导体管芯在有源侧上具有多个焊盘；
虚设管芯，所述虚设管芯具有多个从第一主表面延伸到与所述第一主表面相对的第二主表面的开口，其中所述多个开口与所述多个焊盘对齐；以及
硅基胶水，所述硅基胶水将所述虚设管芯附接到所述半导体管芯的所述有源侧，其中所述半导体管芯的多个可接合表面通过所述虚设管芯的所述多个开口暴露。
在一个或多个实施例中，所述虚设管芯的每个开口与所述半导体管芯的相应焊盘对齐，并且
所述虚设管芯的一部分定位于相邻焊盘之间。
在一个或多个实施例中，所述虚设管芯的周边对应于所述半导体管芯的周边。
在一个或多个实施例中，所述半导体管芯在所述有源侧上包括应力敏感区域，其中所述虚设管芯覆盖所述应力敏感区域。
在一个或多个实施例中，所述虚设管芯的周边延伸超出所述应力敏感区域的周边最小距离。
在一个或多个实施例中，所述应力敏感区域在所述半导体管芯上的所述多个焊盘中的至少一个焊盘下方延伸。
在一个或多个实施例中，所述虚设管芯的厚度处于10微米与100微米之间的范围内。
在一个或多个实施例中，所述硅基胶水的厚度处于20微米与50微米之间的范围内。
在一个或多个实施例中，所述多个开口的一部分定位于所述虚设管芯的外围部分中。
在一个或多个实施例中，所述多个开口的一部分定位于所述虚设管芯的中心部分中。
在一个或多个实施例中，所述多个焊盘的顶表面提供所述多个可接合表面。
在一个或多个实施例中，所述封装半导体装置进一步包括：
多个柱形凸块，所述多个柱形凸块形成于所述多个焊盘上，其中所述多个柱形凸块的顶表面提供所述多个可接合表面。
在一个或多个实施例中，所述封装半导体装置进一步包括：
所述硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个柱形凸块，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的有源表面上方提供密封屏障。
在一个或多个实施例中，所述封装半导体装置进一步包括：
凸块下金属化(UBM)层，所述UBM层形成于所述多个焊盘上，其中所述多个焊盘上的所述UBM层的顶表面提供所述多个可接合表面。
在一个或多个实施例中，所述封装半导体装置进一步包括：
多个焊料凸块，所述多个焊料凸块附接到所述多个焊盘上的所述UBM层，以及
所述硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个焊料凸块，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的所述有源表面上方提供密封屏障。
在一个或多个实施例中，所述封装半导体装置进一步包括：
多个球形接合，所述多个球形接合附接到所述虚设管芯的每个开口内的所述多个可接合表面。
在一个或多个实施例中，所述封装半导体装置进一步包括：
硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个球形接合，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的所述有源表面上方提供密封屏障。
在一个或多个实施例中，所述封装半导体装置进一步包括：
引线框架，所述引线框架具有管芯标记和多个引线指，其中
所述半导体管芯的背侧用管芯附接材料附接到所述管芯标记，并且
所述多个球形接合是多个引线接合互连的一部分，所述多个引线接合互连还包括附接到所述多个引线指的尾部接合。
在一个或多个实施例中，所述封装半导体装置进一步包括：
包封体，所述包封体包封所述引线框架、所述半导体管芯、所述虚设管芯和所述多个引线接合互连。
在一个或多个实施例中，所述半导体管芯是作为半导体管芯晶片的一部分的多个半导体管芯之一，
所述虚设管芯是作为虚设管芯晶片的一部分的多个虚设管芯之一，并且
所述硅基胶水将所述虚设管芯晶片附接到所述半导体管芯晶片，其中所述多个半导体管芯中的每一个半导体管芯的所述多个可接合表面通过所述多个虚设管芯中的每一个虚设管芯的所述多个开口暴露。
本发明的这些和其它方面将根据下文中所描述的实施例显而易见，且参考这些实施例予以阐明。
附图说明
通过参考附图，可以更好地理解本发明并且可以使本发明的众多目的、特征和优点对于本领域的技术人员来说是显而易见的。
图1A-1D、2A-2D和3A-3C是描绘了根据本公开的一些实施例的用于制造示例封装半导体装置的各个步骤的框图。
图4A-4F和5A-5D是描绘了根据本公开的一些实施例的用于制造示例半导体装置的各个晶片级步骤的框图。
图6、7A-7B和8A-8D是描绘了根据本公开的一些实施例的示例封装半导体装置的其它各个方面的框图。
图9A-9D是描绘了根据本公开的一些实施例的用于制造示例半导体装置的其它各个晶片级步骤的框图。
本发明是通过举例来说明的并且不受附图限制，在附图中，类似的附图标记表示类似的元件，除非另有指明。附图中的元件是为了简单和清楚起见而示出的并且不一定按比例绘制。
具体实施方式
下文阐述了旨在说明本发明的各个实施例的详细描述并且不应被认为是限制性的。
概述
半导体管芯的顶侧或有源侧上的某些区域可能对由于CTE(热膨胀系数)不匹配的非对称封装体中的温度变化而产生的应力敏感。这可能导致严重的机械应力，如高度封装体翘曲。一些常规方法包括应力缓冲器，如半导体管芯上的聚酰亚胺层或芯片涂层。然而，这种层覆盖晶片上的接合焊盘，从而需要另外的加工步骤以暴露接合焊盘。这种芯片涂层通常很厚(例如，大于50微米)并且其放置精度不足以获得一致结果。
本公开提供了一种保护方案，其中用硅基胶水将虚设管芯附接到半导体管芯的有源侧上的应力敏感区域。虚设管芯包括穿过虚设管芯的多个开口，所述开口与下方的半导体管芯上的接合焊盘对齐，其中当附接到半导体管芯时，每个开口侧向地包围一个或多个接合焊盘。虚设管芯在半导体管芯上形成外部连接之前，如在引线接合之前或焊料球落下之前，附接到半导体管芯，其中引线接合(如球形接合)或焊料球穿过虚设管芯中的开口形成于接合焊盘上。
虽然可以单独地将虚设管芯附接到每个半导体管芯，但是一些实施例提供了晶片级过程期间的附接，其中可以将虚设管芯晶片附接到半导体管芯晶片。在一些实施例中，虚设管芯晶片首先减薄到预定厚度并且之后附接到半导体管芯晶片。在其它实施例中，具有原始(生产)厚度的虚设管芯晶片首先附接到半导体管芯晶片，之后虚设管芯晶片被背面研磨到期望厚度，所述期望厚度可以小于通过在附接之前减薄虚设管芯晶片实现的预定厚度。虚设管芯晶片级附接还在晶片测试、对半导体管芯晶片的背面研磨和将组合晶片(其包括用硅基胶水附接到半导体管芯晶片的虚设管芯晶片)单切成多个单独装置(也被称为组合管芯)期间保护半导体管芯晶片，其中组合管芯包括用硅基胶水附接到半导体管芯的虚设管芯两者。
此外，减薄单独的虚设管芯晶片或单独的半导体管芯晶片可能导致晶片破坏(例如，当在背面研磨期间经历的力超过单独的虚设管芯晶片或单独的半导体管芯晶片的机械强度时)。虚设管芯晶片级附接为增强型组合晶片提供提高的机械强度，所述提高的机械强度可以降低在对虚设管芯晶片的背面研磨期间或在对半导体管芯晶片的背面研磨期间发生的晶片破坏的风险。相比于在附接之前单独减薄晶片，虚设管芯晶片级附接还可以产生具有更薄的虚设管芯晶片、更薄的半导体管芯晶片或两者的组合晶片。
硅基胶水在半导体管芯的有源侧上提供气密且防潮的密封，从而保护有源侧上的敏感区域不受因温度变化或其它机械源引起的各种应力的影响。在一些实施例中，因为硅基胶水在高温下具有抗氧化性，所以选择硅基胶水，即使示在极端温度偏移期间，如在静电放电(ESD)事件或其它使半导体管芯在其正常操作参数之外操作的事件期间，所述硅基胶水也为应力敏感区域提供另外的保护。
在一些实施例中，敏感区域可以位于一个或多个接合焊盘下方。虚设管芯通过覆盖接合焊盘周围和接合焊盘之间(例如，所形成的到那些接合焊盘的引线接合连接之间)的空隙区域来提供对那些下方的敏感区域的保护。在一些实施例中，还可以向虚设管芯施加压力以使硅基胶水均匀分布从而沿着有源侧形成一致的密封屏障并且在接合焊盘的边缘以及引线接合或其它连接结构(如焊料球或凸块)的侧面上方和周围形成硅基胶水的胶瘤(fillet)。接触接合焊盘和引线接合的胶瘤另外密封虚设管芯中的开口内的这些区域，否则，所述开口可能是缺乏由胶水形成的保护屏障的空隙。
示例实施例
图1A-1D示出了用于制造包括虚设管芯的封装半导体装置的示例过程流程中的各个步骤的横截面视图。图1A示出了封装半导体装置的各个部件，所述封装半导体装置包括半导体管芯102、具有管芯标记108和多条引线110的引线框架以及虚设管芯112。可以以多种方式组合这些部件，如下文另外论述的。
半导体管芯102具有有源侧103和相对的背侧105。半导体管芯102还具有垂直于有源侧103和背侧105的侧边缘或外边缘107。有源侧103包括多个焊盘106，所述焊盘106可以布置在有源侧103上的各个位置中。在所示出的实施例中，焊盘106定位在半导体管芯102的外围附近，但在其它实施例中，焊盘106还可以居中定位在半导体管芯102上(例如，如图3A所示那样)。焊盘106可以以实施一个或多个如行等规则图案或一个或多个不规则图案(例如，如图3A所示那样)或两者的布局布置在有源侧103上。每个焊盘106可以电耦合到在有源侧103附近定位在半导体管芯102上的有源电路系统。敏感区域104也定位在有源侧103上。敏感区域104是半导体管芯102的某个区域，所述区域对如由于部件具有不匹配的CTE(热膨胀系数)而产生的温度变化引起的热应力、由封装体翘曲(例如，包封体翘曲)或包封体的物理损坏引起的机械应力等应力敏感或对其它电热应力敏感。
应注意，半导体管芯(如半导体管芯102)可以由半导体晶片(也被称为半导体管芯晶片)形成(例如，从半导体晶片单切而来)，所述半导体晶片可以是任何半导体材料或如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅等材料的组合以及上述各项的组合。半导体管芯(如半导体管芯102)的有源电路系统使用应用于半导体晶片的一系列许多工艺步骤形成于硅晶片上，所述工艺步骤包括但不限于：沉积包括介电材料和金属在内的半导体材料，如生长、氧化、溅射和保形沉积；蚀刻半导体材料，如使用湿蚀刻剂或干蚀刻剂；使半导体材料平坦化，如执行化学机械抛光或平坦化；执行光刻以实现图案化，包括沉积和去除光刻掩膜或其它光刻胶材料；离子注入；退火等。有源电路系统的例子包括但不限于：如处理器、存储器、逻辑、模拟电路系统、传感器、MEMS(微机电系统)装置等集成电路部件；如电阻器、电感器、电容器、二极管、功率晶体管等独立式分立装置；等。在一些实施例中，有源电路系统可以是以上所列的集成电路部件的组合或者可以是另一种类型的微电子装置。
引线框架是机械地支撑一个或多个如半导体管芯等可以附接到引线框架的管芯标记(如附接到管芯标记108的半导体管芯102，如图1B所示)的电子部件并且通过引线框架的引线(如引线110)为所述部件提供外部电连接的导电框架。引线框架由导电材料形成，所述导电材料的例子包括但不限于铜、镍或其它适合的导电材料或由一种或多种适合的导电材料构成的合金。还可以用导电材料涂覆引线110上的电连接接触区域，所述导电材料的例子包括但不限于镍、金、铜、铝、锡或其它适合的导电金属或由一种或多种适合的导电材料构成的合金。图1A中示出的引线框架可以是单独的引线框架或可以是包括多个引线框架的引线框架阵列中的代表性引线框架。
虚设管芯(如虚设管芯112)是硅或玻璃的一部分，其可以由晶片形成(例如，从晶片单切而来)，所述晶片还被称为虚设管芯晶片。虚设管芯晶片可以是任何半导体材料或如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅等材料的组合以及上述各项的组合。通常，虚设管芯(如虚设管芯112)的厚度小于半导体管芯的厚度。在一些实施例中，虚设管芯112的厚度处于10微米到100微米的范围内，如50微米。在一些实施例中，虚设管芯112的CTE(热膨胀系数)与半导体管芯102的CTE基本上类似(例如，如当虚设管芯112和半导体管芯102两者由同一类型或类似类型的硅形成时)。虚设管芯112的厚度可以通过多种方式实现，包括在下文另外论述的在晶片级过程期间附接到半导体管芯晶片之前或之后进行的背面研磨。
为了实现具有一致CTE的足够薄的轮廓，虚设管芯112不包括任何内部有源电路系统。虚设管芯112包括多个对应于半导体管芯102的有源侧103上的焊盘106的布局的开口116。开口116从虚设管芯112的顶表面111延伸到底表面113。虚设管芯112还具有垂直于顶表面111和底表面113的侧边缘或外边缘109。虚设管芯112被配置成附接到半导体管芯102的有源侧103，其中每个开口116被配置成对齐到并且包围半导体管芯102上的至少一个焊盘106。在一些实施例中，每个开口116可以被配置成包围多于一个焊盘106，如下文结合图3A另外论述的(例如，其中开口318包围三个焊盘106)。
虚设管芯112被配置成覆盖有源侧103的至少包括敏感区域104的一部分，以保护敏感区域104不受各种应力的影响，如下文结合图1B另外论述的。在各个实施例中，虚设管芯112的尺寸可以包括高达半导体管芯102的整个尺寸。例如，图1A示出了侧向尺寸与半导体管芯102的侧向尺寸相同(或基本相同)的虚设管芯112，其中虚设管芯112的侧边缘109与半导体管芯102的侧边缘107对齐，并且其中开口116与下方的焊盘106对齐(如虚线所示)。在这种实施例中，当虚设管芯112附接到半导体管芯102时，虚设管芯112覆盖整个有源侧103(包括敏感区域104上方)。图6示出了另一个实施例，其中当虚设管芯112附接到半导体管芯102时，虚设管芯112部分覆盖有源侧103(至少包括覆盖敏感区域104上方)，包括包围至少一个焊盘106的开口116，如下文另外论述的。
如图1A所示，硅基胶水114施涂到虚设管芯112的底表面113。硅基胶水114被配置成将虚设管芯112附接到半导体管芯102的有源侧103，如下文另外论述的。硅基胶水114是包括具有粘附特性的一种或多种硅酮聚合物的材料。硅酮聚合物包括硅氧烷的重复单元(也称为聚硅氧烷)作为其它元件、有机基团或官能团可以附接的主链结构。在所示出的实施例中，硅基胶水114通常具有低模量和凝胶状粘度，以形成在不阻挡开口116的情况下基本上保持处于虚设管芯112上的适当位置处的薄的、柔性的且顺应性的粘合层。在一些实施例中，硅基胶水114层的厚度可以处于20微米到50微米的范围内，如30微米。在一些实施例中，硅基胶水114层的厚度可以更大，如处于50微米到100微米的范围内。在将虚设管芯112附接到半导体管芯102时，可以向虚设管芯112施加压力以确保硅基胶水114与有源侧103进行充分接触并且使胶水114扩散从而消除有源侧103上的任何空隙或侧向地包围如引线接合或焊料球等连接，如下文结合图5C和7B另外论述的。在一些实施例中，硅基胶水114优选地基于其在高温(例如，350℃或更高)下的抗氧化性而被选择，如下文另外论述的。
图1A示出了用硅基胶水114将单独的虚设管芯112附接到单独的半导体管芯102，其中虚设管芯112可以从虚设管芯晶片单切而来。在一些实施例中，可以将硅基胶水114施涂到整个虚设管芯晶片，并且然后可以将虚设管芯晶片单切成各自在底表面113上具有硅基胶水114层的多个虚设管芯112，以便进行如图1A所示出的单独附接。当虚设管芯112的侧向尺寸或占用空间比半导体管芯102的侧向尺寸小时，这种实施例可能是有益的。
在虚设管芯112的侧向尺寸与半导体管芯102的侧向尺寸相同或基本相同的其它实施例中，作为晶片级过程，可以将硅基胶水114施涂到整个虚设管芯晶片并之后将所述虚设管芯晶片附接到半导体管芯晶片。在这种实施例中，可以首先减薄虚设管芯晶片并且之后将其附接到半导体管芯晶片(如下文结合图4A-4D所论述的)，或者可以首先将具有生产厚度的虚设管芯晶片附接到半导体管芯晶片并且之后减薄所述虚设管芯晶片(如下文结合图9A-9C所论述的)。然后，可以将所得组合晶片单切成多个组合管芯，所述多个组合管芯中的每个组合管芯包括附接到半导体管芯102的结构如图1B中示出的结构的虚设管芯112(然后可以用管芯附接材料118将所述半导体管芯102附接到管芯标记108，如下文所论述的)。
应注意，虚设管芯晶片可以由具有原始厚度或生产厚度的空白晶片形成，其中可以在虚设管芯晶片的表面中形成多个具有某一深度的凹部。在一些实施例中，虚设管芯晶片被减薄成具有对应于凹部的深度的厚度以便暴露或敞开凹部从而形成穿过虚设管芯晶片的开口116。可以在附接之前(如下文结合图4A-4C所论述的)或附接之后(如下文结合图9A-9C所论述的)减薄虚设管芯晶片。应注意，在一些实施例中，图4B、图4C或图5A示出的所得虚设管芯晶片可以被另外单切成单独的虚设管芯112以进行单独附接。
在一些实施例中，在将硅基胶水114施涂(其可以是用于喷涂、丝网印刷或旋转涂覆的有利形式)到虚设管芯112或虚设管芯晶片时，硅基胶水114可以呈无定形形式，优选地具有足以阻止非预期的涂抹或扩散的粘度。在一些实施例中，硅基胶水114可以以压敏粘合剂的形式(例如，以薄膜预成型品的形式)提供，所述压敏粘合剂当被按压时提供到虚设管芯112或虚设管芯晶片的充分粘附。在一些实施例中，硅基胶水114可以在不进行固化步骤的情况下提供到虚设管芯112或虚设管芯晶片(以及到半导体管芯102)的充分粘附。
在一些实施例中，硅基胶水114可以是可以施涂到虚设管芯112或虚设管芯晶片上的可固化材料。例如，胶水114在施涂(例如，喷涂、丝网印刷或旋转涂覆)到虚设管芯112或虚设管芯晶片时可以具有较低粘度，并且之后可以被部分固化(例如，暴露于热或紫外(UV)线以触发交联反应，从而使较低粘度胶水部分硬化)以形成较高粘度胶水114层。在一些实施例中，一旦虚设管芯112附接到半导体管芯102，如图1B所示，就可以完全固化胶水114(例如，通过热或UV线接触完成交联反应以形成固体聚合物层)。
在另一个例子中，可以以B阶薄膜预成型品的形式提供胶水114。B阶薄膜预成型品可以大到足以覆盖单独的虚设管芯112或整个虚设管芯晶片。在一些实施例中，B阶薄膜预成型品可以是实心板或可以包括多个对应于单独的虚设管芯112中或整个虚设管芯晶片中的开口116的开口。在一些实施例中，一旦虚设管芯112附接到半导体管芯102，如图1B所示，就可以完全固化B阶薄膜预成型品。
图1B示出了用硅基胶水114附接到半导体管芯102的有源侧103的虚设管芯112，同时焊盘106保持通过虚设管芯112和胶水114两者暴露，从而提供可接合表面。硅基胶水114在半导体管芯102的表面处形成气密且防水的密封，从而阻止周围环境中的氧气和各种污染物到达敏感区域104。例如，电子装置可能在个别情况下经历电气过应力，其中如当电容器通过不总是可能实现主动的设备上保护的背栅二极管放电时接收到装置的正常操作范围外的电信号。电气过应力可能使装置在正常参数外操作，从而引起可能达到数百度(例如，350℃或更大)的温度偏移。如果在装置周围存在包封体，则高温可能对包封体造成氧化或损坏，使得下方的装置可能暴露于来自周围环境的污染物离子以及由于碎屑引起的可能的物理损坏，所述污染物离子将装置置于电迁移失效的危险中，所述电迁移失效进而可能引起电热失效。相比之下，在半导体管芯102的有源侧103上方存在的硅基胶水114被配置成在类似的温度偏移期间保持完整，这保护下方的敏感区域104不受周围环境暴露的影响，即使包封体变得损坏也是如此。在一些实施例中，优选的是，硅基胶水114以最小的侧向裕度或距离包围敏感区域104，以确保敏感区域104被充分密封，如下文结合图6另外论述的。
如上文所指出的，可以通过多种方式组合图1A中示出的虚设管芯112、半导体管芯102和引线框架以产生图1B中示出的装置。在一些实施例中，可以首先将虚设管芯112附接到半导体管芯102的有源侧103(图1A中示出为顶部箭头)，并且之后用管芯附接材料118将半导体管芯102的背侧105附接到管芯标记108(图1A中示出为底部箭头)。在其它实施例中，首先用管芯附接材料118将背侧105附接到管芯标记108(图1A中的底部箭头)，并且之后将虚设管芯112附接到有源侧103(图1A的顶部箭头)。进一步地，在形成组合管芯(例如，虚设管芯晶片和半导体管芯晶片被附接并且单切成多个组合管芯)的实施例中，用管芯附接材料118将组合管芯中存在的半导体管芯102的背侧105附接到管芯标记108。
管芯附接材料118具有用于将半导体管芯102附接到管芯标记108的粘附特性以及用于将热从半导体管芯102转移到管芯标记108的导热特性。管芯附接材料118的例子包括但不限于焊料合金、聚酰亚胺、硅酮或含有如碳纳米管或氧化铍、氮化铝、氮化硼或金刚石粉末等悬浮填料的基于环氧树脂的材料。
图1C示出了在执行引线接合步骤以产生多个引线接合连接120之后产生的装置。每个引线接合连接120包括如球形接合等形成于相应焊盘106上的第一引线接合122，其中导线从第一引线接合延伸到如针脚式接合或尾部接合(tail bond)等形成于相应引线110上的第二引线接合124。在所示出的实施例中，每个开口116紧密跟随相应焊盘106的周边，从而允许通过虚设管芯112中的开口116将引线接合形成到焊盘106的可接合表面上，同时硅基胶水114保持处于相应焊盘106的周边外部。在一些实施例中，开口116的周边可以比下方的焊盘106大，如50微米，从而将开口116的较大周边与下方的焊盘106的周边侧向分离。这还在将虚设管芯112放置并附接到半导体管芯102上所需的精度方面提供某一容差。当以晶片级附接虚设管芯112和半导体管芯102时，可以进一步提高容差，如下文另外论述的(例如，+/-5微米的精度是充分的)。
在一些实施例中，可以在焊盘106上形成如焊料球或凸块等其它连接，如图5C所示那样。在一些实施例中，每个焊盘106可以包括由提高到焊盘106的连接(如引线接合或焊料球)的润湿性和粘附性的一种或多种导电材料构成的涂层，所述导电材料的例子包括但不限于镍、金、铜、铝、钛、钨、铬、钯或其它合适的导电金属或由一种或多种合适的导电金属构成的合金。在各个实施例中，还可以在焊盘106周围实施焊接掩膜以形成焊接掩模限定(SMD)焊盘或非焊接掩膜限定(NSMD)焊盘。
图1D示出了在执行包封步骤以产生包封体126之后产生的装置，所述包封体126包封管芯标记108、半导体管芯102、虚设管芯112和引线接合连接120。虽然引线110在图1D中被示出为终止于包封体126的外周边处，但在其它实施例中，引线110可以延伸超过包封体126的外周边。虽然在图1D中管芯标记108被包封体126覆盖，但在其它实施例中，管芯标记108可以通过包封体126暴露。在一些实施例中，包封体126由如基于联苯型或多芳族型环氧树脂的模制化合物等包封材料制成，但在其它实施例中，可以是其它类型的包封材料。可以通过包封方法执行包封，如传递模塑、薄膜辅助模塑、顶部包封(glob top)、围堰充填(damand fill)、底部充填、层压或其它类型的其它包封方法。
应注意，图1B、1C和1D以及整个附图中示出的装置可以是单独的装置(如形成于引线框架上的装置或由单独的管芯形成的装置)或可以是多个装置(如形成于引线框架阵列上的多个装置或作为晶片的一部分形成的多个装置)中的代表性装置。在一些实施例中，在引线框架阵列上形成有多个装置，并且可以在包封步骤之后执行剪切和成形(trim andform)步骤以从引线框架阵列单切或分离每个引线框架。在一些实施例中，剪切和成形步骤还可以包括对延伸超过包封体126的外周边的引线110进行成形或整形，如将其成形或整形为J形或鸥翼形引线。
图2A-2D示出了用于制造包括虚设管芯的封装半导体装置的另一个示例过程流程中的各个步骤的横截面视图。图2A示出了封装半导体装置的各个部件，所述封装半导体装置类似地包括如上所述的半导体管芯102、具有管芯标记108和多条引线110的引线框架以及虚设管芯112。还应注意，敏感区域104可以定位于一个或多个焊盘106下方，如图2A所示。
此外，图2A示出了形成于焊盘106上的多个柱形凸块228(图2A中被示出为中间短箭头)。可以使用如毛细管工具等引线接合工具如通过将无导线空气球(wire free airball)附接到焊盘106的可接合表面来形成柱形凸块228。在一些实施例中，每个柱形凸块228优选地被形成为平坦的凸块，所述凸块覆盖焊盘106的一大部分以提供顶部可接合表面。柱形凸块228还可以由一种或多种导电材料形成，所述导电材料的例子包括但不限于镍、金、铜、铝、锡或其它适合的导电金属或由一种或多种适合的导电材料构成的合金。
可以以多种方式组合图2A中示出的部件以形成图2B中示出的装置。优选地，首先将柱形凸块228附接到焊盘106以在虚设管芯112附接到半导体管芯102时(例如，当胶水114具有低粘度时)确保不含硅基胶水114的可接合表面。可以按照与上文描述的顺序(例如，先顶部箭头后底部箭头，或先底部箭头后顶部箭头)类似的顺序附接虚设管芯112和半导体管芯102。在一些实施例中，当硅基胶水114保持在焊盘106的周边外部时，可以在将虚设管芯112附接到半导体管芯102之后将柱形凸块228附接到焊盘106。
图2B示出了附接所述部件之后产生的装置。图2C示出了在执行引线接合步骤以产生多个引线接合连接120之后产生的装置。第一引线接合122形成于由柱形凸块228提供的可接合表面上，其中硅基胶水114可以在不覆盖柱形凸块228的情况下侧向地包围柱形凸块228。在所示出的实施例中，每个开口116紧密跟随相应焊盘106的周边，从而允许通过虚设管芯112中的开口116将接合形成到柱形凸块228上。图2D示出了在执行包封步骤以产生包封体126之后产生的装置，所述包封体126包封管芯标记108、半导体管芯102、虚设管芯112、柱形凸块228和引线接合连接120。在一些实施例中，还可以在包封之后执行剪切和成形步骤。
图3A示出了在虚设管芯112附接到半导体管芯102并且半导体管芯102附接到管芯标记108之后的示例装置的俯视图，并且图3B示出了所述示例装置的横截面视图(在平面B处)。虚设管芯112覆盖有源侧103的包括通过周边334给出轮廓的敏感区域104的至少一部分(例如，周边330侧向地包围周边334)。在所示出的实施例中，虚设管芯112具有外周边330，所述外周边330与下方的半导体管芯102的外周边332基本上对齐(例如，虚设管芯112的侧向尺寸对应于半导体管芯102的侧向尺寸)。图3A和3B还示出了在已经执行引线接合步骤的至少一部分之后的示例装置。
示出了穿过虚设管芯112的多个示例开口302-318。一些开口(如开口302、306、312和314)可以定位于虚设管芯112的外围或外边缘附近，所述开口对应于定位在半导体管芯102的外围或外边缘附近的焊盘106。其它开口(开口304和308)定位于虚设管芯112的中心附近，所述开口对应于半导体管芯102的中心附近的焊盘。一些开口(如304和308)以如行等规则图案定位，而其它开口(如310)以不规则图案定位。虽然一些开口(如302和304)的周边可以紧密跟随单个下方的焊盘106的周边(例如，开口的周边基本上等于下方的焊盘106的周边或由焊接掩膜限定的下方的焊盘106的可接合表面的周边)，但一些开口(如318)的周边可以大于下方的焊盘106的周边。例如，开口318大到足以侧向地包围三个焊盘。
焊盘106还可以包括为引线接合提供可接合表面的涂层，或可以包括如柱形凸块228等为引线接合提供可接合表面的柱形凸块。还在相应焊盘106与相应引线110之间示出了示例引线接合连接320、322和324，所述示例引线接合连接320、322和324各自具有分别形成于开口302、304和306内的引线接合。图3C示出了在执行包封步骤以在管芯标记108、半导体管芯102、虚设管芯112和引线接合连接120周围形成包封体126之后产生的装置的横截面视图。
图6示出了与图3B示出的装置类似的示例封装半导体装置的横截面视图。图6示出的装置包括覆盖有源侧103的小于整个半导体管芯102的一部分的虚设管芯112，其中被覆盖的部分包括敏感区域104。在所示出的实施例中，虚设管芯112的周边630延伸超过下方的敏感区域104的周边634某个侧向裕度或距离636，以确保硅基胶水114密封敏感区域104上方和周围的有源侧103从而保护敏感区域104。在所示出的实施例中，虚设管芯112侧向地包围至少一个焊盘106，其中在开口116内形成有引线接合。
图4A-4F示出了用于以晶片级制造示例装置的示例过程流程的各个步骤的横截面视图。图4A示出了包括多个虚设管芯112的示例虚设管芯晶片402。虚设管芯晶片402由具有当前顶表面111与当前底表面406之间的原始厚度或生产厚度401的空白晶片形成。在顶表面111中形成有到深度404的多个凹部408，所述深度404基本上等于所得虚设管芯112的目标厚度。凹部408可以通过激光或微钻孔或等离子切割或蚀刻形成，其中凹部408对应于半导体管芯晶片418上的焊盘106的布局(在图4A-4C中示出为虚线，图4A-4C示出了与晶片418上的下方的焊盘422对齐的凹部408)。在一些实施例中(未示出)，可以在形成凹部408之前在顶表面111上形成硅基胶水414层，其中凹部408被形成为穿过硅基胶水414和虚设管芯晶片402两者。
图4B示出了在已经执行背面研磨步骤410之后的虚设管芯晶片402，所述背面研磨步骤410通过将虚设管芯晶片402的一部分从底表面406去除到深度404来将晶片402减薄到新的厚度403，所述去除使新的底表面113显露。背面研磨还通过底表面113暴露凹部408以形成延伸穿过虚设管芯晶片402的开口116。在一些实施例中，还可以使用化学-机械抛光(CMP)或其它平坦化方法执行背面研磨。
图4C还示出了在背面研磨步骤410之后将硅基胶水414层施涂到底表面113之后的虚设管芯晶片402。在其它实施例中，在将背面研磨步骤410应用于底表面406之前，可以将硅基胶水414层施涂到顶表面111，其中所得虚设管芯晶片402被翻转以使硅基胶水414面对半导体管芯晶片418(如下文结合图9A-9C所论述的)从而得到与图4D示出的结构类似的所得结构。在一些实施例中，可以对虚设管芯晶片402(其可以通过本文所论述的实施例中的任何实施例形成)执行激光或等离子体清洁步骤以清除和去除可能阻挡开口116的任何胶水414。
图4C还示出了半导体管芯晶片418，所述半导体管芯晶片418具有多个半导体管芯102并且以有源侧朝上的朝向示出，其中半导体管芯晶片418的有源侧419包括多个敏感区域420和多个焊盘422。在晶片418的有源侧419上还示出了介电层或焊接掩膜424以限定焊盘422的可接合表面(例如，在各个实施例中，焊接掩膜424可以与焊盘422的边缘重叠以形成焊接掩膜焊盘或者可以侧向地与焊盘422的边缘分离以形成非焊接掩膜焊盘)。在一些实施例中，图4C还示出了在将虚设管芯晶片402放置和附接到半导体管芯晶片418的有源侧419之前，在焊盘422的可接合表面上形成柱形凸块416(以虚线轮廓示出)的任选步骤。
图4D示出了使用硅基胶水414附接到半导体管芯晶片418的虚设管芯晶片402，其中晶片418具有有源侧419与背侧426之间的生产厚度421。硅基胶水414沿晶片418的有源侧419提供气密密封。在一些实施例中，可以固化硅基胶水414以形成固体聚合物层。用胶水414附接到晶片418的晶片402还可以被称为组合晶片。
图4E示出了在执行背面研磨步骤428之后产生的组合晶片，所述背面研磨步骤428通过将晶片418的一部分从背侧426去除以露出新的背侧430来将晶片418减薄到新的厚度423。在一些实施例中，与背面研磨晶片418而不背面研磨晶片402相比，虚设管芯晶片402到半导体管芯晶片418的附接提供了另外的结构支撑，所述结构支撑允许背面研磨步骤428从背侧426去除较大部分并且产生整体较薄的晶片418。
图4F示出了将组合晶片分离成多个装置的单切步骤432，每个装置包括半导体管芯102和所附接的虚设管芯112。然后，可以如图1B、2B和3B中示出的那样将每个经过单切的装置附接到引线框架并且将其组装成封装半导体装置，如上所述。
图5A-5D示出了用于以晶片级制造示例装置的示例过程流程的各个步骤的横截面视图，所述步骤对于晶片级芯片规模封装体(WLCSP)而言可能是有益的。图5A示出了具有多个从顶表面111延伸到底表面113的开口116的示例虚设管芯晶片402。虚设管芯晶片402还具有处于底表面113上的硅基胶水414层。虚设管芯晶片402可以根据上文论述的方法中的任一种方法产生。
图5A还示出了处于有源侧朝上的朝向的半导体管芯晶片518，其中半导体管芯晶片518的有源侧519包括多个敏感区域520和多个焊盘522。在所示出的实施例中，在半导体管芯晶片518的有源侧519上形成有多个再分布层(RDL)或堆积层526。堆积层526可以包括多个金属化层和介电层。在所示出的实施例中，堆积层526包括介电层524和形成于焊盘522上的凸块下金属化(UBM)焊盘516。在一些实施例中，堆积层526可以包括实施焊盘522到UBM焊盘516的迹线(例如，实施再分布的布线路径)的金属化层。UBM焊盘516由一种或多种导电金属的薄膜堆叠形成，所述导电金属的例子包括但不限于镍、金、铜、铝、钛、钨、铬、钯或其它合适的导电材料或由一种或多种合适的导电金属构成的合金。UBM焊盘516提高外部连接(如焊料凸块528)的润湿性和粘附性。在一些实施例中，可以使用无电镀工艺来形成边缘与介电层524重叠的“蘑菇”形状的镍、钯和金的堆叠从而形成UBM焊盘522。UBM焊盘522还可以被称为NSMD焊盘。虚设管芯晶片402中的开口116与焊盘522对齐(以虚线轮廓示出)。还应注意，在所示出的实施例中，已经对半导体管芯晶片518执行了背面研磨步骤。
图5B示出了当使用硅基胶水414将虚设管芯晶片402附接到半导体管芯晶片518时产生的组合晶片。图5C示出了附接到UBM焊盘522的多个焊料球或焊料凸块528。应注意，开口116大到足以侧向地包围焊料凸块528。在所示出的实施例中，开口116的周边紧密跟随UBM焊盘522的周边。在其它实施例中，可能优选的是，开口116的周边比UBM焊盘522的周边大，以允许焊料凸块528润湿UBM焊盘522的侧面。
还应注意，在一些实施例中，可以将虚设管芯晶片402下压到半导体管芯晶片518上，这可以使硅基胶水414扩散到有源侧519上，如UBM焊盘522的侧面与虚设管芯晶片402之间的任何空隙中并且侧向地包围焊盘522或如焊料球528等还可以称为胶瘤的连接。胶瘤使气密密封延伸到UBM焊盘522的侧面、焊料球528的侧面或两者，其中如果不存在胶瘤，则有源侧519的这些区域可能以其它方式暴露于周围环境。当敏感区域104在焊盘下方延伸时，胶瘤可能尤其有利。图5D示出了将组合晶片分离成多个装置的单切步骤530，每个装置包括半导体管芯102和虚设管芯112以及外部连接528。
图7A示出了包括用硅基胶水114附接到半导体管芯102的虚设管芯112的示例封装半导体装置的横截面视图。虚设管芯112包括多个具有内侧壁708的开口116。在所示出的实施例中，侧壁708基本上是竖直的，但在其它实施例中可以以不同方式倾斜，如下文结合图8A-8D所论述的。已经形成多个引线接合连接704，所述引线接合连接704包括形成于暴露在每个开口116内的相应焊盘106的可接合表面上的第一引线接合702和形成于相应引线110的可接合表面上的第二引线接合706。应注意，半导体管芯102包括在焊盘106下方延伸的敏感区域104。在所示出的实施例中，硅基胶水114是柔性且顺应性的并且可以在施加压力时扩散。
图7B示出了在向虚设管芯112的顶表面施加压力710(示出为大箭头710)时的装置的横截面视图。压力710分布在虚设管芯112上并且使硅基胶水114扩散。根据在管芯102与112之间施涂的胶水114的量，胶水114可以填充焊盘106上的每个连接周围的空隙，这被称为侧向地包围并接触引线接合702的胶瘤714和可以在管芯102和112的侧边缘周围推出的胶瘤712。胶瘤714使气密密封延伸以覆盖焊盘106周围的区域中的有源侧103，如果不存在胶瘤714，所述有源侧103可能以其它方式暴露于周围环境。当敏感区域104在焊盘下方延伸时，如图7B所示，胶瘤可能尤其有利，以确保下方的敏感区域104得到密封。在一些实施例中，可以在形成胶瘤之后固化硅基胶水114。图8A-8D更详细地示出了胶瘤714(例如，图7B示出的圆圈内的装置部分)。
图8A示出了形成于虚设管芯112的开口内的焊盘上的示例引线接合。在所示出的实施例中，开口包括具有正斜率的侧壁816，所述侧壁816为外斜侧壁。在引线接合与胶水114的边缘之间还示出了空间形式的空隙。图8B示出了向虚设管芯112施加的压力，所述压力使胶水114扩散到引线接合周围的空隙中，从而形成胶瘤820。以此方式，胶水114扩散以在每个引线接合周围提供气密密封。还在管芯102和112的侧边缘处形成有胶瘤810，在敏感区域104靠近半导体管芯102的侧边缘延伸的一些实施例中，这可能是有益的。
图8C示出了形成于虚设管芯112的开口内的焊盘上的另一个示例引线接合。在所示出的实施例中，开口包括具有负斜率的侧壁818，所述侧壁818为内斜侧壁。在引线接合与胶水114的边缘之间还示出了空间形式的空隙。图8D示出了向虚设管芯112施加的压力，所述压力使胶水114扩散到引线接合周围的空隙中，从而形成胶瘤822和810。
在焊盘上包括柱形凸块并且在柱形凸块的顶部形成有引线接合的实施例中，可以以类似方式使硅基胶水114扩散到柱形凸块周围的空隙中。在焊盘上包括焊料球或焊料凸块的实施例中，也可以以类似方式使硅基胶水114扩散到焊料球或焊料凸块周围的空隙中。
图9A-9D示出了用于以晶片级制造示例装置的示例过程流程的各个步骤的横截面视图。图9A示出了包括多个虚设管芯112并具有生产厚度401的示例虚设管芯晶片402，如上文类似论述的。在顶表面111中形成有到深度404的多个凹部408，所述深度404基本上等于所得虚设管芯112的目标厚度，如上文类似论述的。图9A还示出了施涂到顶表面111的硅基胶水414层，其中还可以执行激光或等离子体清洁步骤以使凹部408没有任何胶水414，如上文类似论述的。
图9A还示出了包括多个半导体管芯102并且具有生产厚度421的示例半导体管芯晶片418。半导体管芯晶片418以有源侧朝上的朝向示出，其中半导体管芯晶片418的有源侧419包括多个敏感区域，所述敏感区域可以处于与上文示出的区域类似或不同的区域中，包括在接合焊盘422下方延伸。在接合焊盘422周围还示出了焊接掩膜424，其中凹部408对应于焊盘422。
图9B示出了以面朝下的朝向翻转并且用硅基胶水414附接到半导体管芯晶片418的虚设管芯晶片402，其中凹部408与焊盘422对齐。图9C示出了将虚设管芯晶片402的一部分向下去除到深度404的背面研磨步骤410，所述背面研磨步骤410使凹部408暴露或敞开到穿过虚设管芯晶片402的开口116中。应注意，通过结合图9C描述的背面研磨实现的虚设管芯晶片402的所得厚度903可以比通过结合图4B描述的背面研磨实现的所得厚度403薄。
图9D示出了将半导体管芯晶片418的一部分向下去除到所得厚度923的背面研磨步骤428。应注意，通过结合图9D描述的背面研磨实现的所得厚度923可以比通过结合图4E描述的背面研磨实现的所得厚度423薄。
到目前为止，应认识到，已经提供了用于半导体管芯的有源侧上的应力敏感区域的保护方案，其中这种区域通过用硅基胶水附接到并且覆盖应力敏感区域的虚设管芯进行保护。虚设管芯包括穿过虚设管芯的多个开口，所述开口与下方的半导体管芯上的接合焊盘对齐，其中当附接到半导体管芯时，每个开口侧向地包围一个或多个接合焊盘。虚设管芯在通过虚设管芯中的开口对焊盘执行的引线接合或其它连接附接(例如，焊料球或焊料凸块)之前附接到半导体管芯。硅基胶水在半导体管芯的有源侧上提供气密且防潮的密封，从而保护敏感区域不受各种热应力、机械应力和电热应力的影响。
在本公开的一个实施例中，提供了一种封装半导体装置，所述封装半导体装置包括：半导体管芯，所述半导体管芯在有源侧上具有多个焊盘；虚设管芯，所述虚设管芯具有多个从第一主表面延伸到与所述第一主表面相对的第二主表面的开口，其中所述多个开口与所述多个焊盘对齐；以及硅基胶水，所述硅基胶水将所述虚设管芯附接到所述半导体管芯的所述有源侧，其中所述半导体管芯的多个可接合表面通过所述虚设管芯的所述多个开口暴露。
上述实施例的一个方面规定，所述虚设管芯的每个开口与所述半导体管芯的相应焊盘对齐，并且所述虚设管芯的一部分定位于相邻焊盘之间。
上述实施例的另一个方面规定，所述虚设管芯的周边对应于所述半导体管芯的周边。
上述实施例的另一个方面规定，所述半导体管芯在所述有源侧上包括应力敏感区域，其中所述虚设管芯覆盖所述应力敏感区域。
上述实施例的另外方面规定，所述虚设管芯的周边延伸超出所述应力敏感区域的周边最小距离。
上述实施例的另一个另外方面规定，所述应力敏感区域在所述半导体管芯上的所述多个焊盘中的至少一个焊盘下方延伸。
上述实施例的另一个方面规定，所述虚设管芯的厚度处于10微米与100微米之间的范围内。
上述实施例的另一个方面规定，所述硅基胶水的厚度处于20微米与50微米之间的范围内。
上述实施例的另一个方面规定，所述多个开口的一部分定位于所述虚设管芯的外围部分中。
上述实施例的另一个方面规定，所述多个开口的一部分定位于所述虚设管芯的中心部分中。
上述实施例的另一个方面规定，所述多个焊盘的顶表面提供所述多个可接合表面。
上述实施例的另一个方面规定，所述封装半导体装置另外包括：多个柱形凸块，所述多个柱形凸块形成于所述多个焊盘上，其中所述多个柱形凸块的顶表面提供所述多个可接合表面。
上述实施例的另外方面规定，所述封装半导体装置另外包括：所述硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个柱形凸块，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的所述有源表面上方提供密封屏障。
上述实施例的另一个方面规定，所述封装半导体装置另外包括：凸块下金属化(UBM)层，所述UBM层形成于所述多个焊盘上，其中所述多个焊盘上的所述UBM层的顶表面提供所述多个可接合表面。
上述实施例的另外方面规定，所述封装半导体装置另外包括：多个焊料凸块，所述多个焊料凸块附接到所述多个焊盘上的所述UBM层；以及所述硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个焊料凸块，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的所述有源表面上方提供密封屏障。
上述实施例的另一个方面规定，所述封装半导体装置另外包括：多个球形接合，所述多个球形接合附接到所述虚设管芯的每个开口内的所述多个可接合表面。
上述实施例的另外方面规定，所述封装半导体装置另外包括：硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个球形接合，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的所述有源表面上方提供密封屏障。
上述实施例的另一个另外方面规定，所述封装半导体装置另外包括：引线框架，所述引线框架具有管芯标记和多个引线指，其中所述半导体管芯的背侧用管芯附接材料附接到所述管芯标记，并且所述多个球形接合是多个引线接合互连的一部分，所述多个引线接合互连还包括附接到所述多个引线指的尾部接合。
上述实施例的仍另外方面规定，所述封装半导体装置另外包括：包封体，所述包封体包封所述引线框架、所述半导体管芯、所述虚设管芯和所述多个引线接合互连。
上述实施例的另一个方面规定，所述半导体管芯是作为半导体管芯晶片的一部分的多个半导体管芯之一，所述虚设管芯是作为虚设管芯晶片的一部分的多个虚设管芯之一，并且所述硅基胶水将所述虚设管芯晶片附接到所述半导体管芯晶片，其中所述多个半导体管芯中的每一个半导体管芯的所述多个可接合表面通过所述多个虚设管芯中的每一个虚设管芯的所述多个开口暴露。
因为实施本发明的设备在很大程度上由本领域的技术人员已知的电子部件和电路构成，所以如上文所说明的，对电路细节的解释将不会超过认为必要的程度，以便于理解和认识本发明的基本概念并且以免混淆本发明的教导或将注意力转移到本发明的教导之外。
此外，说明书和权利要求中的术语“前面”、“背面”、“顶部”、“底部”“上方”、“下方”等(如果有的话)用于描述性目的并且不一定用于描述不变的相对位置。应当理解的是，如此使用的术语在适当情况下是可互换的，使得相比于在本文所说明或以其它方式描述的朝向，本文所描述的本发明实施例能够在其它朝向上操作。
应注意，如本文中所使用的术语“相邻”意指“邻近”(例如，紧邻并且无任何中间物体)，并且如本文中所使用的“侧向地”意指在“侧向方向上”(例如，与衬底的平面平行的水平方向)。
如本文中所使用的，术语“实质上”或“基本上”意味着足以以实际方式实现所阐述的目的或值，考虑由可能在晶片制造期间出现的通常和预期过程异常所产生的对于所阐述的目的或值不显著的任何微小缺陷或偏差(如果有的话)。而且，如本文中所使用的，术语空间指示不存在材料的空隙或体积。
尽管本文参考具体实施例描述了本发明，但是在不脱离如所附权利要求中所阐述的本发明的范围的情况下，可以进行各种修改和改变。例如，在图1A中可以实施另外的或更少的开口116。因此，说明书和附图应被视为具有说明性而非限制性意义，并且所有这种修改旨在包括在本发明的范围内。本文关于具体实施例描述的任何益处、优点或问题解决方案不旨在被解释为任何或所有权利要求的关键、必需或必要的特征或要素。
此外，如本文所用的术语“一个或一种(a或an)”被定义为一个或多于一个。而且，在权利要求中使用如“至少一个”和“一个或多个”等引入性短语不应被解释为暗示通过不定冠词“一个或一种(a或an)”引入的另一权利要求要素将包含这种所引入权利要求要素的任何特定权利要求限于仅包含一个这种要素的发明，甚至是在同一权利要求包括引入性短语“一个或多个”或“至少一个”以及如“一个或一种(a或an)”等不定冠词时也是如此。对于定冠词的使用也是如此。
除非另有说明，否则如“第一”和“第二”等术语用于任意区分这种术语描述的要素。因此，这些术语不一定旨在指示这种要素的时间优先次序或其它优先次序。

Claims (9)

1.一种封装半导体装置，其特征在于，所述封装半导体装置包括：
半导体管芯，所述半导体管芯在有源侧上具有多个焊盘；
虚设管芯，所述虚设管芯具有多个从第一主表面延伸到与所述第一主表面相对的第二主表面的开口，其中所述多个开口与所述多个焊盘对齐；以及
硅基胶水，所述硅基胶水将所述虚设管芯附接到所述半导体管芯的所述有源侧，其中所述半导体管芯的多个可接合表面通过所述虚设管芯的所述多个开口暴露；
凸块下金属化(UBM)层，所述UBM层形成于所述多个焊盘上，其中所述多个焊盘上的所述UBM层的顶表面提供所述多个可接合表面；
多个焊料凸块，所述多个焊料凸块附接到所述多个焊盘上的所述UBM层，以及
所述硅基胶水的胶瘤，所述胶瘤侧向地包围并且接触每个焊料凸块，其中所述胶瘤在所述半导体管芯的处于所述虚设管芯的每个开口内的有源表面上方提供密封屏障。
2.根据权利要求1所述的封装半导体装置，其特征在于，
所述虚设管芯的每个开口与所述半导体管芯的相应焊盘对齐，并且
所述虚设管芯的一部分定位于相邻焊盘之间。
3.根据权利要求1所述的封装半导体装置，其特征在于，
所述虚设管芯的周边对应于所述半导体管芯的周边。
4.根据权利要求1所述的封装半导体装置，其特征在于，
所述半导体管芯在所述有源侧上包括应力敏感区域，其中所述虚设管芯覆盖所述应力敏感区域。
5.根据权利要求4所述的封装半导体装置，其特征在于，
所述虚设管芯的周边延伸超出所述应力敏感区域的周边最小距离。
6.根据权利要求4所述的封装半导体装置，其特征在于，
所述应力敏感区域在所述半导体管芯上的所述多个焊盘中的至少一个焊盘下方延伸。
7.根据权利要求1所述的封装半导体装置，其特征在于，所述封装半导体装置进一步包括：
多个柱形凸块，所述多个柱形凸块形成于所述多个焊盘上，其中所述多个柱形凸块的顶表面提供所述多个可接合表面。
8.根据权利要求1所述的封装半导体装置，其特征在于，所述封装半导体装置进一步包括：
多个球形接合，所述多个球形接合附接到所述虚设管芯的每个开口内的所述多个可接合表面。
9.根据权利要求1所述的封装半导体装置，其特征在于，
所述半导体管芯是作为半导体管芯晶片的一部分的多个半导体管芯之一，
所述虚设管芯是作为虚设管芯晶片的一部分的多个虚设管芯之一，并且
所述硅基胶水将所述虚设管芯晶片附接到所述半导体管芯晶片，其中所述多个半导体管芯中的每一个半导体管芯的所述多个可接合表面通过所述多个虚设管芯中的每一个虚设管芯的所述多个开口暴露。
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