CN101110401A - 半导体装置及半导体封装结构 - Google Patents

半导体装置及半导体封装结构 Download PDF

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Publication number
CN101110401A
CN101110401A CNA2007100058322A CN200710005832A CN101110401A CN 101110401 A CN101110401 A CN 101110401A CN A2007100058322 A CNA2007100058322 A CN A2007100058322A CN 200710005832 A CN200710005832 A CN 200710005832A CN 101110401 A CN101110401 A CN 101110401A
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groove
semiconductor substrate
substrate
adhesion coating
semiconductor
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CN101110401B (zh
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卢思维
邹觉伦
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置，包括：半导体基板，具有上表面与下表面，该上表面包含至少一装置区；至少一沟槽，从该基板下表面穿过该基板，并连接至该装置区；导电层，填入部分该沟槽；以及粘着层，沉积于该导电层上，并填满该沟槽。根据本发明的封装技术可使用热分散层，使得装置有较佳的热分散效果。此外，封装过程中不会有任何焊盘污染的事情发生，同时其芯片尺寸也小于倒装提供的芯片尺寸。

Description

半导体装置及半导体封装结构
技术领域
本发明涉及一种半导体芯片，特别涉及一种半导体封装技术。
背景技术
图1为已知集成电路封装结构10的剖面示意图，例如Amkor揭示的塑料无引脚芯片封装结构(leadless plastic chip carrier，LPCC)。塑料无引脚芯片封装结构10包括暴露的芯片端(die paddle)12，与铜引脚架(leadframe)14连接。软焊料镀层(solder plating)16，形成于引脚架14下表面。银镀层(silverplating)18，形成于引脚架14上表面。半导体芯片，通过芯片附着材料层(dieattach material layer)20附着于银镀层18上。多条金焊线(wire bond)，形成于芯片上表面与引脚架14之间，例如接地焊线(ground bond)22、下焊线(downbond)24及其他输入/输出焊线(I/O bond)26。封胶材料层(mold compoundlayer)28，包覆上述结构。之后，将塑料无引脚芯片封装装置连接至例如印刷电路板(printed circuit board，PCB)(未图示)。
图1的塑料无引脚芯片封装结构(LPCC)10会存在着因打线接合(wirebonding)而诱导产生的高寄生电感(parasitic inductance)，特别是当与以下描述的倒装接合(flip chip bonding)技术比较时。寄生电感会冲击装置的效能，特别是射频(radio frequency，RF)装置。塑料无引脚芯片封装结构(LPCC)体积也较倒装封装结构大。此外，芯片与芯片焊盘(die pad)间的粘着性差，且打线接合焊盘(wire bonding pad)易在薄晶片去接合/移除过程中被污染。
业界对于如何提升集成电路运算速度与增加装置密度方面，一直有持续不断地研究与努力。结果开发出许多新的用来封装复杂高速集成电路的封装方法，其中之一即是关于已知“倒装”的封装技术，例如McMahon所公开的美国专利第6,075,712号。倒装封装技术的封装成本高，装置效能可获相当程度的改善。
一种先进的封装与内部接合(interconnect)方法是目前所需要的。
发明内容
为了解决上述问题，本发明提供一种半导体装置，包括：半导体基板，具有上表面与下表面，该上表面包含至少一装置区；至少一沟槽，从该基板下表面穿过该基板，并连接至该装置区；导电层，填入部分该沟槽；以及粘着层，沉积于该导电层上，并填满该沟槽。
根据本发明的半导体装置，还包括引脚架，通过该粘着层与该基板下表面连接。
根据本发明的半导体装置，还包括至少一伪沟槽，从该基板下表面至少穿过部分该基板，其中该导电层填入部分该伪沟槽，该粘着层填满该伪沟槽。
根据本发明的半导体装置，还包括：内连线结构，形成于该装置区上；至少一焊盘，形成于该内连线结构上，并与该沟槽电连接；第二半导体基板，具有上表面与下表面，该上表面包含至少一装置区，该第二半导体基板设置于该内连线结构上；至少一沟槽，从该第二半导体基板下表面穿过该第二半导体基板，并连接至该第二半导体基板的装置区；以及第二导电层，填入穿过该第二半导体基板的至少一沟槽，其中该焊盘与该第二导电层电连接。
根据本发明的半导体装置，还包括第二粘着层，设置于该焊盘与该第二导电层之间。
根据本发明的半导体装置，还包括至少一伪沟槽，至少穿过部分该第二半导体基板，该第二粘着层至少填入部分该至少之一伪沟槽。
根据本发明的半导体装置，还包括内连线结构，形成于该装置区上，其中该导电层与该内连线结构电连接。
根据本发明的半导体装置，还包括：内连线结构，形成于该装置区上；以及导线，穿过该基板，该引脚架的输入/输出端口通过该导线与一部分该内连线结构电连接。
本发明提供一种半导体装置，包括：半导体基板，具有上表面与下表面，该上表面包含至少一装置区；至少一伪沟槽，从该基板下表面至少穿过部分该基板；引脚架；以及粘着层，设置于该基板下表面与该引脚架之间。
根据本发明的半导体装置，还包括第二物质层，设置于该伪沟槽内，该粘着层设置于该第二物质层上。
根据本发明的半导体装置，其中该第二物质层填入部分该伪沟槽，该粘着层填满该伪沟槽。
根据本发明的半导体装置，其中该第二物质层包括铜，该粘着层包括软焊料或包含银的导电膏。
根据本发明的半导体装置，其中该粘着层至少填入部分该伪沟槽。
根据本发明的半导体装置，还包括：内连线结构，形成于该半导体基板的装置区上；第二半导体基板，具有上表面与下表面，该上表面包含第二装置区，该第二半导体基板设置于该内连线结构上；至少一伪沟槽，至少穿过部分该第二半导体基板；以及第二粘着层，设置于该第二半导体基板的下表面与该内连线结构之间，该第二粘着层至少填入该第二半导体基板的部分伪沟槽。
本发明提供一种半导体封装结构，包括：第一芯片，包含具有上表面与下表面的第一半导体基板，该上表面包含至少一装置区，至少一沟槽，通过该半导体基板与该装置区连接，且该沟槽包含至少一导电层，至少一伪沟槽，定义于该半导体基板中；引脚架，通过该导电层与该第一芯片连接；以及第二芯片，设置于该第一芯片上，并通过该第一芯片与该引脚架电连接。
根据本发明的封装技术可使用热分散层，使得装置有较佳的热分散效果。此外，封装过程中不会有任何焊盘污染的事情发生，同时其芯片尺寸也小于倒装提供的芯片尺寸。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
附图说明
图1为已知塑料无引脚芯片封装结构的剖面示意图。
图2为本发明第一实施例，集成电路-引脚架的剖面示意图。
图2A为本发明第二实施例，集成电路-引脚架的剖面示意图。
图3为以封装材料包覆图2结构的剖面示意图。
图4、图4A和4B为本发明第三实施例，集成电路-引脚架结构及其制造方法。
图5为以封装材料包覆图4A、图4B结构的剖面示意图。
图6为本发明包含多个装置层的集成电路-引脚架的剖面示意图。
其中，附图标记说明如下：
已知技术图1
10～塑料无引脚芯片封装结构；12～芯片端；14～引脚架；16～软焊料镀层；18～银镀层；20～芯片附着材料层；22～接地焊线；24～下焊线；26～输入/输出焊线；28～封胶材料层。
本发明图2～6
100、100A～半导体装置；101、402～半导体芯片；102、202、450～引脚架；104、204、401、604a、604b～基板；106～基板上表面；108～基板下表面；110、422、610a、610b～内连线层；112、212、424、612a、612b～金属层；114、214、414、614a、614b～沟槽；115～阻障层；116、216、416、616a、616b～伪沟槽；118、218、418、618a、618b～粘着层(焊膏)；120、120A、220、419、420、620a、620b～导电层；200～封装装置；200～封装装置；222～封装层；224～焊线；404～装置区；406～输入/输出焊盘；408～导线；410～输入/输出穿孔；412～切割线；460～封装材料；600～堆叠结构；602～共用引脚架；625a～焊盘。
具体实施方式
图2为本发明实施例，半导体装置100的部分剖面示意图。半导体装置100包括导电基板、芯片焊盘或传统金属引脚架102，与半导体芯片101连接。半导体芯片101包括具有上表面106与下表面108的半导体基板104。如已知技术所知，半导体基板104会形成集成电路的一部分。该集成电路的有源区或装置区(未图示)形成于半导体基板104的上表面106。半导体基板104优选包括硅基板，而其他半导体基板，例如硅锗(silicon-germanium)基板、三-五族化合物基板或绝缘体上硅晶(silicon on insulator，SOI)基板也可使用。内连线或金属化结构110，包括内连线结构(导线)、连接介层窗或层间介电层(inter level dielectric layer，ILD)，形成于半导体基板104上表面106的装置区上，其结构及形成方法与内连线结构110类似。内连线结构110通常包括多层内连线，例如第一层金属层至第九层金属层，形成于装置层与保护/接合结构(未图示)之间。金属化结构110可包括铝、铝铜合金、铜、钨或其他导电材料。
半导体装置100包括至少一个，优选为多个沟槽114，从基板104下表面108穿过该基板至该装置区。实施例中，沟槽114延伸至内连线结构110的第一金属层112。阻障层115，例如氮化钛，形成于沟槽114侧壁。沟槽114例如可代替焊线，作为装置区与引脚架接地端或其他接点的连接。导电层120，优选包括铜或铝铜合金，沉积并至少填入部分沟槽114。在优选实施例中，导电层120仅填入部分沟槽114。粘着层118，形成于基板104下表面108与引脚架102之间。在优选实施例中，粘着层118可为导电软焊料(conductive solder)，接合引脚架102与基板104，并通过沟槽114电连接引脚架102与装置区。导电软焊料物质包括锡铅、锡银铜合金或其他导电膏，例如银导电膏。
如图2所示，装置100包括至少一个，优选为多个伪沟槽116。伪沟槽116作为结构或机械用途，而非扮演电性或功能上的角色。伪沟槽116优选为仅部分穿过基板104。在其他实施例中，若欲连接至装置区对应的伪区域，例如场氧化层或其他隔离区，伪沟槽116可完全穿过基板104。在实施例中，导电层120也填入部分伪沟槽116。
粘着层118优选包括软焊料，且填入部分沟槽114与伪沟槽116，而与导电层120连接。基板104下表面108增加的粗糙度(由沟槽114、116增加的表面积所造成)及导电层120与粘着层118之间的接合提供了引脚架102与基板104之间很强的接合。此强有力的接合，是已知的平坦的基板下表面与引脚架之间的粘着接合无法产生的。
将导电层120填入部分沟槽可有以下几项优点，例如，铜电镀的过程相当耗时且高成本，若能减少导电层120厚度，则可缩短时间、降低成本。此外，若半导体基板104下表面108镀上厚的铜层，则必须加以薄化或移除，以使其与粘着层118达到强且高效率的接合。
在一个实施例中，沟槽114的直径大约为50微米，伪沟槽116的直径大约为30微米或更低。假设基板104的厚度大约为200微米，则伪沟槽116从基板104下表面108算起的深度大约介于30～190微米，优选为50～150微米。在实施例中，假设基板104的厚度大约为200微米，则导电层120的厚度大约为100微米。由于铜/软焊料的接合较硅/软焊料的接合强，因此，伪沟槽116可有效提升与引脚架102的接合强度。
图2A为图2的装置100的另一实施例。装置100A除了有形成于基板104下表面108的导电层120A外，其余结构均与图2的装置100相同。在实施例中，粘着层118在沟槽114、116内与导电层120接合，且与形成于基板104下表面108的导电层120A接合。导电层120与导电层120A同时形成，优选包括电镀铜。
以下揭示图2与图2A的结构的形成方法。提供晶片基板，例如硅基板104。在实施例中，基板的初厚度大约为800微米。之后，经过研磨或蚀刻而达到理想厚度，大约介于100～200微米。接着，利用微机电系统(micro-electro-mechanical system，MEMS)技术、蚀刻、激光或其他钻孔技术制作沟槽，而制作出三种介层窗或沟槽，例如伪沟槽116、接地沟槽114、其他连接用沟槽或输入/输出连接介层窗，在图4及图4B中将作更详细说明。形成介层窗/沟槽后，沉积薄的铜晶种层于基板104下表面与沟槽中，本发明不限定为铜晶种层，镍或其他适合的晶种层也可使用。之后，实施铜电镀步骤，以填入部分沟槽/介层窗。在实施例中，介层窗可被完全填满。完成铜电镀步骤后，以图2装置为例作说明(与图2A不同)。利用例如化学机械研磨法(chemical mechanical polish，CMP)移除基板104下表面108的铜电镀层。待移除铜电镀层后，若介层窗深度太深，造成涂布在引脚架102上的焊膏(solderpaste)无法填入介层窗时，可选择性地将焊膏填入介层窗。接着，将晶片基板切割出独立芯片。之后，将焊膏涂布于引脚架102及/或基板下表面。最后，将基板(独立芯片或芯片)置于引脚架102上。优选情况为，软焊料填入部分沟槽，以与导电层接触。另设置与装置输入/输出端连接的焊线。之后，以封装材料包覆该结构，并切割出独立封装芯片。
图3为图2的装置结构的剖面示意图。该装置封装于封装层222内，以形成封装装置200。封装层222包括封胶材料，其在封胶工艺中，形成覆盖于该装置上。如图3所示，封装装置200包括引脚架202，通过粘着层218连接至基板204。导电层220填入部分沟槽214与伪沟槽216。一部分的引脚架202通过沟槽214与装置层电连接，特别是形成在基板204上表面的第一金属层212。输入/输出区，例如形成在基板204上表面，特别是形成在内连线区域(未图示)上的焊盘，通过焊线224连接至引脚架202的输入/输出端口。
伪沟槽可增加引脚架与基板间的接合强度。在实施例中，例如铜的材料，优选，但非必要，可填入部分沟槽。此举将使沟槽与粘着层间的接合强度大于基板下表面与粘着层间的接合强度。当仅使用伪沟槽时，填入材料与粘着层并不须为导电物质，然而，当粘着层同时填入导电沟槽与伪沟槽时，则必须为导电物质。如上所述，部分充填仍是增加粘着层接合表面的优选方式。粘着层甚至可完全填满伪沟槽。
在一个实施例中，伪沟槽116可略去，留下连接沟槽116。此时，将导电层120填入部分沟槽114的方式，仍是提供粗糙基板表面，以与粘着层118强力接合的优先选择。
图4、图4A和图4B为本发明第三实施例，一种集成电路结构及其制造方法。输入/输出焊线以导电介层窗取代之。图4为一部分半导体晶片402的上视图。晶片402包括多个形成于其上表面的分割装置区404。基板的周边区域，典型地，包括形成于其上的隔离结构，例如场氧化层。各自的内连线结构与保护结构形成在装置区404上。典型地由铜制作成的输入/输出焊盘406形成在保护结构内或上，并与内连线结构电接触。通过钻孔形成的输入/输出穿孔410邻近于输入/输出焊盘406，并完全穿过晶片及形成于其上的任何隔离及/或保护结构。在实施例中，穿孔410的直径大约介于10～100微米。由一层或多层导电层组成的导电插栓填入穿孔410，并与导线408电接触，导线408可为铜或铝导线。沟槽与伪沟槽虽未见于上视图中，仍以上述方式制作形成。输入/输出穿孔410通过导线408与输入/输出焊盘406电连接。切割线412表示晶片切割处。经切割下来的独立芯片即连接至引脚架，并进行后续封装。
图4A为图4晶片402沿切割线412切割下来的独立芯片的上视图。图4B为图4A芯片沿B-B剖面线切割的剖面示意图，同时连接至引脚架450。请参阅图4B，图4A的芯片通过粘着层(焊膏)418与引脚架450连接。基板401包括沟槽414与伪沟槽416。导电层420填入部分沟槽414与伪沟槽416。图中还包括内连线层422、第一金属层424(也显示于图4A中)、输入/输出焊盘406以及导线408。优选情况为，导电层419与粘着层418填入部分输入/输出穿孔410，以形成导电插栓，连接引脚架450的输入/输出端口。在一个实施例中，导电层419与导电层420同时形成，两者包括铜。最后，图5为图4A、图4B装置包覆封装材料460后的剖面示意图，此为最终的封装芯片结构。
由此可知，输入/输出穿孔410已代替图1、图3所示的输入/输出焊线。在此实施例中，不但通过增加晶片背后粗糙度增加了芯片与芯片焊盘间的粘着性，也保有图2、图2A结构的其他优点，且可提升装置电表现，减少由于移除薄晶片造成焊盘污染而产生的任何有关焊线的问题，并允许较小尺寸的芯片进行封装。
以下揭示图5的装置的形成方法。在基板401与内连线层中形成装置区404后，续形成保护结构、输入/输出焊盘406及导线408。之后，将晶片顶部置于例如玻璃基板的晶片载具，以研磨至理想厚度。接着，利用已知微机电技术制作沟槽414与伪沟槽416以及输入/输出穿孔410，并随后溅镀上铜或镍晶种层。接着，电镀导电层419、420至基板下表面，优选并填入部分沟槽414、416及穿孔410。接着，移动晶片载具并切割晶片。之后，优选是将焊膏418涂布在引脚架450上并选择性地填入穿孔。之后，将切割下来的独立芯片通过焊膏418置于引脚架450上并且烘干或焊接。最后，封装芯片与引脚架，以制作完成封装芯片。
图6揭示上述沟槽与伪沟槽亦可应用在三维的集成电路结构。三维集成电路由多层装置层经堆叠、内部电连接所形成。三维集成电路在导线长度、面积、时间及耗能上有其竞争优势。图6揭示堆叠芯片结构600。此处并不限定两芯片堆叠，多层芯片堆叠也为本发明设计范畴。堆叠结构600包括共用引脚架602与利用粘着层连接至引脚架602的第一芯片。第一芯片包括具有沟槽614a与伪沟槽616a的基板604a。导电层620a填入部分沟槽614a与伪沟槽616a。内连线层610a形成于基板604a上表面。引脚架602通过沟槽614a及内部充填的导电物质与第一芯片装置层的第一金属层612a电连接。
与第一芯片类似，第二芯片包括基板604b。基板604b包括连接至第一金属层612b的沟槽614b、伪沟槽616b、导电层620b、内连线层610b以及粘着层618b。粘着层618b与粘着层618a不同，其优选情况为，没有覆盖第二芯片的全部下表面。粘着层618b必须限定在沟槽的区域，且利用已知印刷技术使其与基板604b的下表面形成共平面。形成在沟槽614b、616b区域的粘着层618b连接至第一芯片的焊盘625a，以使伪沟槽616b与第一芯片之间形成结构性接合，且使沟槽614b与第一芯片及引脚架602之间形成结构与电接合。焊盘625a优选包括铜或铝，且形成于内连线层610a上。依此方式，第一芯片与第二芯片可电连接至引脚架602，例如形成接地。与伪沟槽616b连接的焊盘625a可称为伪焊盘，也就是与内连线层610a电隔离的焊盘。
形成于内连线层610b上的焊盘625b可使后续堆叠的芯片与堆叠结构600或连接第二芯片与引脚架602的焊线(未图示)之间形成电性及结构上的连接。最后，封装堆叠结构600，以形成封装结构。
如上所述，新的内连线结构通过增加晶片背后的粗糙度增加了芯片与芯片焊盘间的粘着性，同时使射频装置有较小的封装体积。已知无法将热分散层(heat spreader layer)使用在焊线封装，然而，本发明封装技术可使用热分散层，使得装置有较佳的热分散效果。此外，封装过程中不会有任何焊盘污染的事情发生，同时其芯片尺寸也小于倒装提供的芯片尺寸。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域技术人员，在不脱离本发明的精神和范围内，可以做出变化与修改，因此本发明的保护范围当视后附的权利要求所界定的为准。

Claims (15)

1.一种半导体装置，包括：
半导体基板，具有上表面与下表面，该上表面包含至少一装置区；
至少一沟槽，从该基板下表面穿过该基板，并连接至该装置区；
导电层，填入部分该沟槽；以及
粘着层，沉积于该导电层上，并填满该沟槽。
2.如权利要求1所述的半导体装置，还包括引脚架，通过该粘着层与该基板下表面连接。
3.如权利要求1所述的半导体装置，还包括至少一伪沟槽，从该基板下表面至少穿过部分该基板，其中该导电层填入部分该伪沟槽，该粘着层填满该伪沟槽。
4.如权利要求2所述的半导体装置，还包括：
内连线结构，形成于该装置区上；
至少一焊盘，形成于该内连线结构上，并与该沟槽电连接；
第二半导体基板，具有上表面与下表面，该上表面包含至少一装置区，该第二半导体基板设置于该内连线结构上；
至少一沟槽，从该第二半导体基板下表面穿过该第二半导体基板，并连接至该第二半导体基板的装置区；以及
第二导电层，填入穿过该第二半导体基板的至少一沟槽，其中该焊盘与该第二导电层电连接。
5.如权利要求4所述的半导体装置，还包括第二粘着层，设置于该焊盘与该第二导电层之间。
6.如权利要求5所述的半导体装置，还包括至少一伪沟槽，至少穿过部分该第二半导体基板，该第二粘着层至少填入部分该至少之一伪沟槽。
7.如权利要求1所述的半导体装置，还包括内连线结构，形成于该装置区上，其中该导电层与该内连线结构电连接。
8.如权利要求2所述的半导体装置，还包括：
内连线结构，形成于该装置区上；以及
导线，穿过该基板，该引脚架的输入/输出端口通过该导线与一部分该内连线结构电连接。
9.一种半导体装置，包括：
半导体基板，具有上表面与下表面，该上表面包含至少一装置区；
至少一伪沟槽，从该基板下表面至少穿过部分该基板；
引脚架；以及
粘着层，设置于该基板下表面与该引脚架之间。
10.如权利要求9所述的半导体装置，还包括第二物质层，设置于该伪沟槽内，该粘着层设置于该第二物质层上。
11.如权利要求10所述的半导体装置，其中该第二物质层填入部分该伪沟槽，该粘着层填满该伪沟槽。
12.如权利要求11所述的半导体装置，其中该第二物质层包括铜，该粘着层包括软焊料或包含银的导电膏。
13.如权利要求9所述的半导体装置，其中该粘着层至少填入部分该伪沟槽。
14.如权利要求9所述的半导体装置，还包括：
内连线结构，形成于该半导体基板的装置区上；
第二半导体基板，具有上表面与下表面，该上表面包含第二装置区，该第二半导体基板设置于该内连线结构上；
至少一伪沟槽，至少穿过部分该第二半导体基板；以及
第二粘着层，设置于该第二半导体基板的下表面与该内连线结构之间，该第二粘着层至少填入该第二半导体基板的部分伪沟槽。
15.一种半导体封装结构，包括：
第一芯片，包含具有上表面与下表面的第一半导体基板，该上表面包含至少一装置区，至少一沟槽，通过该半导体基板与该装置区连接，且该沟槽包含至少一导电层，至少一伪沟槽，定义于该半导体基板中；
引脚架，通过该导电层与该第一芯片连接；以及
第二芯片，设置于该第一芯片上，并通过该第一芯片与该引脚架电连接。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856279A (zh) * 2011-06-28 2013-01-02 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN103229290A (zh) * 2010-11-23 2013-07-31 罗伯特·博世有限公司 薄芯片在载体衬底上的低共熔压焊
CN110573840A (zh) * 2017-04-28 2019-12-13 盛思锐股份公司 传感器封装

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7557036B2 (en) * 2006-03-30 2009-07-07 Intel Corporation Method, system, and apparatus for filling vias
US20080217759A1 (en) * 2007-03-06 2008-09-11 Taiwan Solutions Systems Corp. Chip package substrate and structure thereof
SE534510C2 (sv) 2008-11-19 2011-09-13 Silex Microsystems Ab Funktionell inkapsling
KR101870155B1 (ko) 2012-02-02 2018-06-25 삼성전자주식회사 비아 연결 구조체, 그것을 갖는 반도체 소자 및 그 제조 방법들
US8963316B2 (en) 2012-02-15 2015-02-24 Advanced Semiconductor Engineering, Inc. Semiconductor device and method for manufacturing the same
US8722467B2 (en) * 2012-06-30 2014-05-13 Alpha & Omega Semiconductor, Inc. Method of using bonding ball array as height keeper and paste holder in semiconductor device package
US9136236B2 (en) * 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
KR101526278B1 (ko) * 2012-12-21 2015-06-05 제일모직주식회사 경화 필름과 도전 필름을 포함하는 분리형 이방 도전성 필름
JP2014203861A (ja) 2013-04-02 2014-10-27 三菱電機株式会社 半導体装置および半導体モジュール
US9583462B2 (en) * 2015-01-22 2017-02-28 Qualcomm Incorporated Damascene re-distribution layer (RDL) in fan out split die application
US9917043B2 (en) 2016-01-12 2018-03-13 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10600759B2 (en) 2016-01-12 2020-03-24 Advanced Semiconductor Engineering, Inc. Power and ground design for through-silicon via structure

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3343256A (en) * 1964-12-28 1967-09-26 Ibm Methods of making thru-connections in semiconductor wafers
US3372070A (en) * 1965-07-30 1968-03-05 Bell Telephone Labor Inc Fabrication of semiconductor integrated devices with a pn junction running through the wafer
DE1933731C3 (de) * 1968-07-05 1982-03-25 Honeywell Information Systems Italia S.p.A., Caluso, Torino Verfahren zum Herstellen einer integrierten Halbleiterschaltung
US3648131A (en) * 1969-11-07 1972-03-07 Ibm Hourglass-shaped conductive connection through semiconductor structures
US4596069A (en) * 1984-07-13 1986-06-24 Texas Instruments Incorporated Three dimensional processing for monolithic IMPATTs
EP0262485A1 (de) * 1986-10-01 1988-04-06 BBC Brown Boveri AG Halbleiterbauelement mit einer Ätzgrube
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5445974A (en) * 1993-03-31 1995-08-29 Siemens Components, Inc. Method of fabricating a high-voltage, vertical-trench semiconductor device
US5682062A (en) * 1995-06-05 1997-10-28 Harris Corporation System for interconnecting stacked integrated circuits
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5814889A (en) * 1995-06-05 1998-09-29 Harris Corporation Intergrated circuit with coaxial isolation and method
US5618752A (en) * 1995-06-05 1997-04-08 Harris Corporation Method of fabrication of surface mountable integrated circuits
US5973396A (en) * 1996-02-16 1999-10-26 Micron Technology, Inc. Surface mount IC using silicon vias in an area array format or same size as die array
WO1999063596A1 (de) * 1998-06-04 1999-12-09 GFD-Gesellschaft für Diamantprodukte mbH Diamantbauelement mit rückseitenkontaktierung und verfahren zu seiner herstellung
JP2000183003A (ja) * 1998-10-07 2000-06-30 Toshiba Corp 銅系金属用研磨組成物および半導体装置の製造方法
US6075712A (en) * 1999-01-08 2000-06-13 Intel Corporation Flip-chip having electrical contact pads on the backside of the chip
US7179740B1 (en) * 1999-05-03 2007-02-20 United Microelectronics Corporation Integrated circuit with improved interconnect structure and process for making same
KR100345166B1 (ko) * 2000-08-05 2002-07-24 주식회사 칩팩코리아 웨이퍼 레벨 스택 패키지 및 그의 제조 방법
US6459150B1 (en) * 2000-08-17 2002-10-01 Industrial Technology Research Institute Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
KR100364635B1 (ko) * 2001-02-09 2002-12-16 삼성전자 주식회사 칩-레벨에 형성된 칩 선택용 패드를 포함하는 칩-레벨3차원 멀티-칩 패키지 및 그 제조 방법
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
EP1514299A1 (en) * 2002-06-07 2005-03-16 Oticon A/S Feed-through process and amplifier with feed-through
KR100497111B1 (ko) * 2003-03-25 2005-06-28 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지, 그를 적층한 적층 패키지및 그 제조 방법
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7088005B2 (en) * 2003-12-31 2006-08-08 Intel Corporation Wafer stacking with anisotropic conductive adhesive
JP4093186B2 (ja) * 2004-01-27 2008-06-04 カシオ計算機株式会社 半導体装置の製造方法
KR20060081900A (ko) * 2005-01-10 2006-07-14 엘지전자 주식회사 엠시엠 비지에이 패키지의 설계 방법 및 엠시엠 비지에이패키지
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7772116B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103229290A (zh) * 2010-11-23 2013-07-31 罗伯特·博世有限公司 薄芯片在载体衬底上的低共熔压焊
CN103229290B (zh) * 2010-11-23 2016-10-05 罗伯特·博世有限公司 薄芯片在载体衬底上的低共熔压焊
CN102856279A (zh) * 2011-06-28 2013-01-02 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN102856279B (zh) * 2011-06-28 2015-11-25 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN110573840A (zh) * 2017-04-28 2019-12-13 盛思锐股份公司 传感器封装
CN110573840B (zh) * 2017-04-28 2021-08-20 盛思锐股份公司 传感器封装

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US7446424B2 (en) 2008-11-04
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CN101110401B (zh) 2012-03-07
KR20080008208A (ko) 2008-01-23

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