CN103229290A - 薄芯片在载体衬底上的低共熔压焊 - Google Patents

薄芯片在载体衬底上的低共熔压焊 Download PDF

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CN103229290A
CN103229290A CN2010800702589A CN201080070258A CN103229290A CN 103229290 A CN103229290 A CN 103229290A CN 2010800702589 A CN2010800702589 A CN 2010800702589A CN 201080070258 A CN201080070258 A CN 201080070258A CN 103229290 A CN103229290 A CN 103229290A
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semiconductor chip
contact site
aforementioned
packing material
run
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CN103229290B (zh
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A·普吕姆
K-H·克拉夫特
T·迈尔
A·霍伊查斯特
C·舍林
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Robert Bosch GmbH
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    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
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Abstract

本发明涉及一种用于制造半导体元器件(166)的方法。该方法包括下列步骤：a)在初始衬底(112)上制造半导体芯片(110)，其中所述半导体芯片在至少一个支撑点(116)上与所述初始衬底(112)连接，其中所述半导体芯片(110)具有背离所述初始衬底(112)的正面(130)和朝向所述初始衬底(112)的背面(132)，b)在至少一个贯穿接触步骤中，将至少一个贯穿接触部填充材料(142)施加到所述半导体芯片(110)上，其中所述背面(132)的至少一个部分区域(140)被涂以所述贯穿接触部填充材料(142)，c)将所述半导体芯片(110)与所述初始衬底(112)分离，以及d)将所述半导体芯片(110)施加到至少一个载体衬底(150)上，其中所述半导体芯片(110)的背面(132)的被涂以所述贯穿接触部填充材料(142)的部分区域(140)与所述载体衬底(150)上的至少一个焊盘(152)连接。

Description

薄芯片在载体衬底上的低共熔压焊
技术领域
本发明涉及一种薄芯片在载体衬底上的低共熔压焊。
背景技术
由现有技术已知用于制造薄芯片的所谓的芯片膜工序。这种芯片膜工序例如在M.Zimmermann等人于2006年的Tech.Dig.IEDM的1010-1012页上发表的文章“A Seamless Ultra-Thin Chip Fabricationand Assembly Technology”中进行了描述。芯片膜技术指通过特殊的蚀刻法在初始衬底，特别是由常规的硅制成的载体晶片上产生凹陷部，该凹陷部也被称为“空穴”。这些空穴通过制造多孔硅以及随后除去多孔硅(APSM-工序)制成。随后通过外延法在这些空穴上施加对于电路适合的硅。这些施加的涂层随后形成超薄的微芯片。随后通过常规方法在这些面上加工所希望的电路结构。接着，可以通过也被称为“拾取、破裂、放置(Pick，Crack and place)”的技术通过真空吸管吸取(拾取)芯片，使其与初始衬底裂开(破裂)并随后放置(放置)到任一其他载体衬底上。
同样地，由现有技术还已知制造在晶片或芯片上或者穿过晶片或芯片的电触点的方法。在此，例如可以在晶片中产生具有几乎垂直的壁部的细长孔，这些细长孔被绝缘并且随后整个或部分地被导电材料(例如金属或硅)填充。此外，由微系统技术已知在晶片平面上的低共熔压焊法，其以所谓的“芯片到晶片工艺”而为人所知。在应用领域中，已知用于在芯片复合结构中集成传感器芯片和评估IC的方案。
发明内容
以已知的现有技术为出发点，本发明提供了一种用于制造半导体元器件的方法，该方法可以改善在半导体芯片、特别是薄的半导体芯片与载体衬底之间的连接。所提出的方法特别适用于在半导体元器件的基础上制造传感器元件，如由下面的说明将详细进行阐述的那样。
所提出的用于制造半导体元件的方法包括下面所描述的步骤，其优选地以所示出的顺序执行。除了所提到的方法步骤外，还可以设计其他的方法步骤，并且可以在时间上并行地执行一个或多个方法步骤和/或重复执行一个或多个方法步骤。
在第一方法步骤中，在初始衬底上制造半导体芯片。在此，所述半导体芯片在至少一个支撑点上与所述初始衬底连接，并且所述半导体芯片具有背离所述初始衬底的正面和朝向所述初始衬底的背面。该半导体芯片特别地可以被设计为薄芯片，即，被设计为厚度小于100μm，优选小于50μm，并且特别优选地小于20μm的芯片。半导体芯片可以特别地在硅的基础上产生。特别地可以应用上面所描述的芯片膜法制造半导体芯片，从而可以使用具有一个或多个空穴的硅作为初始衬底，所述一个或多个空穴完全或部分地用多孔的半导体材料、特别是多孔硅填充。随后，可以例如以外延的方式在多孔的半导体材料上构造半导体芯片，并且优选地以APSM-工艺去除多孔材料。半导体芯片可以如以上同样实施地那样通过通常的半导体工艺具有结构，并且获得至少一种功能性。
在在下面也被称为贯穿接触步骤的第二方法步骤中，将至少一个贯穿接触部填充材料施加到所述半导体芯片上。其中所述背面的至少一个部分区域被涂以所述贯穿接触部填充材料。同时可以如下面还将详细说明地，在贯穿接触步骤期间至少一个贯穿接触部(即在半导体芯片中的孔，例如垂直于半导体芯片表面的细长孔)的至少一个壁部和半导体芯片的至少一个侧壁被涂以贯穿接触部填充材料。贯穿接触部填充材料在此应理解为一种具有至少半导体特性的材料，即半导体材料或导体材料。该贯穿接触部填充材料因此可以用作电流的载体。特别地，如下面还将详细阐述地，贯穿接触部填充材料可以指可由流体相和/或气相沉积的材料。
在第三方法步骤中，将所述半导体芯片与初始衬底分离。在该分离中，例如通过机械的和/或化学的方法将支撑点断开。例如，可以在这种分离中，使用上面所描述的“拾取、破裂、放置”法，从而能够例如通过真空吸管对半导体芯片进行吸取、旋转或倾斜，并且由此可以使半导体芯片从初始衬底断开并且随后被提供用于其他应用。然而，原则上也可以使用其他技术。
在第四方法步骤中，将所述半导体芯片施加到至少一个载体衬底上，其中半导体芯片的背面的被涂以所述贯穿接触部填充材料的部分区域与所述载体衬底上的至少一个焊盘连接。在此，焊盘应理解为在载体衬底表面上的传导性结构，其可以与所述至少一个部分区域实现传导性连接。该至少一个焊盘例如可以具有矩形的形状、框形形状、圆形形状或其他完全或者部分地与半导体芯片的背面的被涂以贯穿接触部填充材料的部分区域符合的任一形状，或者所述焊盘原则上也可以具有其他结构。
所提出的制造方法的该基本形式可以以不同的方式进行有利地扩展。因此，可以如同上面所示地，规定附加的方法步骤。此外，特别优选的是，在第四方法步骤中使用低共熔压焊法以将半导体芯片背面的被涂以贯穿接触部填充材料的部分区域与所述至少一个焊盘连接。在此，低共熔压焊法应理解为一种以通过低共熔熔合物形成连接为基础的特殊的连接方法。在此，低共熔熔合物应理解为导体材料或半导体材料(例如硅和金或锗和铝)的混合物，这其中混合物的各组分相互间的比例使得熔合物的熔化温度低于各个元素的熔化温度。
贯穿接触部填充材料特别地可以包括至少一种半导体材料。在这种情况下，特别适合的是锗或者硅。相应地，焊盘可以包括能够与贯穿接触部填充材料优选地形成低共熔熔合物的材料。例如，焊盘可以包括铝，其特别地可以与作为贯穿接触部填充材料的锗形成低共熔熔合物。替代地或附加地，焊盘也可以包括例如金，而贯穿接触部填充材料包括硅。另一可行的材料组合是金-锗。总体上有利的是，焊盘包括金属材料，而贯穿接触部填充材料包括半导体材料，其中金属材料和半导体材料可以形成低共熔熔合物。
在贯穿接触步骤中，如上面所述的，除了对半导体芯片的背面的至少一个部分区域涂层以外，还可以对半导体芯片的其他区域进行涂层。例如，可以设置贯穿接触部，即在半导体芯片中的开口，其例如将正面与背面连接或者至少将半导体芯片的一个涂层面与至少一个其他涂层面连接。这些开口例如可以具有圆形或多边形的横截面，其中在贯穿接触步骤中可以对贯穿接触部的至少一个壁部进行涂层。替代地或附加地，可以在贯穿接触步骤中，给半导体芯片的至少一个侧壁涂以贯穿接触部填充材料。在此，侧壁理解为半导体芯片的与正面和背面不同的面，优选的是基本上垂直于正面和背面的面，其中正面和背面优选地相互平行地定向。例如，这种侧壁可以在前面所描述的芯片膜法中在所谓的刻槽(Trenching)步骤中制成，在该步骤中限定出半导体芯片的面和外棱边。在这个刻槽法中，可以使用机械的或化学的分离法，例如DRIE(Deep Reactive IonEtching，深反应离子蚀刻)。
在本发明的另一优选的设计方案中，在贯穿接触步骤中在背面上产生至少一个框架。特别地，在此可以指封闭框架。这个框架例如可以被施加到半导体芯片的背面的侧棱边上并且例如与这些侧棱边相符合。该框架可以优选地具有小于100μm，优选地小于50μm，特别是10μm或更小的或甚至仅为1μm的宽度。在将半导体芯片施加到载体衬底上后，在框架内部产生一个中间腔，特别是气密封闭的中间腔。该中间腔由半导体芯片的背面、载体衬底的朝向半导体芯片的正面和框架限定。附加地，可以设置另外的结构用于限定。封闭的中间腔可以例如如下面还将详细阐述地，用作压力传感器的参考真空(Referenzvakuum)。在此，气密封闭的中间腔应被理解为一种中间腔，在该中间腔中优选地在多个月或甚至多年的时间标度上，特别的是相较于半导体元器件的使用时间，大幅地减缓中间腔的气体与半导体元器件的环境的交换。
在贯穿接触步骤中，特别地可以使用各向同性的沉积法，优选地是共形沉积法，即沉积物通过接触部填充材料至少部分地符合半导体芯片或其他元器件的外轮廓的一种沉积法。特别地，在此提供液相沉积法和/或气相沉积法，例如CVD法(Chemical VaporDeposition，化学气相沉积)，例如LPCVD法(low pressure CVD，低压CVD)。
如上面已示出地，可以特别地这样设计半导体芯片，使得其包括半导体元器件的一个或多个功能元件。特别地，半导体芯片可以包括下列元件中的至少一种：集成电路、传感器结构部、微机械结构部。这些功能元件可以全部或部分地设置在半导体芯片上并且可以借助于如半导体技术领域的专业人员已知的常规方法制造。
本发明的其他可能的改进方案涉及贯穿接触步骤的执行方式。也就是说，例如可以在贯穿接触步骤之前，特别地将至少一种绝缘材料施加到半导体芯片上。这种绝缘材料例如可以是有机材料或者也可以是无机材料。特别优选的是，使用介电层，例如氧化硅层。作为使用这类应至少部分地防止在贯穿接触部填充材料与半导体芯片的特定的功能元件之间的电接触的绝缘材料的替代或附加，还可以应用其他工序。例如，可以使用CMOS工序，其中使用具有至少局部绝缘掺杂的半导体芯片，例如以避免短接。又替代地或附加地，可以在贯穿接触步骤之后，至少部分将贯穿接触部填充材料又从半导体芯片去除。为了该去除，例如可以使用常规的湿化学或干化学性质的半导体法，例如湿化学蚀刻法或干蚀刻法。与此相关地，可以参考已知的蚀刻法。原则上，还可以想到所谓的“提起工序”(Lift-off-Prozess)，即以下工序：将半导体芯片的不应涂上贯穿接触部填充材料的区域先涂上一层，该层在贯穿接触步骤后又从半导体芯片上被除去。
本发明的其他的改进方案涉及半导体芯片的设计方案。如前面已述地，半导体芯片可以特别地根据芯片膜法制造。相应地，特别有利的是，半导体芯片包括单晶的半导体膜、特别是单晶硅膜。然而，原则上其他的半导体材料也是可行的。支撑点除了优选为硅的单晶材料以外，还可包括多孔材料，优选为多孔硅。
除了在上述设计方案中的一个或多个设计方案中所提出的方法外，还提出一种半导体元器件，所述半导体元器件能够按照根据所描述的变型实施方式中的一个或多个变型实施方式的方法制造。特别地，所述半导体元器件可以从下列半导体元器件中选出：压力传感器；惯性传感器；加速度传感器；开关。一般地，可以将半导体元器件整个或部分地设计为特别是传感器元件和/或包括这类传感器元件。
借助于所提出的发明，还能够制造半导体元器件，其特别地可以包括薄芯片并且可以具有贯穿接触部。这些贯穿接触部在此除了承担电的贯穿引导外，还同时承担以下任务，即实现在半导体芯片、特别是薄芯片与原则上任一载体衬底、例如电路板、引线框架或复杂的以机械和/或电的方式设计的载体衬底，例如像ASIC(Application Specific Integrated Circuit，专用集成电路)这样的载体芯片之间的气密且节约空间的连接。在此，贯穿接触部填充材料可以同时用作用于半导体芯片到载体衬底上的低共熔压焊的材料成分。具有IC的薄芯片和/或具有贯穿接触部的传感器结构件可以例如借助于上面所描述的芯片膜法在具有支撑点的单晶硅膜上制造。随后，可以在与贯穿接触部邻接的区域中将贯穿接触部填充材料、例如锗以相同的沉积工序也沉积到膜底面上，即半导体芯片的背面上。薄芯片可以放置在载体衬底的金属焊盘、例如铝上，这样可以制造在贯穿接触部填充材料和焊盘之间的低共熔压焊部。
借助于所提出的方法，特别是在作为载体衬底的载体IC芯片上可以特别地实现不同类型的微机械传感器。在此，一个半导体芯片(然而也可以设置多个半导体芯片)特别地用作薄芯片、用于压力传感器的膜、用于惯性传感器的指状结构部、开关、用于z-加速度传感器的第二反电极或以其他方式用作传感器元件的组成部分。
在所提出的方法和所提出的半导体元器件中特别有利的是，以很小的连接宽度已可以稳定且气密密封地设计可选的低共熔压焊部。可以实现小的压焊框架宽度或者说贯穿接触部，特别是小于10μm的宽度。通过所建议的方法，还可以无应力地连接半导体芯片，特别是薄芯片，由此可以实现半导体元器件的很低的废品率和长的使用寿命。此外，可以在空间使用尽可能最小的情况下实现传感器元件和IC的集成。在载体衬底、例如载体芯片上还可以相互重叠和/或相互并列地集成多个半导体芯片、例如多个薄芯片，并由此优选地集成多种功能。
在所建议的方法中，可以使用常规的工艺技术并依据本发明进行调整。所述方法总体上可以非常简单且基本上地通过常规的加工技术实现。如此，例如所述至少一个贯穿接触部可以与分开的凹槽(Vereinzelungs-Trench)同时产生，其目前在前面所描述的芯片膜法中已经产生。此外，还可以通过例如现今已使用的标准技术在半导体芯片和/或载体衬底上制造功能元件，从而所建议的方法整体上可以非常低成本地实现。
附图说明
本发明的实施例在附图中示出并在下面的描述中进行详细阐述。
附图中：
图1A至图1H示出了用于制造半导体元器件的方法的实施例的方法步骤；
图2示出了可依据本发明制造的压力传感器的实施例；
图3示出了可依据本发明制造的惯性传感器的实施例；
图4示出了可依据本发明制造的z-加速度传感器的实施例；以及
图5示出了具有CMOS-工序的方法变型。
具体实施方式
在图1A至图1H中示出了依据本发明的用于制造半导体元器件的制造方法的实施例的示意性方法步骤。
在图1A中，示例性地示出了第一方法步骤，在该步骤中生产在初始衬底112上的半导体芯片110。该生产在此示例性地在芯片膜工序中进行。半导体芯片110在此被构造为形成在初始衬底112和半导体芯片110之间的空穴114上方的外延膜(epitaktische Membran)，例如为硅膜。半导体芯片110，例如硅膜在此通过支撑点116保持，这些支撑点例如可以被设计为晶体硅和/或多孔硅的形式。通过常规工艺可以将一个或者多个功能元件118(例如功能层120)集成在半导体芯片110内部或者沉积在半导体芯片110的表面上。通过这种方式半导体芯片110可以例如包括涂层堆。
此外，半导体芯片110、例如半导体芯片110的一个涂层堆优选地包括至少一个优选地被绝缘层124(例如氧化物)包围的电触点122、例如焊盘。
借助于所谓的刻槽法接下来在所示出的实施例中(如图1B所示)制造出沟槽126，例如锯齿沟槽。此外，可选地制造出一个或者多个贯穿接触部128，其在该实施例中被设计为在半导体芯片110中的简单开口。这些贯穿接触部128例如可以将半导体110的背向初始衬底112的正面130与半导体芯片110的朝向初始衬底112的背面132相连接。
借助于优选共形的沉积法最终将介电层134施加到半导体芯片110上。例如，该介电层又可以包括氧化物层，优选为氧化硅。作为沉积法，可以考虑例如已知的沉积法，特别是TEOS-臭氧法、SACVD-涂层、低温氧化法或者类似方法。在这种方法中，还可以对在沟槽126区域中的半导体芯片110的侧壁136和/或贯穿接触部128的侧壁138涂以介电层134。此外，在该实施例中，对在沟槽126的区域中和/或贯穿接触部128的区域中位于背面132上的部分区域140涂以介电层134。
接下来，通过强烈的各向异性的、定向的氧化物蚀刻使正面130、即半导体芯片110的芯片表面上的介电层134变薄并且开出电触点122、例如焊盘，而不会使侧壁136、138区域中的侧壁保护部明显变薄。在图1C中示出了这种方法步骤的结果。替代地，还可以通过其他技术实现电触点122的氧化物蚀刻和开出，例如通过喷雾上漆技术。不同的其他技术对于半导体制造领域的技术人员来说是已知的。
在图1D中示出的方法步骤中，接下来，优选地以共形沉积法施加贯穿接触部填充材料142。例如，该贯穿接触部填充材料142可以包括锗。例如可以使用LPCVD法，即低压-CVD法。由于共形沉积法，贯穿接触部填充材料142的涂层符合半导体芯片110的轮廓，从而除了正面130外，还对半导体芯片110的侧壁136以及可选地贯穿接触部128的侧壁138进行涂层，以及又对在半导体芯片110的背面132上的部分区域140进行涂层。
在图1E中示出了在图1D中以大写字母A表示并用虚线框出的半导体芯片110的部分区域，其包括一个贯穿接触部128。在该图中，可以看出贯穿接触部填充材料142的共形沉积的优点。在其内部半导体芯片110的背面132也被涂以贯穿接触部填充材料142的部分区域140优选地不大于在其中背面132被涂以介电层134的部分区域(例如参见图1B上方)。
在图1E中示出了典型的尺寸大小。由此，贯穿接触部128的开口典型地具有小于2μm的直径D1。半导体芯片110的膜典型地具有大约10μm至20μm的厚度d2。这些开口可以通过大约1μm厚的贯穿接触部填充材料142的涂层(例如锗层)封闭。在优选地具有大于3μm的深度的空穴114中，在半导体芯片110的背面132以及在空穴底部上分别沉积例如少于1μm的贯穿接触部填充材料142。随后，在半导体芯片110和空穴底部之间保留一个间隙144，由此进一步保留了半导体芯片110增厚的可能。优选地，以比空穴114的高度d3的一半更小的厚度d4施加贯穿接触部填充材料142。
在图1F中，示出了一种可选的方法步骤，在该步骤中特别是从半导体芯片110的正面130，至少部分地去除贯穿接触部填充材料142。与在部分区域140中相同，在此，在侧壁136和138上可以保留利用贯穿接触部填充材料142实现的涂层。同时，在此可实现贯穿接触部填充材料142的结构化，例如用于在正面130上产生可选的导体电路146和/或其他结构，所述其他结构也可以整个或部分地是功能元件118的组成部分。在图1F所示的例子中，由此例如可以通过所示的导体电路146与贯穿接触部128从背面132与电触点122电接触。为了使贯穿接触部填充材料142结构化，原则上可以使用由半导体制造已知的技术。由此，例如可以使用喷雾上漆、标准光刻或标准蚀刻法。这种类型的方法对于技术人员来说原则上是已知的。
接下来，如在图1G中所示，可以将半导体芯片110与初始衬底112分离。在此，将支撑点116切断。也被称为“拾起”或“拾取”的分离过程例如可以借助于真空吸管148实现，如在图1G中所示。然而，原则上其他方法也可行，例如机械的抓取法。为了切断支撑点116，例如可以绕垂直于半导体芯片110表面的轴线进行扭转和/或进行其他方式的倾斜。然而，原则上其他分离技术也是可行的。
在另一个在图1H中示出的方法步骤中，随后将半导体芯片110施加到载体衬底150上。这些载体衬底150例如可以包括电路板和/或引线框架和/或是另一类型的载体衬底150。该载体衬底150在其待装配的表面154上包括至少一个焊盘152。焊盘152在此原则上可以被理解为任一电结构，其例如可以包括导体电路、框架、连接触点或类似物。在图1H所示的实施例中，在半导体芯片110的背面132上设有贯穿接触部填充材料142的部分区域140例如包括框架156以及贯穿接触部垫158，所述框架优选地完全包住半导体芯片110的棱边，所述贯穿接触部垫158与贯穿接触部128内部的贯穿接触部填充材料142连接，并由此例如与半导体芯片110的正面130上的导体电路146连接。在焊盘152处焊盘框架160或焊盘触点162与所述框架156或贯穿接触部垫158相对应。这些在功能上也可以是混合的，因为例如在侧壁136上的具有贯穿接触部填充材料142的涂层也可以承担电任务。
在图1H所示的装配步骤中，也将在半导体芯片110的背面132上的贯穿接触部填充材料142设置到载体衬底132的焊盘152上。接下来，将半导体芯片110和载体衬底150优选地以低共熔的方式相互压焊。例如，焊盘153可以包括铝，其可以与半导体芯片110的贯穿接触部填充材料142(例如锗)形成低共熔熔合物。为了压焊步骤，例如可以进行热处理，以至少在焊盘152和贯穿接触部填充材料142之间的边界区域中形成低共熔熔合物。
具有优选为1μm的连接部宽度的低共熔压焊连接部至少理论上是气密密封的。通过这种方式可以在半导体110和载体衬底150之间形成气密封闭的中间腔164，这对于多种应用可以是有利的。此外，可能的很小的压焊宽度实现了，具有锗-贯穿接触部的薄芯片也可以以节约空间的方式装配或压焊到其他载体芯片或其他晶片上。相应地，载体衬底150本身可以具有一种或多种功能性，并且原则上可以设计得比在图1H中明显地更为复杂。例如，这可以实现微机电部件(MEMS)的制造。能够通过这种方式产生的半导体元器件166的重要例子是微机械的或微电的传感器元件，其在下面以附图标记168表示。然而，原则上其他应用也是可行的。
在图2至图4中，示出了这类具有传感器元件168的半导体元器件166的不同的例子和/或示出了包括传感器元件168的半导体元器件166。这些原则上展示了在图1H中示出的半导体元器件166的变型，从而对于这些实施例的其他部分可以参照对这个图1H的描述以及对在图1A至图1H中示出的工序的描述。
在图2中，示出了压力传感器170的例子。在这类压力传感器170中，使得气密密封的中间腔164的制造方案是明显特别有利的，因为这个中间腔164例如可以用作参考真空172和/或可以以预定压力或已知压力的气体填充。因此，基于这样的事实，即特别地低共熔连接部通过在小的导体电路密度的情况下的高度气密性而十分出众，在载体衬底150(例如载体芯片)和半导体芯片110(例如薄芯片)之间的参考压力可以被包围。为此，载体衬底150例如可以被设计为集成的开关电路和/或包括这类集成的开关电路，例如ASIC。载体衬底150可以是或者包括例如半导体-载体衬底和/或由其他材料制成的载体衬底，例如由陶瓷材料或玻璃制成。其他的原料原则上也是可行的，例如塑料材料。半导体芯片110本身可以特别地用作压敏膜174。这种压敏膜174还可以包括电阻和/或其他电的元器件，例如用于以压阻的方式读出的电阻。替代地或附加地，该压敏膜174还可以完全地或部分地作为电容器的可动的电极起作用和/或包括这类可动的电极，其中可以在载体衬底150上，例如如在图2中所示设置一个下部的固定电极176。替代地，可以在可选地具有空穴的载体衬底150上，例如预结构化的载体衬底150上压焊上薄芯片-IC形式的半导体芯片110，其同时可以用作膜174。对于同样可以在本发明的范围内实现的微机械式压力传感器的作用原理，例如可以参考罗伯特·博世有限公司2007年版的《机动车辆中的传感器》第128至130页。
在图3中示出了传感器元件168形式的半导体元器件166的另一例子，其在这个例子中被设计为惯性传感器178。惯性传感器是用于测量加速力和旋转力、例如用于测量线性加速力的传感器元件168。惯性传感器178通常包括至少2个，优选为3个或更多个加速度传感器180以用于不同的空间方向或坐标。在所示的例子中，半导体芯片110又在其他部分与根据图1H的实施例相对应，从而又可以参考上面的描述。然而在这种情况下，在半导体芯片110的内部产生形式为指状结构部184的微机械的结构部182。该指状结构部184例如可以与在图1B中示出的沟槽126的制造同时、即与刻槽同时地产生。这些指状结构部184(其中也可以例如为不同的空间方向设置多个这种类型的指状结构部184)由此又形成MEMS，其例如能够以电容的方式读出和/或驱动。这类惯性传感器178的结构和工作方式例如可以参考罗伯特·博世有限公司2007年版的《机动车辆中的传感器》第144至146页。然而，其他的结构和运行方式原则上也是可行的。半导体芯片110例如可以通过低共熔压焊技术被压焊到具有ASIC和/或形式为ASIC的载体衬底150上。然后，可以选择性地进行剪裁(Verknappung)。
在图4中，作为半导体元器件166和传感器元件168的另外的例子示出了所谓的z-加速度传感器186。在这种情况下，载体衬底150包括微机械结构部182，其作为可动的电极188起作用并且在图4中的示图中以虚线圈出。此外，载体衬底150还包括一个下部的固定电极190。压焊上的半导体芯片110(例如薄芯片)可以完全或者部分地作为固定电极192起作用和/或包括这种类型的上部的固定电极192。替代地或附加地，半导体芯片110还可以简单地被用作用于可动电极188的盖部。在z-加速度传感器168工作期间，可以例如以微分的方式评估在z-方向、即在载体衬底150和半导体芯片110之间的连接方向上的还作为z-电极起作用的可动电极188的z-运动。该工作方式和控制装置又可以参考例如罗伯特·博世有限公司2007年版的《机动车辆中的传感器》第144至146页。然而，其他的测量原理和/或控制装置原则上也是可行的。
在图1A至图1H中示出的工序步骤仅是用于实现依据本发明的方法的一些可行的实施例。在本发明的范围内，大量的在设计和策略上的变型均是可行的。因此，可以如在图5中所示，例如完全地或部分地省去绝缘层124的施加。所示出的是基本上与图1F中的示图相应的结构，因此在许多地方可以参考对该图的描述。然而，与图1F不同的是，使用了CMOS-工艺。这种工艺对于半导体技术领域的技术人员来说原则上是已知的。在此，可以通过深掺杂构型(tiefeDotierprofile)在半导体芯片110或半导体芯片110的区域中设置绝缘沟槽或其他类型的绝缘掺杂部194。通过这种方式例如可以在没有绝缘层124和/或介电层134的情况下在半导体芯片110上施加贯穿接触部填充材料142和/或在半导体芯片110中引入贯穿接触部填充材料142，而不会由此与其他元器件、例如半导体芯片110的功能元件118短接而造成危险。通过这种方式可以在压焊和电路区域中避免短接。因此，在此情况下，不需要强制性地沉积介电层134和/或绝缘层124。
特别是具有依据本发明的贯穿接触部的、依据本发明的半导体元器件166对于薄芯片(特别是以芯片膜法制造的芯片)的进一步构建具有重要意义。通过提出的贯穿接触部设计可以实现简单且成本适宜的技术。

Claims (11)

1.一种用于制造半导体元器件(166)的方法，包括下列步骤：
a)在初始衬底(112)上制造半导体芯片(110)，其中所述半导体芯片(110)在至少一个支撑点(116)上与所述初始衬底(112)连接，其中所述半导体芯片(110)具有背离所述初始衬底(112)的正面(130)和朝向所述初始衬底(112)的背面(132)，
b)在至少一个贯穿接触步骤中，将至少一个贯穿接触部填充材料(142)施加到所述半导体芯片(110)上，其中所述背面(132)的至少一个部分区域(140)被涂以所述贯穿接触部填充材料(142)，
c)将所述半导体芯片(110)与所述初始衬底(112)分离，以及
d)将所述半导体芯片(110)施加到至少一个载体衬底(150)上，其中所述半导体芯片(110)的背面(132)的被涂以所述贯穿接触部填充材料(142)的部分区域(140)与所述载体衬底(150)上的至少一个焊盘(152)连接。
2.按照前述权利要求所述的方法，其中，在方法步骤d)中使用低共熔压焊法。
3.按照前述权利要求中任意一项所述的方法，其中，所述贯穿接触部填充材料(142)包括至少一种半导体材料，特别是锗。
4.按照前述权利要求中任意一项所述的方法，其中，所述焊盘(152)包括铝。
5.按照前述权利要求中任意一项所述的方法，其中，在所述贯穿接触步骤中，同时至少一个贯穿接触部(128)的至少一个壁(138)和/或所述半导体芯片(110)的至少一个侧壁(136)被涂上所述贯穿接触部填充材料(142)。
6.按照前述权利要求中任意一项所述的方法，其中，在所述贯穿接触步骤中，在所述背面(132)上制造至少一个框架(156)、特别是封闭的框架(156)，其中在将所述半导体芯片(110)施加到载体衬底(150)上后，在所述框架(156)内产生一个中间腔(164)、特别是气密封闭的中间腔(164)。
7.按照前述权利要求中任意一项所述的方法，其中，所述半导体芯片(110)包括至少一个下列元件：集成电路；传感器结构部；微机械结构部(182)。
8.按照前述权利要求中任意一项所述的方法，其中，在所述贯穿接触步骤中使用共形沉积法，特别是液相沉积法和/或CVD法。
9.按照前述权利要求中任意一项所述的方法，其中，在所述贯穿接触步骤之前，在所述半导体芯片(110)上施加至少一种绝缘材料(124、134)。
10.一种半导体元器件(166)，所述半导体元器件能够按照前述权利要求中任意一项所述的方法制造。
11.按照前述权利要求所述的半导体元器件(166)，其中，所述半导体元器件(166)从下列半导体元器件(166)中选出：传感器元件(168)；压力传感器(170)；惯性传感器(178)；加速度传感器(180)；开关。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070170528A1 (en) * 2006-01-20 2007-07-26 Aaron Partridge Wafer encapsulated microelectromechanical structure and method of manufacturing same
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US11611835B2 (en) * 2020-06-09 2023-03-21 Infineon Technologies Ag Combined corrugated piezoelectric microphone and corrugated piezoelectric vibration sensor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040038500A1 (en) * 2000-06-07 2004-02-26 Larson Charles E. Thin microelectronic substrates and methods of manufacture
US20060051949A1 (en) * 2002-04-16 2006-03-09 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
CN101110401A (zh) * 2006-07-19 2008-01-23 台湾积体电路制造股份有限公司 半导体装置及半导体封装结构
WO2009138138A2 (de) * 2008-05-14 2009-11-19 Robert Bosch Gmbh Verfahren zur herstellung von chips
JP2010098281A (ja) * 2008-09-22 2010-04-30 Alps Electric Co Ltd Ｍｅｍｓセンサ及びその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6225218B1 (en) * 1995-12-20 2001-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
DE102005033254B4 (de) * 2005-07-15 2008-03-27 Qimonda Ag Verfahren zur Herstellung eines Chip-Trägersubstrats aus Silizium mit durchgehenden Kontakten
DE102005035057A1 (de) 2005-07-27 2007-02-01 Robert Bosch Gmbh Verfahren zum Herstellen einer Halbleiterchipanordnung unter Verwendung eines Trägersubstrats und entsprechende Halbleiterchipanordnung
EP1987535B1 (en) 2006-02-01 2011-06-01 Silex Microsystems AB Method of making vias
US7902638B2 (en) * 2007-05-04 2011-03-08 Stats Chippac, Ltd. Semiconductor die with through-hole via on saw streets and through-hole via in active area of die
DE102007043526B4 (de) 2007-09-12 2020-10-08 Robert Bosch Gmbh Verfahren zum Herstellen einer Vielzahl von Chips und entsprechend hergestellter Chip
DE102008040521A1 (de) 2008-07-18 2010-01-21 Robert Bosch Gmbh Verfahren zur Herstellung eines Bauelements, Verfahren zur Herstellung einer Bauelementanordnung, Bauelement und Bauelementanordnung

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040038500A1 (en) * 2000-06-07 2004-02-26 Larson Charles E. Thin microelectronic substrates and methods of manufacture
US20060051949A1 (en) * 2002-04-16 2006-03-09 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
CN101110401A (zh) * 2006-07-19 2008-01-23 台湾积体电路制造股份有限公司 半导体装置及半导体封装结构
WO2009138138A2 (de) * 2008-05-14 2009-11-19 Robert Bosch Gmbh Verfahren zur herstellung von chips
JP2010098281A (ja) * 2008-09-22 2010-04-30 Alps Electric Co Ltd Ｍｅｍｓセンサ及びその製造方法

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