CN101996993A - 利用单一金属化的焊盘下的器件 - Google Patents

利用单一金属化的焊盘下的器件 Download PDF

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Publication number
CN101996993A
CN101996993A CN2009100565260A CN200910056526A CN101996993A CN 101996993 A CN101996993 A CN 101996993A CN 2009100565260 A CN2009100565260 A CN 2009100565260A CN 200910056526 A CN200910056526 A CN 200910056526A CN 101996993 A CN101996993 A CN 101996993A
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China
Prior art keywords
single metal
metal pad
dielectric layer
interlevel dielectric
pad
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CN2009100565260A
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English (en)
Inventor
刘志纲
俞大立
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN2009100565260A priority Critical patent/CN101996993A/zh
Priority to US12/582,690 priority patent/US8373272B2/en
Publication of CN101996993A publication Critical patent/CN101996993A/zh
Pending legal-status Critical Current

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本发明涉及利用单一金属化的焊盘下的器件，提供包含改进的焊盘结构的集成电路器件。该器件具有半导体衬底。多个有源MOS器件形成在半导体衬底上。该器件具有上覆于多个有源MOS器件的层间电介质层和形成在层间电介质层上以及至少一个有源器件的直接上方的至少一个单一金属焊盘。在正方形的至少一个单一金属焊盘上形成至少四个边角区域。在四个边角区域的每一个上形成成角度切除区域。优选地，成角度切除区域处在至少一个单一金属焊盘的正方形的周边。在至少一个单一金属焊盘上方形成具有开口的钝化层。该器件具有在多个有源MOS器件和至少一个单一金属焊盘之间的无缓冲金属层区域。无缓冲金属层区域处在整个的层间电介质层中。在单一金属焊盘下面，层间电介质层基本不含缓冲金属层。

Description

利用单一金属化的焊盘下的器件
技术领域
本发明涉及集成电路及其用于半导体器件制造的处理。更具体地，本发明提供用于制造用于先进集成电路器件的焊盘结构的方法和结构。然而，应该认识到本发明具有更加广泛的可应用性。
背景技术
集成电路已经从制造在单个硅芯片上的少数的互连器件发展到数百万个器件。传统集成电路提供的性能和复杂度已远远超过了当初的想象。为了实现复杂度和电路密度(即，能够被安置到给定芯片面积上的器件的数量)的提高，对于每一代集成电路，最小器件线宽的尺寸(也被称为器件“几何”)变得越来越小。
不断增大的电路密度已不仅提高了集成电路的复杂度和性能，而且也为客户提供了更低成本的部件。集成电路或者芯片制造工厂可能花费成百上千万，甚至十几亿美元。每一制造企业具有一定的生产量，而每片晶片上也将会有一定数量的集成电路。因此，通过制造更小的个体集成电路器件，每片晶片上可以制造更多的器件，这样就可以增加制造企业的产量。要使器件更小总是很有挑战性的，因为每一种用于制造半导体器件的工艺都存在限制。那也就是说，一种给定的工艺通常只能加工到某一特定的线宽尺寸，于是不是工艺就是器件布局需要被改变。此外，随着器件要求越来越快的设计，工艺限制会伴随特定的传统工艺和材料而存在。
这样的工艺的示例是集成电路器件的焊盘结构的制造。这样的焊盘结构已经习惯上变得越来越小，并且占据硅真实面积(real estate)的更小的区域。虽然已经有了明显的提高，但是这样的焊盘设计仍然具有许多限制。仅仅作为示例，这些设计必须变得越来越小而仍然要提供足够的机械性能来支撑焊线结构。焊盘设计常常剥落并导致其他的质量和可靠性问题。此外，使用焊盘之下器件的传统焊盘设计常常要求附加的缓冲层，这需要复杂的制造工艺和结构。在本说明书中，更具体地在下文中可以找到传统高电压半导体器件的这些和其他的限制。
从上面看出，用于处理半导体器件的改进技术是人们所需要的。
发明内容
本发明涉及集成电路及其用于半导体器件制造的处理。更具体地，本发明提供用于制造用于先进集成电路器件的焊盘结构的方法和结构。然而，应该认识到本发明具有更加广泛的可应用性。
在具体的实施例中，本发明提供一种集成电路器件。该器件具有半导体衬底和形成在所述半导体衬底上的多个有源MOS器件。层间电介质层上覆于所述多个有源MOS器件。在所述层间电介质层上以及至少一个所述有源器件的直接上方形成至少一个单一金属焊盘。钝化层具有开口，所述开口形成在所述至少一个单一金属焊盘的上方。在所述多个有源MOS器件和所述至少一个单一金属焊盘之间形成无缓冲金属层区域。所述无缓冲金属层区域在整个的所述层间电介质层之中。在所述单一金属焊盘的下面，所述层间电介质层不含所述缓冲金属层。优选地，所述单一金属焊盘的特征是具有四个边角的正方形，其中所述边角的每一个具有角部切除区域。
在另一个具体实施例中，本发明提供一种集成电路器件，该器件包括改进的焊盘结构。该器件具有半导体衬底。多个有源MOS器件形成在所述半导体衬底上。该器件具有上覆于所述多个有源MOS器件的层间电介质层和形成在所述层间电介质层上以及至少一个所述有源器件的直接上方的至少一个单一金属焊盘。在正方形的所述至少一个单一金属焊盘上形成至少四个边角区域。在所述四个边角区域的每一个上形成成角度切除区域。优选地，所述成角度切除区域处在所述至少一个单一金属焊盘的正方形的周边。在所述至少一个单一金属焊盘上方形成具有开口的钝化层。该器件具有在所述多个有源MOS器件和所述至少一个单一金属焊盘之间的无缓冲金属层区域。所述无缓冲金属层区域处在整个的所述层间电介质层中。在所述单一金属焊盘下面，所述层间电介质层基本不含所述缓冲金属层。
较传统技术，通过本发明获得了的很多优点。例如，本技术为使用依赖于传统技术的工艺提供了便利。在一些实施例中，本方法提供了每个晶片的按管芯计的更高的器件产率。此外，本方法提供了与传统工艺技术兼容而不用对传统设备和工艺进行实质修改的工艺。优选地，本发明提供了不会在焊接过程后剥落或者裂缝的改进的焊盘结构。此外，本发明提供无缓冲层间电介质区域，其允许布线附加的导线层。依据实施例，可以获得这些优点中的一个或多个。这些优点或其他优点将在本说明书全文中并且更具体地在下文中，进行更多的描述。
参考后面的详细说明和附图，可以更全面地了解本发明的各种其他目的、特征和优点。
附图说明
图1是用于焊盘构造之下器件的传统焊盘结构的简化的横截面视图。
图2是用于焊盘构造之下器件的传统焊盘结构的简化的俯视图。
图3是根据本发明的一个实施例的用于焊盘构造之下器件的焊盘结构的简化的横截面视图。
图4和5是根据本发明的实施例的焊盘结构的简化的俯视图。
具体实施方式
根据本发明，提供了涉及集成电路及其用于半导体器件制造的处理的技术。更具体地，本发明提供用于制造用于先进集成电路器件的焊盘结构的方法和结构。然而，应该认识到本发明具有更加广泛的可应用性。
图1是用于焊盘构造之下器件的传统焊盘结构的简化的横截面视图100。如图所示，视图100包括形成在半导体衬底上的多个MOS器件101。优选地，半导体衬底是硅晶片或者绝缘体晶片上硅等。该视图包括第一图案化金属层103，第二图案化金属层105、第三图案化金属层107及其他。在这些层的每一层之间形成层间电介质层。该结构还具有焊盘结构111下面的缓冲金属层109。焊盘结构包括线115上的球结构。钝化层117覆于焊盘结构的一部分之上而形成。缓冲层起到提供焊盘下面的机械支撑，以防止层间电介质层的裂缝。
图2是用于焊盘构造之下器件的传统焊盘结构的简化的俯视图。如图所示，焊盘结构包括常常发生剥落和剥离的角部区域。剥离常常是由层间电介质在焊接工艺中的裂缝导致的。我们在传统的焊盘结构中发现了这些限制。
图3是根据本发明的一个实施例的用于焊盘构造之下器件的焊盘结构的简化的横截面视图。此图仅仅是示例，不应限制这里的权利要求的范围。本领域的普通技术人员将认识到很多变化、替代和修改。如图所示，器件300具有例如硅晶片和绝缘体上硅的半导体衬底。多个有源MOS器件301被形成在半导体衬底上。器件具有上覆于多个有源MOS器件的例如0.18微米或者更薄的层间电介质层311(例如，BPSG、PSG、FSG、掺杂氧化物、APCVD)。如图所示，层间电介质层实际上是在金属层301’和其他层之间形成的多个层间电介质层。优选地，存在多于六层的金属层。依据实施例，这些层中的一些或者全部可以被平坦化。优选地，在层间电介质层上并且在有源器件中的至少一个器件313的径直上方形成至少一个单一金属焊盘303(例如铝)。在至少一个单一金属焊盘的上方形成具有开口的钝化层309(氧化硅上的氮化硅)。器件300在多个有源MOS器件和至少一个的单一金属焊盘之间具有无缓冲金属层区域。无缓冲金属层区域处在整个的层间电介质层之中。也就说，根据本发明的一个实施例，在焊盘的下面不存在缓冲层。优选地，层间电介质层在整个的钝化层之中不含缓冲金属层，允许在层间电介质层中再布置至少一条金属线。
图4和5是根据本发明的实施例的焊盘结构的简化的俯视图。这些图仅仅是示例，不应限制这里的权利要求的范围。本领域的普通技术人员将认识到很多变化、替代和修改。至少四个边缘区域被形成在所述至少一个的单一金属焊盘上的正方形上。在四个边缘区域中的每一个上形成成角度切除区域401。优选地，成角度切除区域位于至少一个的单一金属焊盘的正方形的界限内。成角度切除区域具有45度的角度，而不是正方形焊盘的90度角度。或者，角部切除区域是圆角。依据实施例，单一金属焊盘具有50微米或者更小的长度，0.8微米或者更小的厚度。优选地，单一金属焊盘包括含铝材料并且包含单一金属焊盘表面区域，所述单一金属焊盘表面区域包含基本95％的完整正方形区域。
图5提供了用于焊盘之下器件的焊盘结构的另一个示例。在本说明书全文中，更具体地在下文中，可以找到制造焊盘结构的细节。
一种制造根据本发明的实施例的用于先进集成电路器件的焊盘结构的方法可以总结如下：
1.提供衬底；
2.在衬底上形成MOS晶体管；
3.形成上覆于MOS晶体管的一个或者多个层间电介质层；
4.形成上覆于所述MOS晶体管的一个或者多个金属互连层；
5.使一个或者多个层间电介质层保持不含缓冲金属层；
6.形成上覆于层间电介质层并且直接上覆于至少一个MOS晶体管的焊盘；
7.形成上覆于焊盘的钝化层；
8.在钝化层中形成开口，以暴露焊盘的一部分；
9.将引线焊接到焊盘结构，同时防止层间电介质层中的裂缝；以及
10.按需要进行其他步骤。
上述顺序的步骤提供了根据本发明的实施例的方法。如所示出的，该方法利用了多个步骤的组合，包括形成用于动态随机访问存储器器件的焊盘构造之下器件的焊盘结构的方法。仅仅作为示例，依据具体实施例，引线焊接参数设置范围包括：功率90～100mA；力：10～25g；以及时间：10～15ms。利用下面的设备参数已经实现了这些参数。
表1
  引线焊接机   K&S 8028PPS
  引线拉力和焊接强度测试器   Dage 4000
  金线   99.99％的金
还可以提供许多其他可供选择的方法，其中在不背离这里的权利要求的范围的情况下，加入某些步骤，删去一个或多个步骤，或者一个或多个步骤按照不同的顺序进行。
还应当理解，这里所描述的示例和实施例只是为了说明的目的，本领域的普通技术人员可以根据上述示例和实施例对本发明进行各种修改和变化。这些修改和变化都在本申请的精神和范围内，并且也在所附权利要求的范围内。

Claims (17)

1.一种集成电路器件，包括：
半导体衬底；
形成在所述半导体衬底上的多个有源MOS器件；
上覆于所述多个有源MOS器件的层间电介质层；
在所述层间电介质层中形成的至少六个图案化的金属层；
形成在所述层间电介质层上且在至少一个所述有源器件的直接上方的至少一个单一金属焊盘；
形成在所述至少一个单一金属焊盘的上方的具有一个开口的钝化层；
所述多个有源MOS器件和所述至少一个单一金属焊盘之间的无缓冲金属层区域，所述无缓冲金属层区域在整个的所述层间电介质层之中；
其中，在所述单一金属焊盘的下面，所述层间电介质层基本不含所述缓冲金属层。
2.如权利要求1所述的器件，其中所述单一金属焊盘的特征是一个具有四个边角的正方形，每一个所述边角具有一个角部切除区域。
3.如权利要求2所述的器件，其中所述角部切除区域是圆角。
4.如权利要求3所述的器件，其中所述角部切除区域是成角度的。
5.如权利要求1所述的器件，其中所述单一金属焊盘具有50微米或者更小的长度。
6.如权利要求1所述的器件，其中所述至少一个单一金属焊盘基本不含所述缓冲金属层，所述缓冲金属层耦合到所述单一金属焊盘，以防止焊接过程中所述层间电介质层中的任何裂缝。
7.如权利要求1所述的器件，其中所述至少一个单一金属焊盘具有0.8微米或者更小的厚度。
8.如权利要求1所述的器件，其中所述至少一个单一金属焊盘包括含铝材料。
9.如权利要求1所述的器件，其中所述至少一个单一金属焊盘的特征是一个具有四个角部切除区域的正方形，所述单一金属焊盘包含基本95％的完整正方形区域。
10.如权利要求1所述的器件，其中在整个所述层间电介质层中不含所述缓冲金属层的所述层间电介质层允许在所述层间电介质层中再布置至少另外一条金属线。
11.一种集成电路器件，包括：
半导体衬底；
形成在所述半导体衬底上的多个有源MOS器件；
上覆于所述多个有源MOS器件的层间电介质层；
形成在所述层间电介质层上且在至少一个所述有源器件的直接上方的至少一个单一金属焊盘；
形成在正方形的所述至少一个单一金属焊盘上的至少四个边角区域；
形成在所述四个边角区域的每一个上的成角度切除区域，所述成角度切除区域位于所述至少一个单一金属焊盘的正方形的界限内；
形成在所述至少一个单一金属焊盘上方的具有一个开口的钝化层；
在所述多个有源MOS器件和所述至少一个单一金属焊盘之间的无缓冲金属层区域，所述无缓冲金属层区域处在整个的所述层间电介质层中；
其中，在所述单一金属焊盘下面，所述层间电介质层基本不含所述缓冲金属层。
12.如权利要求11所述的器件，其中所述单一金属焊盘具有50微米或者更小的长度。
13.如权利要求11所述的器件，其中所述至少一个单一金属焊盘基本不含所述缓冲金属层，所述缓冲金属层耦合到所述单一金属焊盘，以防止焊接过程中所述层间电介质层中的任何裂缝。
14.如权利要求11所述的器件，其中所述至少一个单一金属焊盘具有0.8微米或者更小的厚度。
15.如权利要求11所述的器件，其中所述至少一个单一金属焊盘包括含铝材料。
16.一种集成电路器件，包括：
半导体衬底；
形成在所述半导体衬底上的多个有源MOS器件；
上覆于所述多个有源MOS器件的层间电介质层；
形成在所述层间电介质中的至少三个图案化的金属层；
形成在所述层间电介质层上且在至少一个所述有源器件的直接上方的至少一个单一金属焊盘；
形成在所述至少一个单一金属焊盘上方的具有一个开口的钝化层；
在所述多个有源MOS器件和所述至少一个单一金属焊盘之间的无缓冲金属层区域，所述无缓冲金属层区域处在整个的所述层间电介质层中；
其中，在所述单一金属焊盘下面，所述层间电介质层基本不含所述缓冲金属层。
17.一种集成电路器件，包括：
半导体衬底；
形成在所述半导体衬底上的多个有源MOS器件；
上覆于所述多个有源MOS器件的层间电介质层；
形成在所述层间电介质层中的至少三个图案化金属层；
形成在所述层间电介质层上且在至少一个所述有源器件的直接上方的至少一个单一金属焊盘；
形成在所述至少一个单一金属焊盘上方的具有一个开口的钝化层；
其中，在所述单一金属焊盘下面，所述层间电介质层基本不含所述缓冲金属层。
CN2009100565260A 2009-08-13 2009-08-13 利用单一金属化的焊盘下的器件 Pending CN101996993A (zh)

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