CN106898589A - 集成电路 - Google Patents

集成电路 Download PDF

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Publication number
CN106898589A
CN106898589A CN201510957726.9A CN201510957726A CN106898589A CN 106898589 A CN106898589 A CN 106898589A CN 201510957726 A CN201510957726 A CN 201510957726A CN 106898589 A CN106898589 A CN 106898589A
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China
Prior art keywords
integrated circuit
circuit described
contact pad
metal layer
mat structure
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Granted
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CN201510957726.9A
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English (en)
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CN106898589B (zh
Inventor
许永岱
郭添赏
陈彦铨
郑志豪
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN201510957726.9A priority Critical patent/CN106898589B/zh
Priority to US15/008,432 priority patent/US9941220B2/en
Publication of CN106898589A publication Critical patent/CN106898589A/zh
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Publication of CN106898589B publication Critical patent/CN106898589B/zh
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Abstract

本发明公开一种集成电路，其包含一切割道、一接触垫结构以及一延伸垫结构。该切割道是设置于一基底上。该接触垫结构是设置于该基底上的一介电层内，其中该接触垫结构包含多个第一插塞，该些第一插塞是设置在多个位于该介电层内的第一金属层之上。该延伸垫结构是设置在该介电层内，并位于该切割道与该接触垫结构之间，该延伸垫结构具有一第一区及第二区，并包含数量小于该第一金属层的多个第二金属层，其中，位于该第一区内的该多个第二金属层上设置有多个第二插塞，位于该第二区内的该多个第二金属层不设置任何插塞。

Description

集成电路
技术领域
本发明涉及一种半导体集成电路，特别来说，是关于一种可避免芯片裂痕的半导体集成电路。
背景技术
在现代的信息社会中，由集成电路(integrated circuit,IC)所构成的微处理器系统早已被普遍运用于生活的各个层面，例如自动控制的家电用品、移动通讯设备、个人电脑等，都有集成电路的踪迹。而随着科技的日益精进，以及人类社会对于电子产品的各种想象，使得集成电路也往更多元、更精密、更小型的方向发展。
一般所谓集成电路，是通过现有半导体制作工艺中所生产的管芯(die)而形成。制造管芯的过程，是由生产一晶片(wafer)开始：首先，在一片晶片上区分出多个区域，并在每个区域上，通过各种半导体制作工艺如沉积、光刻、蚀刻或平坦化步骤，以形成各种所需的电路路线，接着，再对晶片上的各个区域进行切割而成各个管芯，并利用各种的封装技术，将管芯封装成芯片(chip)，而形成一完整的封装体，最后再将芯片电连接至一电路板，如一印刷电路板(printed circuit board,PCB)，使芯片与印刷电路板的接脚(pin)电连接后，便可执行各种编程的处理，而形成各式电子装置。
为了达成各种微型化的需求，目前业界对于集成电路的封装制作工艺以及封装结构有着强烈的需求。
发明内容
本发明的一目的在于提供一种半导体集成电路，其在接触垫结构与切割道之间设置有一延伸垫结构，该延伸垫结构设置有不具任何插塞结构的一无插塞区域(via free region)，因而可有效防止芯片裂痕(chip cracking)的产生。
为达上述目的，本发明的一实施例提供一种集成电路，其包含一切割道、一接触垫结构以及一延伸垫结构。该切割道是设置于一基底上。该接触垫结构是设置于该基底上的一介电层内，其中该接触垫结构包含多个第一插塞，该些第一插塞是设置在多个位于该介电层内的第一金属层之上。该延伸垫结构是设置在该介电层内，并位于该切割道与该接触垫结构之间，该延伸垫结构具有一第一区及第二区，并包含数量小于该第一金属层的多个第二金属层，其中，位于该第一区内的该多个第二金属层上设置有多个第二插塞，位于该第二区内的该多个第二金属层不设置任何插塞。
本发明的集成电路主要是在接触垫结构及切割道之间，额外设置有延伸垫结构，该延伸垫结构在邻接该切割道处设置有不具任何插塞结构的一区域，由此，可避免该集成电路于进行晶片切割(die saw)制作工艺时，切割应力沿插塞结构传递至接触垫结构内，进而避免发生芯片裂痕的问题。
附图说明
图1至图2为本发明一优选实施例中半导体集成电路的示意图；
图3至图7为本发明一优选实施例中半导体集成电路的封装制作工艺的步骤示意图。
主要元件符号说明
100 半导体晶片
200 管芯区
201 半导体基底
202 金属介电层
204 接触垫结构
205 延伸垫结构
205a 第一区
205b 第二区
212 层间介电层
213、223 切割凹槽
214、215、224、225、234、235、244 金属层
216、217、226、227、236 插塞
300 切割道
400 密封环
500 晶片
501 连接件
503、505 导电层
510、530 封装材料
520 金属层
600 承载件
D 切割方向
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的数个优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
请参考图1至图2，所绘示者为本发明一优选实施例中半导体集成电路的示意图，其中图1是半导体晶片100的平面示意图；图2为图1中沿A-A’切线获得的剖面示意图。
半导体晶片100可包含有多个管芯区(die region)200，且其是由互相交错的切割道300所环绕，以分隔各管芯区200。此外，切割道300与管芯区200之间，还设置有密封环(seal ring)400，其是邻接并环绕各管芯区200，如图1所示。管芯区200中应形成有所需的电路元件，例如包含晶体管(未绘示)、掺杂区(未绘示)、金属内连接系统(未绘示)等，但不以此为限；且各管芯区200可在后续制作工艺中经切割制作工艺而形成各管芯(die,未绘示)。此外，在一实施例中，切割道300还可以设置有测试电路301，如图1所示，但不以此为限。在另一实施例中，也可选择省略测试电路301(未绘示)。需说明的是，本实施例为简化说明，仅绘示部分的管芯区200，其实际数量及排列方式可视实际需求而变动，不以图1所示样态为限
各管芯区200中由下而上依序可包含有一半导体基底201，例如是硅基底(silicon substrate)、硅锗基底(silicon-germanium substrate)或硅覆绝缘基底(silicon-on-insulator,SOI substrate)等，以及形成于其一表面(例如是正面)上的一金属介电(inter-metal dielectric,IMD)层202。具体来说，半导体基底201内或其上还可进一步形成有所需的主动元件，如晶体管(未绘示)等；而金属介电层202内则可形成有一接触垫结构204、延伸垫结构205及所需的金属内连线，其都是由依序堆叠的多个金属层(metal layer)及多个插塞(via)所组成，例如是由低阻质的金属材质组成，如铜(copper,Cu)、铝(aluminum,Al)、钨(tungsten,W)等。并且，在一实施例中，接触垫结构204的该些金属层可选择与延伸垫结构205的该些金属层彼此直接连接，如金属层224、234及金属层225、235所示。也就是说，接触垫结构204的金属层224、234可与延伸垫结构205的金属层225、235一体成形，并经由同一道金属制作工艺形成，但不以此为限。在另一实施例中，接触垫结构204的该些金属层与延伸垫结构205的金属层也可选择彼此不连接，如金属层214及金属层215所示。
在一实施例中，延伸垫结构205具有少于接触垫结构204的金属层数量，举例来说，当接触垫结构204具有依序堆叠的m层金属层(m不小于2)；延伸垫结构205则具有堆叠的m-n(m大于n，n不等于零)层金属层，但不以此为限。在另一实施例中，延伸垫结构205则也可具有其他数量小于m层的该金属层。
在本实施例中，接触垫结构204包含由半导体基底201该表面依序往上堆叠的4层金属层214、224、234、244，以及分别形成于各金属层214、224、234上的插塞216、226、236；而延伸垫结构205则是位于接触垫结构204与切割道300之间，其包含同样是由半导体基底201该表面依序往上堆叠的3层金属层215、225、235，以及分别形成于各金属层215、225上的插塞217、227，如图2所示。
需注意的是，延伸垫结构205优选具有邻接接触垫结构204的一第一区205a，以及邻接切割道300及密封环400的第二区205b。其中，延伸垫结构205的插塞217、227仅形成在第一区205a的金属层215、225上，如图2所示。也就是说，延伸垫结构205的第二区205b内的金属层215、225、235上不具有任何插塞。在另一实施例中，延伸垫结构205的第二区205b大体上具有一长度L，例如是约为20微米至40微米，优选为36微米，或是约为延伸垫结构205整体长度的二分之一。
此外，延伸垫结构205位于金属层215、225上的插塞217、227的数量优选是逐层递减，由此，使延伸垫结构205相对于接触垫结构204可具有较少的插塞数量。换句话说，在延伸垫结构205的第一区205a中，设置在金属层225的插塞227的数量优选是小于设置在金属层215的插塞217的数量，例如是约少于15％，或者是使设置在金属层225的插塞227的间距大于设置在金属层215的插塞217，但不以此为限。此外，在另一实施例中还可包含一层间介电(interlayer dielectric,ILD)层212，位于金属介电层202及半导体基底201之间，并且层间介电层212也可形成有所需的主动元件等(未绘示)。
由此可知，本发明例优选实施例中的集成电路主要是在接触垫结构及切割道之间，额外设置有延伸垫结构，该延伸垫结构在邻接该切割道处设置有不具任何插塞结构的一无插塞区域(via-free region)，该无插塞区域例如是具有约为20微米至40微米的长度，或是约为该延伸垫结构整体长度的二分之一。由此，可避免该集成电路于进行晶片切割(die saw)制作工艺时，切割应力沿插塞结构传递至接触垫结构内，进而避免该集成电路于切割制作工艺时发生芯片裂痕的问题。
本发明的集成电路可接着进行如图3至图7所示的封装制作工艺。首先，可选择先进行管芯区200的薄化制作工艺，例如是包含从半导体基底201的另一表面(例如是背面)进行一化学机械抛光(chemical mechanical polishing,CMP)制作工艺或者是一蚀刻制作工艺，以减少其整体厚度，如图3所示。
接着，进行一封装步骤以将半导体晶片100对应地封装至另一晶片500的阵列排列的管芯区(未绘示)上。本实施例的封装步骤，是指任何电连接管芯区200的接触垫结构204与晶片500中任一管芯区(未绘示)的步骤。具体来说，该封装步骤包含利用表面粘着技术(surface-mount technology,SMT)，形成一连接件501，例如锡球(solder bond)，以电连接管芯区200的连接垫结构204以及晶片500中该对应管芯区的一导电层503，如图3所示，但不以此为限。在其他实施例中，也可使用其他技术，例如硅贯穿电极、铜柱、硅中间板(interposer)或是打线(wire bonding)等方式来实现。此外，在一实施例中，晶片500可先接合至一承载件600，例如是玻璃基板，再进行与半导体晶片100的封装制作工艺，但不以此为限。或者，在另一实施例中，该封装步骤也可选择直接将半导体晶片100对应地封装至一管芯(未绘示)或一电路板(未绘示)等。
然后，进行一第一光刻暨蚀刻制作工艺(photolithography and etchingprocess,PEP)，移除半导体晶片100一部分半导体基底201及一部分的层间介电层212，以在半导体基底201经薄化制作工艺的该表面(例如是背面)形成一切割凹槽213，对应切割道300，如图3所示。需注意的是，该第一光刻暨蚀刻制作工艺仅部分移除半导体晶片100的半导体基底201，而不蚀刻晶片500。
接着，移除半导体晶片100一部分的金属介电层202以及密封环400，并在半导体基底201经薄化制作工艺的该表面共形地形成一封装材料510，例如是包含聚合物(polymer)或苯并环丁烯(benzocyclobutene,BCB)，如图4所示。然后，进行一第二光刻暨蚀刻制作工艺，继续移除半导体晶片100的金属介电层202以及密封环400，并进一步移除晶片500的一部分，使晶片500的一导电层505可被暴露出，进而形成自半导体基底201延伸至晶片500的切割凹槽223，如图5所示。
此外，另需注意的是，形成切割凹槽223时，除了可暴露出晶片500的导电层505之外，还可进一步使管芯区200最上层的金属层(即，最远离基底201正面的金属层)，例如是延伸垫结构205的金属层235，自切割凹槽223的一侧被暴露出，如图5所示，但不以此为限。之后，即可进一步于封装材料510上形成一金属层520，以直接电连接导电层505及金属层235的一侧，如图6所示。
最后，再形成封装材料530，覆盖部分的金属层520，如图7所示。由此，即完全本发明优选实施例的封装制作工艺，后续则可继续进行一晶片切割制作工艺，例如是利用钻石刀机械切割、激光切割或钻石刀与激光混用的切割方式，自切割凹槽223处，沿着半导体基底201的背面向正面(即切割方向D)进行切割，以形成多个阵列管芯(未绘示)。该阵列管芯还可继续进行后续的封装制作工艺，进而制作出可与电路板电连接的芯片(chip)。
由前述步骤即可完成本发明的封装制作工艺，其主要是通过锡球及/或金属层分别电连接该半导体晶片的接触垫结构及该另一晶片、一管芯或一电路板的一导电区，使该半导体晶片可对应地封装至该另一晶片的管芯区、该管芯或该电路板。此外，本发明的集成电路因额外设置有不具任何插塞结构的延伸垫结构，可避免该半导体晶片于进行晶片切割制作工艺时，其切割应力沿插塞结构传递至接触垫结构内，进而可避免发生芯片裂痕的问题。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种集成电路，其特征在于包含：
切割道，设置于一基底上；
接触垫结构，设置于该基底上的一介电层内，其中该接触垫结构包含多个第一插塞，该些第一插塞是分别设置在多个位于该介电层内的多个第一金属层之上；以及
延伸垫结构，设置在该介电层内，并位于该切割道与该接触垫结构之间，该延伸垫结构具有一第一区及一第二区，并包含数量小于该第一金属层的多个第二金属层，其中，位于该第一区内的该多个第二金属层上设置有多个第二插塞，位于该第二区内的该多个第二金属层不设置任何插塞。
2.依据权利要求1所述的集成电路，其特征在于，该第二区邻接该切割道。
3.依据权利要求1所述的集成电路，其特征在于，该第二区具有一长度，该长度约为该延伸垫结构的长度的二分之一。
4.依据权利要求1所述的集成电路，其特征在于，该第二区具有一长度，约为20微米至40微米。
5.依据权利要求1所述的集成电路，其特征在于，该接触垫结构的该多个第一金属层相互堆叠并具有一数量m；该延伸垫结构的该多个第二金属层相互堆叠并具有一数量m-n，其中m大于n，n不等于零。
6.依据权利要求1所述的集成电路，其特征在于还包含：
密封环，设置在该切割道与该延伸垫结构之间。
7.依据权利要求6所述的集成电路，其特征在于，该密封环邻接该延伸垫结构的该第二区。
8.依据权利要求1所述的集成电路，其特征在于，该基底具有一第一表面及一第二表面，且该介电层设置在该基底的该第一表面。
9.依据权利要求8所述的集成电路，其特征在于，该切割道包含一切割凹槽，该切割凹槽是设置在该基底的该第二表面上。
10.依据权利要求8所述的集成电路，其特征在于，该第二插塞在该多个第二金属层上的数量是自该基底的第二表面自第一表面逐层渐减。
11.依据权利要求10所述的集成电路，其特征在于，该延伸垫结构的该多个第二金属层包含一第一层及一第二层，该第一层及该第二层自该基底的该第二表面向该第一表面堆叠，且设置在该第二层的该第二插塞的数量约少于设置在该第一层的该第二插塞的数量的15％。
12.依据权利要求1所述的集成电路，其特征在于，该第二插塞的数量小于该第一插塞。
13.依据权利要求1所述的集成电路，其特征在于，该基底还包含一管芯区，该管芯区包含该接触垫结构及该延伸垫结构且该切割道环绕管芯区。
14.依据权利要求1所述的集成电路，其特征在于，该接触垫结构的该多个第一金属层与该延伸垫结构的该多个第二金属层彼此连接。
15.依据权利要求14所述的集成电路，其特征在于，该接触垫结构的该多个第一金属层与该延伸垫结构的该多个第二金属层一体成型。
16.依据权利要求1所述的集成电路，其特征在于，该接触垫结构的该多个第一金属层与该延伸垫结构的该多个第二金属层彼此不连接。
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