CN107833837B - 具有反向轮廓的铜柱的信息结构 - Google Patents

具有反向轮廓的铜柱的信息结构 Download PDF

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Publication number
CN107833837B
CN107833837B CN201710618102.3A CN201710618102A CN107833837B CN 107833837 B CN107833837 B CN 107833837B CN 201710618102 A CN201710618102 A CN 201710618102A CN 107833837 B CN107833837 B CN 107833837B
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polymer layer
layer
opening
inclination angle
metal column
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CN107833837A (zh
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郑锡圭
张兢夫
韩至刚
黄信杰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括形成第一聚合物层以覆盖晶圆的金属焊盘,以及图案化第一聚合物层以形成第一开口。暴露于第一开口的第一聚合物层的第一侧壁具有第一倾斜角,其中第一侧壁与金属焊盘接触。该方法还包括在第一开口中形成金属柱,锯切晶圆以产生器件管芯,将器件管芯密封在密封材料中,实施平坦化以暴露金属柱,在密封材料和器件管芯上方形成第二聚合物层,以及图案化第二聚合物层以形成第二开口。通过第二开口暴露金属柱。暴露于第二开口的第二聚合物层的第二侧壁具有比第一倾斜角度更大的第二倾斜角。本发明实施例涉及具有反向轮廓的铜柱的信息结构。

Description

具有反向轮廓的铜柱的信息结构
技术领域
本发明实施例涉及具有反向轮廓的铜柱的信息结构。
背景技术
随着半导体技术的进步,半导体芯片/管芯变得越来越小。同时,需要将更多功能集成在半导体管芯中。因此,半导体管芯需要将越来越多的I/O焊盘封装在更小的区域中,并且因此I/O焊盘的密度随着时间的推移增加。结果,器件管芯的封装变得更加困难,这会对封装产量产生不利影响。
为了解决这个问题,已经开发了将器件管芯密封在诸如模塑料的密封材料中并且形成再分布线以连接至器件管芯的表面焊盘的工艺。再分布线跨越到比器件管芯更大的区域,并且允许形成更多的I/O焊盘,而不需要增加器件管芯的面积。
发明内容
根据本发明的一个实施例,提供了一种形成封装件的方法,包括:形成第一聚合物层以覆盖晶圆的金属焊盘;图案化所述第一聚合物层以形成第一开口,通过所述第一开口暴露所述金属焊盘,其中,所述第一聚合物层的从所述第一开口暴露的第一侧壁限定投影于所述金属焊盘的上表面上方的第一倾斜角;在所述第一开口中形成金属柱;形成环绕并覆盖所述金属柱的介电层;锯切所述晶圆以产生器件管芯;将所述器件管芯密封在密封材料中;实施平坦化以暴露所述金属柱;在所述密封材料和所述器件管芯上方形成第二聚合物层;以及图案化所述第二聚合物层以形成第二开口,其中,通过所述第二开口暴露所述金属柱,其中,所述第二聚合物层的暴露于所述第二开口的第二侧壁具有大于所述第一倾斜角的第二倾斜角。
根据本发明的另一实施例,还提供了一种形成封装件的方法,包括:形成第一聚合物层以覆盖晶圆的金属焊盘;图案化所述第一聚合物层以形成第一开口,通过所述第一开口暴露所述金属焊盘;在第一温度处烘焙所述晶圆;在所述第一开口中形成金属柱;形成环绕并覆盖所述金属柱的介电层;锯切所述晶圆以产生器件管芯;将所述器件管芯密封在密封材料中;实施平坦化以暴露所述金属柱;在所述密封材料和所述器件管芯上方形成第二聚合物层;图案化所述第二聚合物层以形成第二开口,其中,通过所述第二开口暴露所述金属柱;在低于所述第一温度的第二温度处烘焙所述第二聚合物层;以及形成再分布线,所述再分布线具有填充所述第二开口的部分。
根据本发明的又一实施例,还提供了一种封装件,包括:器件管芯,包括:金属焊盘;第一聚合物层,覆盖所述金属焊盘的边缘部分;以及金属柱,延伸到所述第一聚合物层内以接触所述第一聚合物层的第一侧壁,其中,所述第一聚合物层的所述第一侧壁限定相对于所述金属焊盘的上表面的第一倾斜角;密封材料,密封所述器件管芯,其中,所述金属柱的顶面与所述密封材料的顶面共面;第二聚合物层,位于所述密封材料和所述器件管芯上方;以及再分布线,具有延伸到所述第二聚合物层内以接触所述第二聚合物层的第二侧壁的部分,其中,所述第二侧壁具有大于所述第一倾斜角的第二倾斜角。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1至图24示出了根据一些实施例的形成封装件的中间阶段的截面图。
图25和图26分别示出根据一些实施例的器件管芯和封装件的一些部分的截面图。
图27示出根据一些实施例的封装工艺的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
图1至图24示出了根据一些实施例的形成集成扇出(InFO)封装件的中间阶段的截面图。在如图27所示的工艺流程300中还示意性地示出了图1至图24中示出的步骤。
图1示出根据一些实施例的晶圆10的截面图。晶圆10包括多个半导体芯片12。晶圆10还包括在半导体芯片12内延伸的半导体衬底14。半导体衬底14可以是块状硅衬底或绝缘体上硅衬底。半导体衬底14还可以包括包括Ⅲ族、Ⅳ族和Ⅴ族元素的其他半导体材料。在半导体衬底14的表面14A处形成集成电路16。集成电路16可以包括位于其中的互补金属氧化物半导体(CMOS)晶体管。
半导体芯片12可以进一步包括位于半导体衬底14上方的层间介电层(ILD)17和位于ILD 17上方的互连结构22。互连结构22包括介电层24以及形成在介电层24中的金属线20和通孔18。根据本发明的一些实施例,介电层24由低k介电材料形成。例如,低k介电材料的介电常数(k值)可以小于约2.8或小于约2.5。金属线20和通孔18可以由铜、铜合金或其他含金属的导电材料形成。可以使用单镶嵌和/或双镶嵌工艺形成金属线20和通孔18。
金属焊盘26形成在互连结构22上方,并且可以通过金属线20和通孔18电连接至电路16。金属焊盘26可以是铝焊盘或铝-铜焊盘,或者可以包括其他金属。根据本发明的一些实施例,位于金属焊盘26下面并且接触金属焊盘26的金属部件是金属线。根据可选实施例,位于金属焊盘26下面并且接触金属焊盘26的金属部件是金属通孔。
形成钝化层28以覆盖金属焊盘26的边缘部分。通过钝化层28中的开口暴露每个金属焊盘26的中心部分。钝化层28可以由非多孔材料形成。根据本发明的一些实施例,钝化层28是包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层(未示出)的复合层。根据可选实施例,钝化层28由非掺杂硅酸盐玻璃(USG)、氮氧化硅等形成。虽然示出一个钝化层28,但是可以存在多于一个的钝化层。
在钝化层28上方涂覆聚合物层30并覆盖钝化层28。相应步骤在图27所示的工艺流程中示出为步骤302。聚合物层30由聚合物形成,聚合物可以是诸如聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)等的光敏材料。实施预烘焙,接着进行如图1所示的曝光。使用包括不透明部分和具有期望图案的透明部分的光刻掩模32来曝光(light-expose)聚合物层30,其中光34穿过光刻掩模32的透明部分,并且被光刻掩模32的不透明部分阻挡。
接下来,显影曝光的聚合物层30,去除一些部分以形成开口31,并且下面的金属焊盘26的中心部分暴露于开口31。相应步骤在图27所示的工艺流程中示出为步骤304。图2中示出所得的结构10。根据本发明的一些实施例,聚合物层30的侧壁的倾斜角γ1是大致垂直的,例如在约85度和约95度之间的范围内。
在显影聚合物层30之后,进一步烘焙晶圆10以固化聚合物层30并驱除溶剂。相应步骤在图27所示的工艺流程中示出为步骤306。图3中示出所得的晶圆10。根据一些实施例,用于烘焙晶圆10的相对高的温度可以在约370℃和约410℃之间的范围内。根据一些实施例,烘焙可持续约40分钟至约120分钟之间的时间段。烘焙导致聚合物层30的完全固化。
图25示出晶圆10的部分的放大图。如图25所示,在高温烘焙之后,聚合物层30的侧壁轮廓是平滑的和圆的,其中聚合物层30的侧壁30'具有平滑且连续的圆形部分。或者,从侧壁30'的底部至顶部,侧壁30'的倾斜角可以连续且平滑地增加。虚线37示意性地表示在高温烘焙之前聚合物层30的侧壁的位置和轮廓,并且圆形侧壁30'示出在高温烘焙之后聚合物层30的形状。观察到,高温烘焙导致聚合物层30朝向金属焊盘26的中心线回流。回流是部分回流,并且软化聚合物层30以具有高粘度。聚合物层30的回流导致侧壁30'的倾斜角减小。例如,在侧壁30'接触金属焊盘26的位置处(或直接相邻的区域处),侧壁30'的倾斜角γ'在约15度和约45度之间的范围内,并且可以在约20度和约30度之间的范围内。减小的角度γ'可以有助于在后续平坦化期间减小聚合物层30和金属焊盘26之间的应力,并且降低了聚合物层30从金属焊盘26剥离的可能性。
烘焙温度选择为足够高以导致聚合物层30稍微回流以产生如图25所示的轮廓。然而,回流导致开口31的宽度从W1减小至W2。根据一些实施例,宽度差(W1-W2)在约6μm和约10μm之间的范围内。比率W2/W1可以在约0.8和约0.9之间的范围内。为了在金属焊盘26和将在后续步骤中形成的上面的金属柱46(图26)之间保持足够的接触面积,通过选择适当的烘焙温度来控制回流。应当理解,通过聚合物30的材料部分地确定期望的烘焙温度。此外,聚合物30的组分(诸如在烘焙期间将蒸发的溶剂的量)还影响期望的烘焙温度,并且因此可以实施实验以产生期望的回流。
接下来,参考图4,例如通过物理汽相沉积(PVD)在聚合物层30上沉积凸块下金属(UBM)层36。根据本发明的一些实施例,UBM层36由铜层或铜合金层形成。根据可选实施例,UBM层36包括钛层以及包括由铜或铜合金形成的晶种层。UBM层36还与金属焊盘26接触。然后施加光刻胶38并图案化以形成开口,通过开口暴露UBM层36。
参考图5,例如通过镀将金属区42选择性地沉积到开口40内。相应步骤在图27所示的工艺流程中示出为步骤308。根据一些示例性实施例,金属区42由在用于熔化焊料的回流工艺中不熔化的非焊料材料形成。例如,金属区42可以由铜或铜合金形成。在金属区42的顶面上形成焊帽44,其中,焊帽44可以由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成并且可以是无铅焊帽或含铅焊帽。还可以通过镀形成焊帽44。
在形成金属区42和焊帽44之后,去除光刻胶38,如图6所示。接下来,去除先前由光刻胶38覆盖的UBM层36的部分,留下未去除的金属区42和焊帽44,如图7所示。在后续讨论中,UBM层36的剩余部分和金属区42的组合称为金属柱46。
根据一些实施例,实施回流,从而使得焊帽44具有圆形的顶面。焊帽44中的焊料包括保持与金属区42重叠的一些部分,并且可以包括或可以不包括向下流动以接触金属柱46的侧壁的一些其他部分。回流的焊帽44可以不覆盖金属柱46的侧壁的底部。根据可选实施例,由于将在后续步骤中去除焊帽44,所以不实施焊帽44的回流。
接下来,如图8所示,对焊帽44实施探测步骤以测试半导体芯片12的电特性。通过使探针48与焊帽44接触来实施该探测。探针48是探针卡50的部分,探针卡50电连接至测试设备(未示出)。通过探测,发现有缺陷的半导体芯片12,并且确定良好的半导体芯片12。有利地,焊帽44比下面的金属柱46更软。因此,探针48和焊帽44之间的接触比探针48和金属柱46之间的接触更好。因此,与如果不形成焊帽44相比,该探测更加可靠。
如图9所示,在探测之后,形成聚合物层52以覆盖晶圆10的顶面。相应步骤在图27所示的工艺流程中示出为步骤310。因此,金属柱46和焊帽44嵌入在聚合物层52中,其中,聚合物层52的顶面高于焊帽44的顶端。聚合物层52可以由选自聚合物层30的相同候选材料(诸如PBO)的材料形成。然后对晶圆10实施管芯锯切,并且半导体管芯12彼此分离。相应步骤在图27所示的工艺流程中示出为步骤312。分离的半导体管芯12此后称为器件管芯12。
图10至图23示出器件管芯12的封装以形成InFO封装件,从而使得InFO封装件的所得的电连接件(诸如焊料区)可以分布至比器件管芯12更大的区域。图10示出载体54和形成在载体54上的释放层56。载体54可以是玻璃载体,并且可以具有圆形顶视形状和常见的硅晶圆的尺寸。可以由光热转换(LTHC)涂覆材料形成释放层56。释放层56的顶面是平坦的。在释放层56上形成介电层58。根据一些实施例,介电层58由聚合物形成,该聚合物还可以是通过曝光和显影来图案化的诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的光敏材料。
图11至图13示出形成金属桩60。相应步骤在图27所示的工艺流程中示出为步骤313。贯穿说明书,由于金属桩60穿过后续分配的密封材料,所以金属桩60可选地称为贯通孔60。
参考图11,例如,通过物理汽相沉积(PVD)来形成金属晶种层62。根据一些实施例,金属晶种层62可包括铜,或可以包括钛层和钛层上方的铜层。在金属晶种层62上方形成光刻胶64。
然后使用光刻掩模(未示出)对光刻胶64实施曝光。如图11所示,在后续显影之后,在光刻胶64中形成开口66。金属晶种层62暴露于开口66。开口66具有沙漏轮廓,其中,底部宽度W1和顶部宽度W2大于中间宽度W3。此外,开口66的最小宽度可以接近开口66的中间高度。
选择光刻胶64的材料,以使所得的开口66具有沙漏轮廓。根据一些示例性实施例,光刻胶包括TOK P50系列光刻胶(由在美国注册的东京应化工业所制造)。根据一些实施例,TOK P50可包括聚丙烯酸酯、交联剂和光敏引发剂。通过使用适当的光刻胶材料,并且调整曝光和显影的工艺条件,可产生沙漏轮廓。
接下来,如图12所示,通过镀形成贯通孔60。控制镀速率,以确保所镀的贯通孔60的形状遵循开口66的形状。在后续步骤中,去除光刻胶64,并且因此暴露下面的金属晶种层62的部分。然后,在蚀刻步骤中去除金属晶种层62的暴露部分。在图13中示出所得的贯通孔60。贯穿说明书,金属晶种层62的剩余部分认为是贯通孔60的部分,并且未单独示出。
贯通孔60具有窄于相应的顶部和相应的底部的中间部分。应该注意,图13示出贯通孔60在一个垂直平面中的形状。如果从任何其他的垂直平面观察,则贯通孔60还是具有沙漏轮廓。贯通孔60的顶视图形状可以是圆形、矩形、正方形、六边形等。
图14示出器件管芯12放置在图13所示的结构上的透视图,其中,器件管芯12布置为行和列。放置在探测期间找到的良好管芯12,并且丢弃缺陷管芯12。虽然图14中未示出贯通孔60,但是它们还存在。
图15示出图14所示的结构的部分的截面图。在图15中,仅示出单个器件管芯12和它周围的贯通孔60。然而,应该注意,在晶圆级处实施并且对载体54上的所有器件管芯12均实施图15至图23中所示的工艺步骤。器件管芯12放置在载体54上,并且通过作为粘合膜的管芯附接膜(DAF)68粘附至介电层58。相应步骤在图27所示的工艺流程中示出为步骤314。
接下来,参照图16,将密封材料70密封在器件管芯12和贯通孔60上。相应步骤在图27所示的工艺流程中示出为步骤316。密封材料70填充相邻贯通孔60之间的间隙以及贯通孔60和器件管芯12之间的间隙。密封材料70可以包括模塑料、模制底部填充物、环氧树脂或树脂。模塑料可以包括聚合物(例如树脂)和聚合物中的填料,其中填料可以包括二氧化硅(无定形SiO2)的球形颗粒、氧化铝等。密封材料70的顶面高于金属柱46和贯通孔60的顶端。
接下来,如图17所示,实施诸如化学机械抛光(CMP)步骤或研磨步骤的平坦化以削薄密封材料70,直到暴露贯通孔60和金属柱46。相应步骤在图27所示的工艺流程中示出为步骤318。由于研磨,贯通孔60的顶端与金属柱46的顶面齐平(共面),并且与密封材料70的顶面共面。在示出的示例性实施例中,实施平坦化,直到暴露金属柱46。因此,去除焊帽44的与金属柱46重叠的部分。在平坦化之后,保留焊帽44的位于金属柱46的侧壁上的部分(如果由回流引起)。
图26示出包括金属柱46的晶圆10的部分的截面图。如图26所示,聚合物层30以小倾斜角γ'连接至金属焊盘26。这可以有助于释放在平坦化期间由于消除金属柱46的尖锐底角而施加在聚合物层30和金属焊盘26上的应力。小倾斜角γ'因此有益于减少聚合物层30和金属焊盘26之间的分层,部分是由于在PI朝向焊盘26的中心回流时聚合物层30在金属焊盘26上方增加的接触/重叠,因此增加了在接合界面处的结构完整性并且降低了分层的可能性。
金属柱46包括低于聚合物层30的顶面的下部46A和高于聚合物层30的顶面的上部46B。下部46A和上部46B的厚度分别为T1和T2。根据一些实施例,厚度比T1/T2在约1.1和1.4之间的范围内。部分46B的侧壁的倾斜角β可以在约60度和约105度之间的范围内,或在约70度和约90度之间的范围内。
进一步参考图26,根据一些实施例,侧壁30'的弯曲部分可以具有半径R1,其中比率R1/T1可以大于约0.2、大于约0.3、或在约0.3和0.5之间的范围内,大半径R1在后续平坦化中在释放应力方面更有效,如将在后续段落中讨论的。然而,半径R1不能太大,因为增加的值R1可能导致金属柱46和金属焊盘26之间的接触面积太小。
再次参考图17,在平坦化之后,贯通孔60可以保持具有沙漏轮廓。可以通过前面的工艺步骤得到贯通孔60的若干轮廓。根据本发明的一些实施例,贯通孔60可包括顶部60A、中间部分60B和底部60C,其中顶部60A和底部60C可具有垂直的侧壁和均匀的宽度(由虚线60'示出),而中间部分60B具有倾斜的侧壁和连续变化的宽度,如图所示。根据可选实施例,部分60A、60B和60C都具有逐渐且连续变化的宽度,贯通孔60的中间部分最窄,并且相应的上部变得越来越宽,下部也变得越来越宽,如图17中的实线所示。
图18至图24示出前侧RDL和焊料区的形成。相应步骤在图27所示的工艺流程中示出为步骤320。参考图18,例如使用光敏材料形成聚合物层72。根据一些实施例,聚合物层72由聚酰亚胺形成。根据可选实施例,聚合物层72由诸如PBO的其他介电材料形成。在聚合物层72中形成开口74以暴露贯通孔60和金属柱46。
聚合物层72和开口74的形成包括分配聚合物层72、预烘焙聚合物层72、在聚合物层72上实施曝光以及显影暴露的聚合物层72。显影后,烘焙聚合物层72。根据一些实施例,开口74窄于开口31(图2)。因此,期望由烘焙导致的聚合物层72的回流效应不如聚合物层30显著,从而使得开口74的宽度没有开口31减少得那么多。否则,将填充开口74的再分布线(RDL)之间的接触面积将减小太多,并且接触电阻将太高。此外,由于在RDL的形成中不实施CMP,所以在减小应力方面的要求较低,并且倾斜角α1可以大于倾斜角γ'(图25)。
根据一些实施例,为了限制聚合物层72的回流,烘焙温度(在显影之后实施)是低的,并且低于聚合物层30的烘焙温度。根据本发明的一些实施例,聚合物层72的烘焙温度在约225℃和约275℃之间的范围内。聚合物层72的烘焙温度还可以比聚合物层30的烘焙温度低高于约100℃的差值,并且该差值还可以在约120℃和160℃之间的范围内。烘焙时间可以在约40分钟和约80分钟的范围内。
根据一些实施例,聚合物层30和聚合物层72由相同的材料(例如,聚酰亚胺)形成,并且聚合物层30的烘焙温度高于聚合物层72的烘焙温度,以在聚合物层30中引起比聚合物层72中更多的回流。根据可选实施例,聚合物层30和聚合物层72由不同的材料形成,例如,一个由聚酰亚胺形成并且另一个由PBO形成,并且聚合物层30的烘焙温度还高于聚合物层72的烘焙温度以在聚合物层30中引起比聚合物层72中更多的回流。根据又一实施例,聚合物层30和聚合物层72由不同的材料形成。例如,聚合物层30可以由具有比聚合物层72更低的回流温度的材料形成,因此层30和72两者可以在相同的温度(或具有小于约20℃的差值的类似温度)处实施,而聚合物层30仍然回流得比聚合物层72更多。
因为聚合物层72的较低烘焙温度导致比聚合物层30更小的回流效应,所以在烘焙聚合物层72之后,聚合物层72的原始垂直侧壁比聚合物层30的侧壁倾斜得少且没有聚合物层30的侧壁圆。根据本发明的一些实施例,倾斜角α1大于角γ'(图26)。差值(β-γ')可以大于约30度,并且可以在约30度和约60度之间的范围内。倾斜角α1可以在约70度和90度之间的范围内。较低的烘焙温度对于不能维持非常高的温度的载体54也是有益的。
接下来,参照图19,形成再分布线(RDL)80以连接至金属柱46和贯通孔60。RDL 80还可以互连金属柱46和贯通孔60。RDL 80包括位于聚合物层72上方的金属迹线(金属线)以及延伸至开口74(图18)内以电连接至贯通孔60和金属柱46的通孔。根据一些实施例,在镀工艺中形成RDL 80,其中,每个RDL 80均包括晶种层(未示出)和位于晶种层上方的镀的金属材料。晶种层和镀的材料可以由相同材料或不同材料形成。RDL 80可以包括金属或金属合金,该合金包括铝、铜、钨和/或它们的合金。RDL 80由非焊料材料形成。RDL 80的通孔部分可与金属柱46和贯通孔60的顶面物理接触。根据一些实施例,厚度比率T1/T3(图26所示的T1)在约1.3和1.6之间的范围内,其中厚度T3是RDL 80的厚度。
参考图20,在RDL 80和聚合物层72上方形成介电层82。可以使用聚合物来形成介电层82,可从与聚合物层72的材料相同的候选材料中选择该介电层。例如,介电层82可以包括聚酰亚胺、PBO、聚酰亚胺、BCB等。开口84还可形成在介电层82中以暴露RDL 80。通过光刻工艺可实施开口84的形成。可以使用类似于聚合物层72的烘焙的工艺来烘焙聚合物层82,并且因此聚合物层82的侧壁的倾斜角α2可以在与聚合物层72的倾斜角α1相同的范围内。
图21示RDL 86的形成,RDL 86电连接至RDL 80。RDL 86的形成可采用与形成RDL80的方法和材料类似的方法和材料。由于RDL 86和80都位于器件管芯12的前侧上,所以RDL86和80还称为前侧RDL。
如图22所示,形成额外的介电层88以覆盖RDL 86和介电层82,该介电层88可以是聚合物层。介电层88可以选自用于形成介电层72和82的相同的候选聚合物。然后,开口90形成在介电层88中,以暴露RDL 86的金属焊盘部分。根据一些实施例,在形成介电层88之前,一个或多个介电层和RDL层可以形成在RDL 86上方并且电连接至RDL 86,并且材料和方法可以类似于下面的介电层和RDL的材料和方法。
图23示出根据一些示例性实施例的凸块下金属(UBM)92和电连接件94的形成。UBM92的形成可包括沉积和图案化。电连接件94的形成可包括将焊球放置在UBM 92的暴露部分上,然后回流该焊球。在可选的实施例中,电连接件94的形成包括实施镀步骤以在RDL 86上方形成焊料区并且然后回流焊料区。电连接件94还可以包括金属柱或者包括金属柱和焊帽,其还可以通过镀来形成。贯穿说明书,包括器件管芯12、贯通孔60、密封材料70和对应的RDL和介电层的组合结构将称为封装件100,封装件100可以是具有圆形顶视图形状的复合晶圆。
接下来,封装件100从载体54去接合。相应步骤在图27所示的工艺流程中示出为步骤322。还从封装件100清除释放层56。通过将诸如UV光或激光的光投射在释放层56上以分解释放层56来实施去接合。
在去接合中,将胶带(未示出)附接至介电层88和电连接件94上。在后续步骤中,从封装件100去除载体54和释放层56。实施管芯锯切步骤以将封装件100锯切成多个封装件,每个封装件均包括器件管芯12和贯通孔60。所得的封装件中的一个示出为图24中的封装件102。
图24示出封装件102与另一封装件200的接合。相应步骤在图27所示的工艺流程中示出为步骤324。根据本发明的一些实施例,通过焊料区98实施接合。根据一些实施例,封装件200包括器件管芯202,该器件管芯可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。在一些示例性实施例中,存储器管芯还可以接合至封装衬底204。
本发明的实施例具有一些有益特征。通过使金属柱的侧壁的底部具有较小的倾斜角来减小在后续的平坦化中引起的应力,并且减少或消除分层。
根据本发明的一些实施例,一种方法包括形成第一聚合物层以覆盖晶圆的金属焊盘,并且图案化第一聚合物层以形成第一开口。第一聚合物层的暴露于第一开口的第一侧壁具有第一倾斜角,其中第一侧壁与金属焊盘接触。该方法还包括在第一开口中形成金属柱,形成环绕并覆盖金属柱的介电层,锯切晶圆以产生器件管芯,将器件管芯密封在密封材料中,实施平坦化以暴露金属柱,在密封材料和器件管芯上方形成第二聚合物层,并且图案化第二聚合物层以形成第二开口。通过第二开口暴露金属柱。暴露于第二开口的第二聚合物层的第二侧壁具有比第一倾斜角更大的第二倾斜角。
根据本发明的一些实施例,一种方法包括形成第一聚合物层以覆盖晶圆的金属焊盘,并且图案化第一聚合物层以形成第一开口,通过第一开口暴露金属焊盘。该方法还包括在第一温度处烘焙晶圆,在第一开口中形成金属柱,形成环绕并覆盖金属柱的介电层,锯切晶圆以产生器件管芯,将器件管芯密封在密封材料中,实施平坦化以暴露金属柱,在密封材料和器件管芯上方形成第二聚合物层,并且图案化第二聚合物层以形成第二开口,通过第二开口暴露金属柱。在低于第一温度的第二温度处烘焙第二聚合物层。再分布线形成以具有填充第二开口的部分。
根据本发明的一些实施例,封装件包括器件管芯,器件管芯包括金属焊盘、覆盖金属焊盘的边缘部分的第一聚合物层以及延伸到第一聚合物层内以接触第一聚合物层的第一侧壁的金属柱。第一聚合物层的第一侧壁具有第一倾斜角。该封装件还包括密封器件管芯的密封材料。金属柱的顶面与密封材料的顶面共面。第二聚合物层位于密封材料和器件管芯上方。再分布线具有延伸到第二聚合物层内以接触第二聚合物层的第二侧壁的部分。第二侧壁具有大于第一倾斜角的第二倾斜角。
根据本发明的一个实施例,提供了一种形成封装件的方法,包括:形成第一聚合物层以覆盖晶圆的金属焊盘;图案化所述第一聚合物层以形成第一开口,通过所述第一开口暴露所述金属焊盘,其中,所述第一聚合物层的从所述第一开口暴露的第一侧壁限定投影于所述金属焊盘的上表面上方的第一倾斜角;在所述第一开口中形成金属柱;形成环绕并覆盖所述金属柱的介电层;锯切所述晶圆以产生器件管芯;将所述器件管芯密封在密封材料中;实施平坦化以暴露所述金属柱;在所述密封材料和所述器件管芯上方形成第二聚合物层;以及图案化所述第二聚合物层以形成第二开口,其中,通过所述第二开口暴露所述金属柱,其中,所述第二聚合物层的暴露于所述第二开口的第二侧壁具有大于所述第一倾斜角的第二倾斜角。
在上述方法中,图案化所述第一聚合物层包括曝光和显影所述第一聚合物层以及在第一温度处烘焙所述第一聚合物层,以及图案化所述第二聚合物层包括曝光和显影所述第二聚合物层以及在低于所述第一温度的第二温度处烘焙所述第二聚合物层。
在上述方法中,选择所述第一温度以导致所述第一倾斜角在15度和45度之间,以及选择所述第二温度以导致所述第二倾斜角在70度和90度之间。
在上述方法中,所述第一温度比所述第二温度高一差值,所述差值高于120度。
在上述方法中,其中,所述第一聚合物层的所述第一侧壁的下部是弯曲的并且具有半径,并且所述金属柱的在所述第一聚合物层中的部分具有厚度,并且其中,所述半径与所述厚度的比率大于0.2。
在上述方法中,还包括形成金属桩,其中,将所述金属桩密封在所述密封材料中,并且所述金属桩具有沙漏轮廓。
在上述方法中,还包括:在所述金属柱上方并且接触所述金属柱镀焊料层;以及在所述平坦化中去除所述焊料层,其中,在镀所述焊料层和去除所述焊料层之间,不回流所述焊料层。
根据本发明的另一实施例,还提供了一种形成封装件的方法,包括:形成第一聚合物层以覆盖晶圆的金属焊盘;图案化所述第一聚合物层以形成第一开口,通过所述第一开口暴露所述金属焊盘;在第一温度处烘焙所述晶圆;在所述第一开口中形成金属柱;形成环绕并覆盖所述金属柱的介电层;锯切所述晶圆以产生器件管芯;将所述器件管芯密封在密封材料中;实施平坦化以暴露所述金属柱;在所述密封材料和所述器件管芯上方形成第二聚合物层;图案化所述第二聚合物层以形成第二开口,其中,通过所述第二开口暴露所述金属柱;在低于所述第一温度的第二温度处烘焙所述第二聚合物层;以及形成再分布线,所述再分布线具有填充所述第二开口的部分。
在上述方法中,所述第一聚合物层的暴露于所述第一开口的第一侧壁具有邻近于所述第一侧壁和所述金属焊盘接触的位置的第一倾斜角,以及所述第二聚合物层的暴露于所述第二开口的第二侧壁具有大于所述第一倾斜角的第二倾斜角。
在上述方法中,选择所述第一温度以导致所述第一倾斜角在15度和45度之间,并且选择所述第二温度以导致所述第二倾斜角在70度和90度之间。
在上述方法中,在所述第一温度处烘焙所述晶圆之后,所述第一聚合物层的所述第一侧壁的下部是弯曲的并且具有半径,以及所述金属柱的在所述第一聚合物层中的部分具有厚度,以及所述半径与所述厚度的比率大于0.2。
在上述方法中,图案化所述第一聚合物层包括在烘焙所述第一聚合物之前,曝光和显影所述第一聚合物层,并且图案化所述第二聚合物层包括在烘焙所述第二聚合物层之前,曝光和显影所述第二聚合物层。
在上述方法中,所述第一温度比所述第二温度高一差值,所述差值在120度和160度之间的范围内。
在上述方法中,所述第一聚合物层和所述第二聚合物层由相同的聚合物材料形成。
在上述方法中,所述第一聚合物层和所述第二聚合物层由不同的聚合物材料形成。
根据本发明的又一实施例,还提供了一种封装件,包括:器件管芯,包括:金属焊盘;第一聚合物层,覆盖所述金属焊盘的边缘部分;以及金属柱,延伸到所述第一聚合物层内以接触所述第一聚合物层的第一侧壁,其中,所述第一聚合物层的所述第一侧壁限定相对于所述金属焊盘的上表面的第一倾斜角;密封材料,密封所述器件管芯,其中,所述金属柱的顶面与所述密封材料的顶面共面;第二聚合物层,位于所述密封材料和所述器件管芯上方;以及再分布线,具有延伸到所述第二聚合物层内以接触所述第二聚合物层的第二侧壁的部分,其中,所述第二侧壁具有大于所述第一倾斜角的第二倾斜角。
在上述封装件中,所述第一倾斜角在15度和45度之间的范围内。
在上述封装件中,所述第一聚合物层的所述第一侧壁的下部是弯曲的并且具有半径,以及所述金属柱的在所述第一聚合物层中的部分具有厚度,其中,所述半径与所述厚度的比率大于0.2。
在上述封装件中,所述第一聚合物层和所述第二聚合物层由相同的聚合物材料形成。
在上述封装件中,所述第一聚合物层和所述第二聚合物层由不同的聚合物材料形成。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法,包括:
形成第一聚合物层以覆盖晶圆的金属焊盘;
图案化所述第一聚合物层以形成第一开口,通过所述第一开口暴露所述金属焊盘,其中,所述第一聚合物层的从所述第一开口暴露的第一侧壁限定投影于所述金属焊盘的上表面上方的第一倾斜角,并且所述第一聚合物层的所述第一侧壁的下部是弯曲的;
在所述第一开口中形成金属柱;
形成环绕并覆盖所述金属柱的介电层;
锯切所述晶圆以产生器件管芯;
将所述器件管芯密封在密封材料中;
实施平坦化以暴露所述金属柱;
在所述密封材料和所述器件管芯上方形成第二聚合物层;以及
图案化所述第二聚合物层以形成第二开口,其中,通过所述第二开口暴露所述金属柱,其中,所述第二聚合物层的暴露于所述第二开口的第二侧壁具有大于所述第一倾斜角的第二倾斜角。
2.根据权利要求1所述的方法,其中,图案化所述第一聚合物层包括曝光和显影所述第一聚合物层以及在第一温度处烘焙所述第一聚合物层,以及图案化所述第二聚合物层包括曝光和显影所述第二聚合物层以及在低于所述第一温度的第二温度处烘焙所述第二聚合物层。
3.根据权利要求2所述的方法,其中,选择所述第一温度以导致所述第一倾斜角在15度和45度之间,以及选择所述第二温度以导致所述第二倾斜角在70度和90度之间。
4.根据权利要求2所述的方法,其中,所述第一温度比所述第二温度高一差值,所述差值高于120度。
5.根据权利要求1所述的方法,其中,所述第一聚合物层的所述第一侧壁的下部是弯曲的并且具有半径,并且所述金属柱的在所述第一聚合物层中的部分具有厚度,并且其中,所述半径与所述厚度的比率大于0.2。
6.根据权利要求1所述的方法,还包括形成金属桩,其中,将所述金属桩密封在所述密封材料中,并且所述金属桩具有沙漏轮廓。
7.根据权利要求1所述的方法,还包括:
在所述金属柱上方并且接触所述金属柱镀焊料层;以及
在所述平坦化中去除所述焊料层,其中,在镀所述焊料层和去除所述焊料层之间,不回流所述焊料层。
8.一种形成封装件的方法,包括:
形成第一聚合物层以覆盖晶圆的金属焊盘;
图案化所述第一聚合物层以形成第一开口,通过所述第一开口暴露所述金属焊盘;
在第一温度处烘焙所述晶圆;
在所述第一开口中形成金属柱;
形成环绕并覆盖所述金属柱的介电层;
锯切所述晶圆以产生器件管芯;
将所述器件管芯密封在密封材料中;
实施平坦化以暴露所述金属柱;
在所述密封材料和所述器件管芯上方形成第二聚合物层;
图案化所述第二聚合物层以形成第二开口,其中,通过所述第二开口暴露所述金属柱;
在低于所述第一温度的第二温度处烘焙所述第二聚合物层;以及
形成再分布线,所述再分布线具有填充所述第二开口的部分。
9.根据权利要求8所述的方法,其中,所述第一聚合物层的暴露于所述第一开口的第一侧壁具有邻近于所述第一侧壁和所述金属焊盘接触的位置的第一倾斜角,以及所述第二聚合物层的暴露于所述第二开口的第二侧壁具有大于所述第一倾斜角的第二倾斜角。
10.根据权利要求9所述的方法,其中,选择所述第一温度以导致所述第一倾斜角在15度和45度之间,并且选择所述第二温度以导致所述第二倾斜角在70度和90度之间。
11.根据权利要求9所述的方法,其中,在所述第一温度处烘焙所述晶圆之后,所述第一聚合物层的所述第一侧壁的下部是弯曲的并且具有半径,以及所述金属柱的在所述第一聚合物层中的部分具有厚度,以及所述半径与所述厚度的比率大于0.2。
12.根据权利要求8所述的方法,其中,图案化所述第一聚合物层包括在烘焙所述第一聚合物之前,曝光和显影所述第一聚合物层,并且图案化所述第二聚合物层包括在烘焙所述第二聚合物层之前,曝光和显影所述第二聚合物层。
13.根据权利要求8所述的方法,其中,所述第一温度比所述第二温度高一差值,所述差值在120度和160度之间的范围内。
14.根据权利要求8所述的方法,其中,所述第一聚合物层和所述第二聚合物层由相同的聚合物材料形成。
15.根据权利要求8所述的方法,其中,所述第一聚合物层和所述第二聚合物层由不同的聚合物材料形成。
16.一种封装件,包括:
器件管芯,包括:
金属焊盘;
第一聚合物层,覆盖所述金属焊盘的边缘部分;以及
金属柱,延伸到所述第一聚合物层内以接触所述第一聚合物层的第一侧壁,其中,所述第一聚合物层的所述第一侧壁限定相对于所述金属焊盘的上表面的第一倾斜角,并且所述第一聚合物层的所述第一侧壁的下部是弯曲的;
密封材料,密封所述器件管芯,其中,所述金属柱的顶面与所述密封材料的顶面共面;
第二聚合物层,位于所述密封材料和所述器件管芯上方;以及
再分布线,具有延伸到所述第二聚合物层内以接触所述第二聚合物层的第二侧壁的部分,其中,所述第二侧壁具有大于所述第一倾斜角的第二倾斜角。
17.根据权利要求16所述的封装件,其中,所述第一倾斜角在15度和45度之间的范围内。
18.根据权利要求16所述的封装件,其中,所述第一聚合物层的所述第一侧壁的下部是弯曲的并且具有半径,以及所述金属柱的在所述第一聚合物层中的部分具有厚度,其中,所述半径与所述厚度的比率大于0.2。
19.根据权利要求16所述的封装件,其中,所述第一聚合物层和所述第二聚合物层由相同的聚合物材料形成。
20.根据权利要求16所述的封装件,其中,所述第一聚合物层和所述第二聚合物层由不同的聚合物材料形成。
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Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9852998B2 (en) * 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10861773B2 (en) * 2017-08-30 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
US11114315B2 (en) * 2017-11-29 2021-09-07 Pep Innovation Pte. Ltd. Chip packaging method and package structure
US11232957B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and package structure
US11233028B2 (en) 2017-11-29 2022-01-25 Pep Inovation Pte. Ltd. Chip packaging method and chip structure
US11610855B2 (en) 2017-11-29 2023-03-21 Pep Innovation Pte. Ltd. Chip packaging method and package structure
TWI645527B (zh) * 2018-03-06 2018-12-21 矽品精密工業股份有限公司 電子封裝件及其製法
US10510645B2 (en) 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Planarizing RDLs in RDL-first processes through CMP process
JP2021529459A (ja) 2018-07-06 2021-10-28 バタフライ ネットワーク,インコーポレイテッド 超音波オンチップをパッケージングする方法及び装置
TWI693686B (zh) * 2018-08-09 2020-05-11 新唐科技股份有限公司 半導體封裝結構及其形成方法
KR102138012B1 (ko) * 2018-08-28 2020-07-27 삼성전자주식회사 팬-아웃 반도체 패키지
KR102477356B1 (ko) * 2018-09-11 2022-12-15 삼성전자주식회사 반도체 패키지
KR102551747B1 (ko) 2018-09-13 2023-07-06 삼성전자주식회사 반도체 패키지
US11024593B2 (en) * 2018-09-28 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Metal bumps and method forming same
US10522488B1 (en) * 2018-10-31 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning polymer layer to reduce stress
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR102621100B1 (ko) * 2019-05-16 2024-01-04 삼성전자주식회사 반도체 패키지
US11322465B2 (en) * 2019-08-26 2022-05-03 Cirrus Logic, Inc. Metal layer patterning for minimizing mechanical stress in integrated circuit packages
US11316086B2 (en) * 2020-07-10 2022-04-26 X Display Company Technology Limited Printed structures with electrical contact having reflowable polymer core
KR20220009218A (ko) * 2020-07-15 2022-01-24 삼성전자주식회사 반도체 패키지, 및 이를 가지는 패키지 온 패키지
TWI809951B (zh) * 2022-05-10 2023-07-21 南亞科技股份有限公司 具有多重碳濃度介電層的半導體元件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856279A (zh) * 2011-06-28 2013-01-02 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN104576584A (zh) * 2013-10-18 2015-04-29 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN104658988A (zh) * 2013-11-18 2015-05-27 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105428329A (zh) * 2014-09-15 2016-03-23 台湾积体电路制造股份有限公司 具有ubm的封装件和形成方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696766B2 (en) * 2007-01-31 2010-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra-fine pitch probe card structure
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8426985B2 (en) * 2008-09-04 2013-04-23 Hitachi Chemical Company, Ltd. Positive-type photosensitive resin composition, method for producing resist pattern, and electronic component
US9985150B2 (en) 2010-04-07 2018-05-29 Shimadzu Corporation Radiation detector and method of manufacturing the same
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8569167B2 (en) * 2011-03-29 2013-10-29 Micron Technology, Inc. Methods for forming a semiconductor structure
US9000584B2 (en) * 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9437564B2 (en) * 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US20150228675A1 (en) * 2012-09-21 2015-08-13 Sharp Kabushiki Kaisha Liquid crystal display
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9728517B2 (en) * 2013-12-17 2017-08-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9595482B2 (en) 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102856279A (zh) * 2011-06-28 2013-01-02 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN104576584A (zh) * 2013-10-18 2015-04-29 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN104658988A (zh) * 2013-11-18 2015-05-27 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105428329A (zh) * 2014-09-15 2016-03-23 台湾积体电路制造股份有限公司 具有ubm的封装件和形成方法

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