CN105390455A - 用于晶圆级封装件的互连结构及其形成方法 - Google Patents

用于晶圆级封装件的互连结构及其形成方法 Download PDF

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Publication number
CN105390455A
CN105390455A CN201510511079.9A CN201510511079A CN105390455A CN 105390455 A CN105390455 A CN 105390455A CN 201510511079 A CN201510511079 A CN 201510511079A CN 105390455 A CN105390455 A CN 105390455A
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tube core
polymeric layer
moulding compound
face
flat forms
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CN201510511079.9A
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CN105390455B (zh
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余振华
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US14/464,487 external-priority patent/US9484285B2/en
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Abstract

一种器件封装件包括:多个管芯;模塑料,沿着多个管芯的侧壁延伸;和聚合物层,位于模塑料上方并且接触模塑料。模塑料包括非平坦的顶面,并且聚合物层的顶面的总厚度变化(TTV)小于模塑料的非平坦的顶面的TTV。该器件封装件还包括位于聚合物层上的导电部件,其中,导电部件电连接至多个管芯中的至少一个。本发明实施例涉及用于晶圆级封装件的互连结构及其形成方法。

Description

用于晶圆级封装件的互连结构及其形成方法
相关申请的交叉引用
本申请是2014年8月20日提交的标题为“InterconnectStructuresforWaferLevelPackageandMethodsofFormingSame”的美国专利申请第14/464,487号的部分继续申请,其全部内容结合于此作为参考。
技术领域
本发明实施例涉及用于晶圆级封装件的互连结构及其形成方法。
背景技术
在诸如晶圆级封装(WLP)的传统的封装技术的方面中,再分布层(RDL)可以形成在管芯上方并且电连接至管芯中的有源器件。然后,可以形成诸如凸块下金属化层(UBM)上的焊料球的外部输入/输出(I/O)焊盘,以通过RDL电连接至管芯。这样的封装技术的有利特征在于,有可能形成扇出封装件。因此,与管芯相比,管芯上的I/O焊盘可以再分布至更大的面积,并且因此,可以增加封装在管芯的表面上的I/O焊盘的数量。
在这样的封装技术中,可以在管芯周围形成模塑料,以提供用于支撑扇出互连结构的表面面积。例如,RDL通常包括形成在管芯和模塑料上方的一个或多个聚合物层。导电部件(例如,导电线和/或通孔)形成在聚合物层中,并且将管芯上的I/O焊盘电连接至RDL上方的外部I/O焊盘。外部I/O焊盘可以设置在管芯和模塑料上方。
发明内容
根据本发明的一个实施例,提供了一种器件封装件,包括:多个管芯;模塑料,沿着所述多个管芯的侧壁延伸,其中,所述模塑料包括非平坦的顶面;聚合物层,位于所述模塑料上方并且接触所述模塑料,其中,所述聚合物层的顶面的总厚度变化(TTV)小于所述模塑料的非平坦的顶面的TTV;以及导电部件,位于所述聚合物层上,其中,所述导电部件电连接至所述多个管芯中的至少一个。
根据本发明的另一实施例,提供了一种器件封装件,包括:第一管芯;第二管芯,邻近所述第一管芯;模塑料,沿着所述第一管芯和所述第二管芯的侧壁延伸,其中,所述模塑料包括位于所述第一管芯与所述第二管芯之间的非平坦的顶面;聚合物层,位于所述模塑料上方并且接触所述模塑料,其中,所述聚合物层包括位于所述模塑料的非平坦的顶面上方的非平坦的顶面,并且其中,所述聚合物层的非平坦的顶面具有小于约5微米(μm)的总厚度变化(TTV);以及导电线,位于所述聚合物层上,其中,所述导电线的至少一部分接触所述聚合物层的非平坦的顶面,并且其中,所述导电线电连接至所述第一管芯。
根据本发明的又一实施例,提供了一种用于形成器件封装件的方法,所述方法包括:在载体上设置多个管芯;在所述载体上方和在所述多个管芯周围形成模塑料,其中,当形成所述模塑料时,所述多个管芯由膜层覆盖,并且其中,所述模塑料包括位于所述多个管芯的相邻管芯之间的非平坦的顶面;在所述多个管芯上方形成聚合物层并且所述聚合物层接触所述模塑料的非平坦的顶面,其中,形成所述聚合物层包括平坦化工艺,以使得所述聚合物层的顶面的总厚度变化(TTV)小于所述模塑料的非平坦的顶面的TTV;以及在所述聚合物层上形成导电线。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,各种部件没有按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1A至图1D示出了根据一些实施例的器件封装件的截面图和顶视图。
图2至图13示出了根据一些实施例的制造器件封装件的中间步骤的截面图。
图14至图20示出了根据一些其他实施例的制造器件封装件的中间步骤的截面图。
图21A和图21B示出了根据一些可选实施例的器件封装件的截面图。
图22示出了根据一些实施例的用于形成器件封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的许多不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例,并且也可以包括在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
另外,为便于描述,本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语,以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外,空间关系术语旨在包括在使用或操作中的器件的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在本文中使用的空间关系描述符可以同样作相应的解释。
在具体地描述所示出的实施例之前,通常描述本发明公开的实施例的特定优势特征和各方面。一般而言,公开了一种用于将聚合物膜涂覆(如,用于再分布层(RDL)结构)在模塑料表面上的新的结构和方法,这简化了封装件加工并降低了工艺成本。
下文描述的是一种用于形成扇出封装件的方法和对应的结构。在一些实施例中,使用传递模塑工艺在管芯周围形成模塑料。在形成模塑料之后,仍然可以暴露管芯的顶面。因此,不必对模塑料执行研磨工艺(或其他回蚀刻技术)以暴露管芯。由于传递模塑工艺,所以模塑料的顶面可以具有约5μm至约10μm的总厚度变化(TTV,如,顶面的最高点和最低点之间的距离)。例如,聚合物层(例如,第一RDL)形成在模塑料和管芯上方并且使用压力夹紧/层压工艺来平坦化该聚合物层。平坦化之后的聚合物层的总厚度变化可以相对较小(例如,小于约5μm),从而允许附加RDL层可靠地形成在聚合物层上方。因此,可以使用传递模塑和层压工艺在管芯和模塑料上方形成扇出RDL结构,这可以降低制造封装件的总体成本。
图1A示出了根据各个实施例的扇出器件封装件100的截面图。封装件100包括管芯102、设置在管芯周围的模塑料104、形成在管芯102和模塑料104上方的RDL106(例如,具有导电部件120)。管芯102可以是半导体管芯,并且可以是任何类型的集成电路,诸如处理器、逻辑电路、存储器、模拟电路、数字电路、混合信号等。管芯102可以包括衬底、有源器件和互连结构(没有单独示出)。例如,衬底可以包括掺杂或未掺杂的块状硅,或绝缘体上半导体(SOI)衬底的有源层。通常,SOI衬底包括形成在绝缘层上的诸如硅的半导体材料的层。例如,绝缘层可以是掩埋氧化物(BOX)层或氧化硅层。在诸如硅或玻璃衬底的衬底上提供绝缘层。可选地,衬底可以包括另一元素半导体,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。也可以使用诸如多层或梯度衬底的其他衬底。
可以在衬底的顶面处形成有源器件,诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。可以在有源器件和衬底上方形成互连结构。互连结构可以包括层间介电层(ILD)和/或金属间介电层(IMD),层间介电层和/或金属间介电层含有使用任何合适的方法形成的导电部件(例如,包括铜、铝、钨、它们的组合等的导电线和通孔)。ILD和IMD可以包括设置在这样的导电部件之间的低k介电材料,例如,低k介电材料具有低于约4.0或甚至2.0的k值。例如,在一些实施例中,ILD和IMD可以由磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、碳化硅材料、它们的化合物、它们的复合物、它们的组合等制成,并且可以通过诸如旋涂、化学汽相沉积(CVD)和等离子体增强的CVD(PECVD)的任何合适的方法形成。互连结构电连接各个有源器件,以在管芯102内形成功能电路。通过这样的电路提供的功能可以包括存储器结构、处理结构、传感器、放大器、功率分布、输入/输出电路等。本领域普通技术人员将理解,提供上述实例仅用于示出的目的,以进一步解释本发明的应用并且不意欲以任何方式限制本发明。对于给定的应用可以适当地使用其他电路。
可以在互连结构上方形成输入/输出(I/O)和钝化部件。例如,接触焊盘110可以形成在互连结构上方并且可以通过互连结构中的各种导电部件电连接至有源器件。接触焊盘110可以包括导电材料,诸如铝、铜等。此外,可以在互连结构和接触焊盘上方形成钝化层112。在一些实施例中,钝化层112可以由诸如氧化硅、氮化硅、未掺杂的硅酸盐玻璃、氮氧化硅的等非有机材料形成。也可使用其他合适的钝化材料。钝化层112的部分可以覆盖接触焊盘110的边缘部分。
诸如附加的钝化层、导电柱和/或凸块下金属化(UBM)层的附加的互连部件也可以任选地形成在接触焊盘110上方。例如,图1A的封装件100包括接触焊盘110上方的UBM层114。UBM层114可以延伸至钝化层112上方并且覆盖部分钝化层112。相比之下,图1B示出了封装件130,其中,省略了UBM层114。可以通过任何合适的方法形成管芯102的各个部件并且本文中不再进一步详细描述。此外,上文描述的管芯102的常见部件和配置仅仅是一个示例性实施例,并且管芯102可以包括任意数量的上述部件以及其他部件的任何组合。
模塑料104设置在管芯102周围。例如,在模塑料104/管芯102(未示出)的顶视图中,模塑料104可以环绕管芯102。如将在随后的段落中更详细地描述,可以使用传递模塑工艺形成模塑料104,该模塑料不覆盖管芯102的顶面。作为传递模塑工艺的结果,模塑料104的顶面可能不基本齐平。例如,模塑料104可以包括背对管芯102的侧壁的倾斜的凹进的表面104’。虽然图1A将倾斜表面104’示出为具有基本线性轮廓,但是在其他实施例中(例如,见图1C),表面104’可能是非线性的(例如,凹形或凸形)。模塑料104的顶面的其他部分可以包括角度和高度的类似的变化。在各个实施例中,模塑料104的顶面的TTVT1可以为约5μm至约30μm。
可以在管芯102和模塑料104上方形成一个或多个RDL106。RDL106可以横向延伸越过管芯102的边缘,以提供扇出互连结构。RDL106可以包括最底部聚合物层108,该最底部聚合物层108的底面接触管芯102和模塑料104的顶面。如随后将更详细的解释,可以使用诸如真空层压、热压层压等的层压工艺形成聚合物层108。在一些实施例中,聚合物层108可以包括聚酰亚胺、聚苯并恶唑(PBO)、环氧树脂、环烯烃聚合物、底部填充膜、模制的底部填充膜或任何其他合适的层压膜材料。聚合物层108可以或可以不包括任何填充材料,诸如二氧化硅填料、玻璃填料、氧化铝、氧化硅等。此外,由于层压工艺期间的压力夹紧和/或单独的压力夹紧工艺,所以聚合物层108的顶面可以基本齐平(或至少比模塑料104更齐平)。例如,聚合物层108的顶面的TTV可以小于模塑料的TTVT1,以提供用于形成RDL106的附加的部件的合适的表面。在实施例中,聚合物层108的TTV可以为约5μm或以下。相比之下,聚合物层108的底面可能不基本齐平。例如,聚合物层108的底面与模塑料104接触并且可以具有约5μm至约30μm的TTVT1。
RDL106还可以包括导电部件120(例如,导电线120A和导电通孔120B)和附加的聚合物层122。导电线120A可以形成在聚合物层108上方,并且导电通孔120B可以延伸穿过聚合物层108并且电连接至管芯102的接触焊盘110。聚合物层122也可以形成在聚合物层108上方。在各个实施例中,聚合物层122可以是类似于聚合物层108的层压膜材料,可以使用类似的层压工艺形成该聚合物层122。可选地,聚合物层122可以包括其他聚合物材料,例如包括使用诸如旋涂技术等任何合适的手段形成的聚酰亚胺(PI)、PBO、苯并环丁烯(BCB)、环氧树脂、有机硅、丙烯酸酯、纳米填充的苯酚树脂、硅氧烷、含氟聚合物、环状烯烃聚合物、聚降冰片烯等。RDL106还可以包括基于封装件设计的位于聚合物层122和导电部件120上方的任意数量的附加的聚合物层(未示出),该附加的聚合物层中设置有导电部件。
诸如外部连接件126的附加的封装部件可以设置在RDL106上方。连接件126可以是设置在金属下金属化层(UBM)124上的球栅阵列(BGA)球、可控塌陷芯片连接件(C4)凸块等,金属下金属化层(UBM)可以形成在RDL106上方。可以通过RDL106将连接件126电连接至管芯102。连接件126可以用于将封装件100电连接至其他封装组件,诸如另一器件管芯、内插器(interposer)、封装衬底、印刷电路板、主板等。
图1C示出了根据实施例的具有多个管芯的器件封装件150。图1D示出了封装件150中的导电线120A和聚合物层108的对应的顶视图。图1C提供的截面图是沿着图1D中的贯穿线(acrossline)1C-1C截取的。在图1D中通过虚线示出管芯102的位置以便于参考。
封装件150包括与封装件100或130类似的部件,其中,相似的参考标号代表相似的元件。如图所示,封装件150包括通过间隔S1间隔开的至少两个管芯102。模塑料104密封和环绕管芯102,模塑料104的一部分设置在管芯102之间。如上所述,由于用于形成模塑料104的传递模塑工艺,所以模塑料104的顶面可能不基本齐平。在一些实施例中,模塑料104的在管芯102之间的顶面(例如,表面104”)可以具有凹形轮廓,并且表面104”可以包括位于管芯102之间的凹槽。表面104”的TTV可以与管芯102之间的间隔S1的尺寸相关。例如,随着间隔S1增大,表面104”的对应的TTV也增大。在一些实施例中,由于管芯102之间的间隔,所以表面104”的TTV也可以相对较大。例如,在实施例中,表面104”的TTV可以约大于5μm或者甚至更大。
聚合物层108形成在管芯102和模塑料104上方。聚合物层108可以包括设置在管芯102之间并且接触模塑料104(例如,模塑料104的表面104”)的部分。在各个实施例中,聚合物层108的形成包括:甚至是在模塑料104的TTV相对较高的区域中减小聚合物层108的TTV的平坦化工艺(例如,压力夹紧/层压)。例如,在模塑料104的凹形表面104”上形成的聚合物层108的非平坦表面108’可以具有相对较小的TTVT2(例如,低于凹形表面104”的TTV)。
此外,因为表面108’设置在凹形表面104”上,所以表面108’的TTVT2也可以与管芯102之间的间隔S1的尺寸相关。例如,随着间隔S1增大,TTVT2也增大。在各个示例性封装件中,即使当间隔S1较大时,TTVT2也可以相对较小。例如,在实施例中,当间隔S1小于3000μm时,TTVT2可以小于约15μm。在实施例中,当间隔S1小于约500μm时,TTVT2可能小于约10μm。在实施例中,当间隔S1小于约100μm时,TTVT2可以小于约5μm。
导电线120A形成在聚合物层108上,并且导电线120A通过导电通孔120B电连接至管芯102,导电通孔120B延伸穿过聚合物层108。例如,导电线120A可以具有约5μm的厚度T3。在实施例中,导电线120A的至少一部分的顶面也可以是非平坦的(例如,凹形)。已经观察到,通过将管芯间隔S1和聚合物层108的TTVT2之间的关系保持在上述范围内,精细间隔的导电线(例如,导电线120A)可以可靠地形成在聚合物层108上(包括管芯102之间的表面108’上)。例如,当导电线形成在具有较大的TTV和/或跨越较大的管芯之间的距离的表面上时,可能需要相对较厚的导电线以确保足够的材料可用于覆盖表面中的尖端并且降低在所产生的线中形成缺陷(例如,间隙)的风险。通过将聚合物层108的TTV维持在上述范围内,即使是在模塑料104具有相对较大的TTV(例如,在管芯之间)处,都可以可靠地形成精细间距的导电线120A。在一些实施例中,导电线120A可以具有小于约10μm的宽度W1,并且相邻的导电线120A之间的间隔S2可以小于约10μm(例如,见图1D中的晶圆150的顶视图)。因此,多个管芯示例性封装件允许:即使是在管芯之间的区域中,精细间隔的导电线120A也可靠地直接形成在聚合物层上。
图2至图5示出了根据各个实施例的形成模塑料104和聚合物层108的各个中间阶段的截面图。参考图2,管芯102安装在载体200上。通常,载体200在随后的处理步骤期间对管芯102提供临时的机械和结构支撑。以这种方式,减少或防止对管芯102的损坏。例如,载体200可以包括玻璃、氧化硅、氧化铝等。在载体200上方沉积临时的粘合层202(例如,胶层、光热转换(LTHC)涂层、紫外(UV)膜等)。可以使用设置在管芯102的背侧上的粘合层202和/或附加的粘合层204(例如,管芯贴膜(DAF))将管芯202临时地附接至载体200。
例如,图3和图4示出了使用真空层压工艺在管芯120上方形成聚合物层108。首先参照图3,载体200(具有安装至载体的管芯102)设置在模制装置205的顶板和底板206之间。顶板和底板206可以包括用于提供结构支撑的合适的材料,诸如金属、陶瓷等。离型膜208可以设置在顶板206的底面上,并且聚合物层108可以设置在离型膜208的底面上。在一些实施例中,离型膜208包括聚对苯二甲酸乙二醇酯(PET)、聚四氟乙烯、橡胶、聚乙烯萘二甲酸乙二醇酯(PEN)、聚醚酰亚胺(PEI)、硅橡胶、聚亚苯基硫化物(PPS)、含有预浸料的玻璃纤维、或者可以临时地支撑聚合物层108并且在形成各个部件之后从聚合物层108去除的任何其他材料。
聚合物层108可以设置在离型膜208的底面上(例如,面向管芯102)。聚合物层108可以包括具有或不具有填充材料的层压膜材料,诸如聚酰亚胺、PBO、环氧树脂、底部填充膜、模制的底部填充膜等。可以通过相对较弱的键将聚合物层108粘附至离型膜208的底面。例如,在将聚合物层108放置在管芯102上之前,聚合物层可以未被固化或仅部分被固化。随后,例如,如箭头210所示,可以移动顶板和/或底板206以使聚合物层108的底面接触管芯102的顶面。
图4示出了在将聚合物层108设置在管芯102的顶面上之后的模制装置205。聚合物层108可以覆盖管芯102的顶面(例如,覆盖接触焊盘110和钝化层112)。聚合物层108可能未广泛地延伸越过管芯102的顶面。例如,间隙207可以保持设置在聚合物层108下方的管芯102之间。此外,在聚合物层108下方缺少任何的支撑材料都可能导致聚合物层108的底面基本不齐平。例如,聚合物层108的底面(标注为108’)可以具有约5μm至约10μm的TTVT1。TTVT1可以是管芯102的间隔(例如,间距P1)和间隙207的对应的横向尺寸的变量。例如,在间隔P1为约100μm至约200μm的实施例中,TTVT1可以更小(例如,约10μm)。作为另一个实例,在间隔P1为约1mm至约2mm的实施例中,TTVT1可以更大(例如,约20μm)。
在将聚合物层108设置在管芯102上之后,可以执行固化工艺,以将聚合物层108粘附至管芯102的顶面。例如,在一些实施例中,可以在约25℃至约200℃的温度下并且在约30秒至约10分钟的时间段内对聚合物层108进行固化。可以根据聚合物层108的材料改变固化工艺。在各个实施例中,对聚合物层108施加充足的压力(例如,通过顶板和/或底板206),从而使得聚合物层108的顶面基本齐平或至少比模塑料104更齐平。虽然图4将聚合物层108示出为完全齐平,但是聚合物层108的顶面可以是非平坦的(例如,凹形),特别是在管芯102之间(例如,见图1C)。在实施例中,当管芯102之间的间隔小于约3000μm时,聚合物层108的TTV可以小于约5μm。在当管芯102之间的间隔小于约500μm时的实施例中,聚合物层108的TTV可以小于约3μm。在当管芯102之间的间隔小于约100μm时的实施例中,聚合物层108的TTV可以小于约2μm。如上所述,已经观察到,通过将聚合物层108的TTV相对于管芯间隔维持在这些范围内,可以在聚合物层108上可靠地形成相对细间距的导电线。
接下来,在图5中,例如,使用传递模塑工艺在间隙207中形成模塑料104。在模塑工艺期间,聚合物层108可以用作覆盖管芯102的顶面(例如,覆盖接触焊盘110和钝化层112)的膜层。模塑料104包括合适的材料,诸如环氧树脂、模制底部填充物等。在一些实施例中,传递模塑工艺包括以液体形式在管芯102之间(例如,在间隙207中)分配模塑料。接下来,可以执行固化工艺以固化模塑料104。模塑料104的顶面可以接触聚合物层108的底面,并且因此,模塑料104的顶面可以具有与聚合物层108的底面类似的轮廓。例如,模塑料104的顶面可以包括背对管芯102的侧壁的倾斜的凹进的表面104’。模塑料104的顶面的其他部分可以包括角度和/或高度的类似变化。在各个实施例中,模塑料104的顶面(和聚合物层108的对应的底面)的TTVT1可以为约5μm至约30μm。因此,可以使用层压和传递模塑工艺在封装件100中形成模塑料104和聚合物层108。
图2至图5示出了根据一些实施例的在形成模塑料104之前聚合物层108的形成。在可选实施例中,可以采用形成封装件100中的各个元件的可选顺序。例如,图6至图8示出了在形成模塑料104之后形成聚合物层108。
在图6中,在形成聚合物层108之前,在管芯102之间和周围分配模塑料104。例如,管芯102(被载体200支撑)可以放置在模制装置205的底板206上,并且离型膜208(例如,由顶板206支撑)可以用于在传递模塑期间覆盖管芯102的顶面。可以以液体形式在管芯102之间分配模塑料104,然后固化模塑料。作为传递模塑工艺的结果,模塑料104的顶面可以不基本齐平(例如,具有约5μm至约30μm的TTVT1),并且例如,可以具有倾斜的和/或凹进的部分104’。TTVT1可以根据管芯102的间隔P1而改变。
接下来,如图7所示,从管芯102和载体200去除顶板和底板206以及离型膜208。例如,离型膜208可以包括与模塑料104具有相对较弱的粘合键的材料,并且可以使用机械力去除离型膜208(和附接的顶板206)。例如,离型膜208可以包括聚对苯二甲酸乙二醇酯(PET)、聚四氟乙烯、橡胶、聚萘二甲酸乙二醇酯(PEN)、聚醚酰亚胺(PEI)、硅橡胶、聚亚苯基硫化物(PPS)、含有预浸料的玻璃纤维等。由于离型膜208的放置,所以模塑料104可以形成在管芯102周围而不覆盖管芯102的顶面。因此,不需要执行附加的工艺(例如,研磨)来暴露管芯102的部件(例如,接触焊盘110),从而节约了工艺成本。
在图8中,使用合适的层压工艺在管芯102和模塑料104上方形成聚合物层108。例如,管芯102(由载体200支撑)可以放置在顶板和底板206’之间。顶板和底板206’可以是与模制装置205的顶板/底板206相同的支撑件,或者顶板和底板206’可以是另一加工装置(例如,层压工具)的部件。顶板和底板206’可以用于将聚合物层108放置在管芯102和模塑料104上方。离型膜208’可以设置在聚合物层108和顶板206’之间。可选地,热辊层压工艺(例如,包括滚动装置,未示出)可以用于滚动管芯102和模塑料104上的聚合物层108。在另一实施例中,可以使用诸如化学汽相沉积等的任何合适的工艺形成聚合物层108。
在将聚合物层108设置在管芯102/模塑料104上之后,可以执行固化工艺,以将聚合物层108粘附至管芯102和模塑料104的顶面。例如,可以在约25℃至约200℃的温度下并且在约30秒至约10分钟的时间段内对聚合物层108进行固化。对聚合物层108应用诸如压力夹紧(例如,通过使用顶板和/或底板206’施加适量的压力)的平坦化工艺,以使聚合物层108的顶面齐平。例如,在压力夹紧之后,聚合物层108的顶面可以具有小于约3μm的TTV,这可以是用于在聚合物层108上方可靠地形成附加的RDL部件(例如,细间距的导电部件和/或附加的聚合物层)的合适的TTV。此外,在一些实施例中,高温膜(例如,高温PBO膜,未示出)可以任选地设置在聚合物层108上方、被固化并且被平坦化(例如,使用压力夹紧工艺)。当高温膜部分(例如,约10%至约80%)被固化时,可以对高温膜应用压力夹紧工艺。
在图9中,从顶板和底板206去除管芯102,管芯102上形成有模塑料104和聚合物层108。离型膜208可以使用机械力帮助去除顶板和底板206。例如,离型膜208可以包括与聚合物层108没有高粘附性的材料(例如,聚乙烯对苯二甲酸乙二醇酯(PET)、聚四氟乙烯、橡胶、聚萘二甲酸乙二醇酯(PEN)、聚醚酰亚胺(PEI)、硅橡胶、聚亚苯基硫化物(PPS)、含有预浸料的玻璃纤维等),并且可以在不损坏器件封装件的其他部件的情况下使用机械力去除离型膜208。接下来,例如,在图10中,使用诸如光刻、激光打孔和/或蚀刻技术的任何合适的工艺在聚合物层108中形成开口212,以暴露接触焊盘110。
图11和图12示出了诸如导电通孔120B和导电线120A的各种导电部件120的形成。首先,在图11中,用导电材料(例如,铜、银、金等)填充开口212,以形成导电通孔120B。开口212的填充可以包括首先沉积晶种层(未示出)和用导电材料电化学镀开口212。导电材料可以过填充开口212,并且可以执行化学机械抛光(CMP)或其他回蚀刻技术,以去除聚合物层108上方的导电材料的过量部分。导电通孔120B可以电连接至管芯102的接触焊盘110。
接下来,在图12中,在聚合物层108上方形成导电线120A(例如,包括铜、银、金等)。例如,导电线120A的形成可以包括:使用具有多个开口以限定导电线120A的形状的掩模层(未示出)来沉积晶种层(未示出),以及使用电化学镀工艺填充掩模层中的开口。然后可以去除掩模层。虽然导电线120A被示出为具有完全齐平的顶面,但是在一些实施例中,位于聚合物层108和模塑料104的非平坦部分上方的导电线120A的顶面可以是非平坦的(例如,凹形)(例如,见图1C)。在实施例中,导电线120A的宽度可以小于约10μm,并且相邻的导电线120A之间的间隔可以小于10μm。
可以在聚合物层108和导电部件120上方形成附加的部件。例如,图13示出了在聚合物层108和导电部件120上方形成另一聚合物层122。可以使用诸如层压、旋涂工艺等的任何合适的工艺形成聚合物层122。因此,在管芯102和模塑料104上方形成RDL106。RDL106的聚合物层和导电部件的数量不限于图13所示出的实施例。例如,RDL106可以包括位于多个聚合物层中的任意数量的堆叠的电连接的导电部件。
还如图13所示,可以在RDL106上方形成诸如外部连接件126(例如,BGA球、C4凸块等)的附加的封装部件。连接件126可以设置在UBM124上,该UBM也可以形成在RDL106上方。连接件126可以通过RDL106电连接至一个或多个管芯102。连接件126可以用于将管芯102电连接至其他封装组件,诸如另一器件管芯、内插器、封装衬底、印刷电路板、主板等。随后,可以去除载体200并且可以沿着划线使用合适的管芯锯切技术来分割管芯102(包括RDL106、UBM124和连接件126的对应的部分)。在分割之后,取决于封装件配置,每个器件封装件都可以包括单个管芯或多个管芯。
图14至图20示出了根据一些可选实施例的制造具有延伸穿过模塑料的中间通孔的器件封装件的各个中间阶段的截面图。在图14中,在载体衬底200上方(例如,在粘合层202上)形成各个中间通孔302。例如,中间通孔302可以包括铜、镍、银、金等并且可以通过任何合适的工艺形成。例如,可以在载体200上方形成晶种层(未示出),并且具有开口的图案化的光刻胶(未示出)可以用于限定中间通孔302的形状。开口可以暴露晶种层,并且可以用导电材料(例如,以电化学镀工艺)填充开口。随后,可以以灰化和/或湿剥离工艺去除光刻胶,保留位于载体200上的中间通孔302。也可以通过铜引线接合工艺使用铜引线柱(例如,不需要掩模、光刻胶和铜镀)来形成中间通孔302。中间通孔302的顶面可以或可以不基本齐平。开口304可以设置在相邻组的中间通孔302之间,并且开口304可以具有足够大的尺寸,以在其中设置管芯102(例如,见图15)。
接下来,在图15中,将管芯102放置在中间通孔302之间的开口304中。中间通孔302的顶面可以高于管芯102的顶面。图16和图17示出了模塑料104形成在管芯102周围以及聚合物层108形成在管芯102上方。聚合物层108可以足够厚以覆盖中间通孔302的顶面。例如,可以使用层压和传递模塑技术来形成聚合物层108和模塑料104,诸如通过图2至图5描述的方法(例如,在形成模塑料104之前形成聚合物层108)或图6至图8描述的方法(例如,在形成模塑料104之后形成聚合物层108)。聚合物层108的形成还可以包括压力夹紧工艺(例如,使用顶板和/或底板206),以平坦化聚合物层108的顶面。
在图18中,可以对聚合物层108执行减薄工艺,以暴露中间通孔302。例如,可以对聚合物层108的顶面应用研磨、CMP、飞切割工艺或其他回蚀刻技术,以暴露中间通孔302。在图19中,在聚合物层108中图案化开口212(例如,通过激光钻孔、光刻和/或蚀刻技术),以暴露管芯102的接触焊盘110。所产生的聚合物层108可以包括顶面,该顶面的TTV小于模塑料104的顶面的TTV。例如,聚合物层108的TTV可以小于约3μm,以对随后在聚合物层108上形成细间距的导电线提供合适的表面。
随后,在图20中,在聚合物层108上方形成RDL106的其他部件。例如,在聚合物层108上方形成导电部件能120和附加的聚合物层122。还如图20所示,可以在RDL106上方形成附加的封装部件,诸如位于UBM124上的外部连接件126(例如,BGA球、C4凸块等)。连接件126可以通过RDL106电连接至一个或多个管芯102和/或中间通孔302。随后,可以去除载体200,并且可以使用合适的管芯锯切技术沿着划线分割管芯102(包括对应的中间通孔302以及RDL106、UBM124和连接件126的部分)。在一些实施例中,可以在封装件100的背侧(例如,侧300’)上形成附加的部件(例如,附加的RDL、连接件、散热部件等),并且中间通孔302可以用于提供正侧RDL106与封装件300的背侧上的这些部件之间的电连接。因此,使用传递模塑工艺和层压工艺形成具有延伸穿过模塑料104的中间通孔的器件封装件300。
图21A和图21B分别示出了根据可选实施例的器件封装件500和550的截面图。封装件500和550可以基本类似于封装件100,其中,类似的参考标号代表类似的元件。例如,可以使用如上所述的传递模塑工艺在管芯102周围形成模塑料104,可以在模塑料104上方形成具有第一聚合物层108的RDL106。用于聚合物层108的形成工艺可以导致具有基本平坦的顶面(例如,作为包括压力夹紧的层压工艺的结果)的聚合物层108。可选地,聚合物层108可以具有非平坦的顶面,该非平坦的顶面的TTV小于模塑料104的顶面的TTV。RDL106还可以包括电连接至管芯102的各种导电部件120(例如,导电通孔120B和导电线120A),并且外部连接件126可以形成在这些导电部件120上方并且电连接至这些导电部件。图21A示出了一个实施例,其中UBM124也形成在导电部件120上方并且连接件126设置在UBM124上。在一些实施例中,一个或多个附加的钝化层(未示出)也可以形成在RDL106上方,其中,一些这样的附加的钝化层任选地覆盖UBM124的边缘。可选的,如图21B所示,可以省略UBM124,并且连接件126可以直接设置在RDL106中的导电线120A上。
如在封装件500和550中进一步包括的,模制的底部填充物502可以形成在连接件126周围,以向连接件126提供结构支撑和/或保护下面的器件层(例如,RDL106)。在一些实施例中,使用与模塑料104基本类似的工艺形成模制的底部填充物502。例如,在附接连接件126之前,可以使用如上所述的传递模塑工艺形成模制的底部填充物502。结果,模制的底部填充物502的顶面可以是非平坦的。随后,可以图案化(例如,使用光刻、激光钻孔和/或蚀刻技术)模制的底部填充物502,以暴露下面的UBM124(例如,如图21A所示)或导电线120A(例如,如图21B所示),并且连接件126可以放置在这样的导电部件上。
图22示出了根据各个实施例的用于形成器件封装件的工艺流程400。在步骤402中,例如,使用传递模塑工艺在管芯(例如,管芯102)周围形成模塑料(例如,模塑料104)。模塑料可以不延伸至管芯的顶面上方或不覆盖该管芯的顶面。例如,在形成模塑料时,管芯的顶面可以由膜层(例如,层压膜层或离型膜层)覆盖。在步骤406中,聚合物层(例如,聚合物层108)层压至管芯的顶面上方。聚合物层可以横向延伸越过管芯的边缘。在一些实施例中,在形成模塑料(步骤402)之前,形成聚合物层,并且在模制期间,聚合物层可以用作覆盖管芯的顶面的膜层。在其他的实施例中,在形成模塑料之后形成聚合物层,并且在模制期间所使用的膜层是离型膜层,在形成聚合物层之前,去除该离型膜层。
在步骤408中,通过压力夹紧来平坦化聚合物层的顶面。例如,通过模制装置或通过单独的层压装置实施压力夹紧。在一些实施例中,可以在层压工艺期间(例如,在用于将聚合物粘合至管芯的顶面的固化工艺期间)执行压力夹紧。可选地或附加地,可以与层压分离地执行压力夹紧。接下来,在步骤410中,在聚合物层中形成导电通孔(例如,通孔120B),导电通孔电连接至管芯(例如,电连接至管芯102中的接触焊盘110)。也可以形成其他部件,诸如附加的聚合物层、导电部件(例如,导电线、导电通孔和/或延伸穿过模塑料的中间通孔)、UBM、外部连接件等。
公开了一种用于形成扇出器件封装件和对应的结构的方法。在一些实施例中,使用传递模塑工艺在管芯周围形成模塑料,其中,在模制工艺期间,管芯的顶面由膜层覆盖。模塑料可以不形成为覆盖管芯的顶面,并且可以不需要对模塑料执行研磨工艺(或其他回蚀刻技术)来暴露管芯,简化了模制工艺并且降低了制造成本。由于传递模塑工艺,所以模塑料的顶面可以具有约5μm至约30μm的TTV。
使用层压工艺(例如,真空层压、热辊层压等)在模塑料和管芯上方形成诸如聚合物层(例如,层压膜材料)的第一RDL。在一些实施例中,在模制期间,聚合物层用作膜层。可选地,可以在形成模塑料之后形成聚合物层。层压工艺还可以包括压力夹紧,以提供适合用于在管芯上方形成各个扇出结构(例如,导电线)的聚合物层的基本平坦的顶面。聚合物层的接触模塑料的底面可以具有与模塑料对应的轮廓和TTV。因此,可以使用传递模制和层压工艺形成扇出器件封装件,这可以降低制造封装件的总体成本。
根据实施例,一种器件封装件包括:多个管芯;模塑料,沿着多个管芯的侧壁延伸;和聚合物层,位于模塑料上方并且接触模塑料。模塑料包括非平坦的顶面,并且聚合物层的顶面的总厚度变化(TTV)小于模塑料的非平坦的顶面的TTV。该器件封装件还包括位于聚合物层上的导电部件,其中,导电部件电连接至多个管芯中的至少一个。
根据另一实施例,一种器件封装件包括:第一管芯;第二管芯,邻近第一管芯;模塑料,沿着第一管芯和第二管芯的侧壁延伸;以及聚合物层,位于模塑料上方并且接触模塑料。模塑料包括介于第一管芯与第二管芯之间的非平坦的顶面,并且聚合物层包括位于模塑料的非平坦的顶面上方的非平坦的顶面。聚合物层的非平坦的顶面具有小于约5微米(μm)的总厚度变化(TTV)。器件封装件还包括位于聚合物层上的导电线,并且导电线的至少一部分接触聚合物层的非平坦的顶面。导电线电连接至第一管芯或第二管芯。
根据又一实施例,一种用于形成器件封装件的方法包括:在载体上设置多个管芯;在载体上方和在多个管芯周围形成模塑料;以及在多个管芯上方形成聚合物层。当形成模塑料时,多个管芯由膜层覆盖,并且模塑料包括介于多个管芯的相邻管芯之间的非平坦的顶面。聚合物层接触模塑料的非平坦的顶面,并且形成聚合物层包括平坦化工艺,以使得聚合物层的顶面的总厚度变化(TTV)小于模塑料的非平坦的顶面的TTV。该方法还包括在聚合物层上形成导电线。
根据本发明的一个实施例,提供了一种器件封装件,包括:多个管芯;模塑料,沿着所述多个管芯的侧壁延伸,其中,所述模塑料包括非平坦的顶面;聚合物层,位于所述模塑料上方并且接触所述模塑料,其中,所述聚合物层的顶面的总厚度变化(TTV)小于所述模塑料的非平坦的顶面的TTV;以及导电部件,位于所述聚合物层上,其中,所述导电部件电连接至所述多个管芯中的至少一个。
在上述器件封装件中,所述非平坦的顶面设置在所述多个管芯的相邻管芯之间,并且其中,所述聚合物层的设置在所述模塑料的非平坦的顶面上的部分也包括非平坦的顶面。
在上述器件封装件中,当所述多个管芯的相邻管芯之间的间隔小于约3000微米(μm)时,所述聚合物层的所述部分的TTV小于约15μm。
在上述器件封装件中,当所述多个管芯的相邻管芯之间的间隔小于约500微米(μm)时,所述聚合物层的所述部分的TTV小于约10μm。
在上述器件封装件中,当所述多个管芯的相邻管芯之间的间隔约小于100微米(μm)时,所述聚合物层的所述部分的TTV小于约5μm。
在上述器件封装件中,所述导电部件包括非平坦的顶面。
在上述器件封装件中,所述模塑料的非平坦的顶面是凹形的。
在上述器件封装件中,所述模塑料的非平坦的顶面的TTV为约5μm至约30μm。
根据本发明的另一实施例,提供了一种器件封装件,包括:第一管芯;第二管芯,邻近所述第一管芯;模塑料,沿着所述第一管芯和所述第二管芯的侧壁延伸,其中,所述模塑料包括位于所述第一管芯与所述第二管芯之间的非平坦的顶面;聚合物层,位于所述模塑料上方并且接触所述模塑料,其中,所述聚合物层包括位于所述模塑料的非平坦的顶面上方的非平坦的顶面,并且其中,所述聚合物层的非平坦的顶面具有小于约5微米(μm)的总厚度变化(TTV);以及导电线,位于所述聚合物层上,其中,所述导电线的至少一部分接触所述聚合物层的非平坦的顶面,并且其中,所述导电线电连接至所述第一管芯。
在上述器件封装件中,所述模塑料的非平坦的顶面的TTV大于所述聚合物层的非平坦的顶面的TTV。
在上述器件封装件中,所述模塑料的TTV为约5微米(μm)至约30μm。
在上述器件封装件中,所述第一管芯与所述第二管芯之间的间隔小于约3000μm。
在上述器件封装件中,所述聚合物层的非平坦的顶面和所述模塑料的非平坦的顶面均包括凹形轮廓。
在上述器件封装件中,所述导电线的接触所述聚合物层的非平坦的顶面的部分包括非平坦的顶面。
在上述器件封装件中,还包括:中间通孔,延伸穿过所述模塑料和所述聚合物层,其中,所述中间通孔电连接至形成在所述聚合物层上方的导电元件。
根据本发明的又一实施例,提供了一种用于形成器件封装件的方法,所述方法包括:在载体上设置多个管芯;在所述载体上方和在所述多个管芯周围形成模塑料,其中,当形成所述模塑料时,所述多个管芯由膜层覆盖,并且其中,所述模塑料包括位于所述多个管芯的相邻管芯之间的非平坦的顶面;
在所述多个管芯上方形成聚合物层并且所述聚合物层接触所述模塑料的非平坦的顶面,其中,形成所述聚合物层包括平坦化工艺,以使得所述聚合物层的顶面的总厚度变化(TTV)小于所述模塑料的非平坦的顶面的TTV;以及在所述聚合物层上形成导电线。
在上述方法中,在所述平坦化工艺之后,所述聚合物层的顶面的TTV小于约5微米(μm),并且其中,所述多个管芯的相邻管芯之间的间隔小于约3000μm。
在上述方法中,所述平坦化工艺包括压力夹紧所述聚合物层的顶面。
在上述方法中,形成所述聚合物层包括对所述模塑料上的膜层进行层压。
在上述方法中,在所述平坦化工艺之后,所述聚合物层的接触所述模塑料的非平坦的顶面的至少一部分也包括非平坦的顶面。上面论述了若干实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,可以进行多种变化、替换以及改变。

Claims (10)

1.一种器件封装件,包括:
多个管芯;
模塑料,沿着所述多个管芯的侧壁延伸,其中,所述模塑料包括非平坦的顶面;
聚合物层,位于所述模塑料上方并且接触所述模塑料,其中,所述聚合物层的顶面的总厚度变化(TTV)小于所述模塑料的非平坦的顶面的TTV;以及
导电部件,位于所述聚合物层上,其中,所述导电部件电连接至所述多个管芯中的至少一个。
2.根据权利要求1所述的器件封装件,其中,所述非平坦的顶面设置在所述多个管芯的相邻管芯之间,并且其中,所述聚合物层的设置在所述模塑料的非平坦的顶面上的部分也包括非平坦的顶面。
3.根据权利要求2所述的器件封装件,其中,当所述多个管芯的相邻管芯之间的间隔小于约3000微米(μm)时,所述聚合物层的所述部分的TTV小于约15μm。
4.根据权利要求2所述的器件封装件,其中,当所述多个管芯的相邻管芯之间的间隔小于约500微米(μm)时,所述聚合物层的所述部分的TTV小于约10μm。
5.根据权利要求2所述的器件封装件,其中,当所述多个管芯的相邻管芯之间的间隔约小于100微米(μm)时,所述聚合物层的所述部分的TTV小于约5μm。
6.根据权利要求1所述的器件封装件,其中,所述导电部件包括非平坦的顶面。
7.根据权利要求1所述的器件封装件,其中,所述模塑料的非平坦的顶面是凹形的。
8.根据权利要求1所述的器件封装件,其中,所述模塑料的非平坦的顶面的TTV为约5μm至约30μm。
9.一种器件封装件,包括:
第一管芯;
第二管芯,邻近所述第一管芯;
模塑料,沿着所述第一管芯和所述第二管芯的侧壁延伸,其中,所述模塑料包括位于所述第一管芯与所述第二管芯之间的非平坦的顶面;
聚合物层,位于所述模塑料上方并且接触所述模塑料,其中,所述聚合物层包括位于所述模塑料的非平坦的顶面上方的非平坦的顶面,并且其中,所述聚合物层的非平坦的顶面具有小于约5微米(μm)的总厚度变化(TTV);以及
导电线,位于所述聚合物层上,其中,所述导电线的至少一部分接触所述聚合物层的非平坦的顶面,并且其中,所述导电线电连接至所述第一管芯。
10.一种用于形成器件封装件的方法,所述方法包括:
在载体上设置多个管芯;
在所述载体上方和在所述多个管芯周围形成模塑料,其中,当形成所述模塑料时,所述多个管芯由膜层覆盖,并且其中,所述模塑料包括位于所述多个管芯的相邻管芯之间的非平坦的顶面;
在所述多个管芯上方形成聚合物层并且所述聚合物层接触所述模塑料的非平坦的顶面,其中,形成所述聚合物层包括平坦化工艺,以使得所述聚合物层的顶面的总厚度变化(TTV)小于所述模塑料的非平坦的顶面的TTV;以及
在所述聚合物层上形成导电线。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107808857A (zh) * 2016-09-09 2018-03-16 力成科技股份有限公司 芯片封装结构及其制造方法
CN110520975A (zh) * 2017-04-21 2019-11-29 应用材料公司 用于半导体封装处理的方法和设备

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI446501B (zh) * 2012-01-20 2014-07-21 矽品精密工業股份有限公司 承載板、半導體封裝件及其製法
US9691686B2 (en) * 2014-05-28 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Contact pad for semiconductor device
US9633934B2 (en) 2014-11-26 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semicondutor device and method of manufacture
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US10276421B2 (en) * 2016-03-15 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, integrated fan-out package array, and method of manufacturing integrated fan-out packages
US20170338204A1 (en) * 2016-05-17 2017-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Device and Method for UBM/RDL Routing
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US9935068B2 (en) * 2016-06-21 2018-04-03 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
US10141276B2 (en) 2016-09-09 2018-11-27 Powertech Technology Inc. Semiconductor package structure and manufacturing method thereof
US10529697B2 (en) 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10157846B2 (en) * 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US20180130761A1 (en) * 2016-11-09 2018-05-10 Samsung Electro-Mechanics Co., Ltd. Semiconductor package, manufacturing method thereof, and electronic element module using the same
US10304793B2 (en) * 2016-11-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
CN111010871A (zh) 2017-03-16 2020-04-14 分子印记公司 光学聚合物膜及其铸造方法
US11152274B2 (en) 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
CA3076669A1 (en) 2017-10-17 2019-04-25 Magic Leap, Inc. Methods and apparatuses for casting polymer products
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10522436B2 (en) 2017-11-15 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization of semiconductor packages and structures resulting therefrom
US10510704B2 (en) * 2018-01-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US11315891B2 (en) * 2018-03-23 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming semiconductor packages having a die with an encapsulant
US10700008B2 (en) * 2018-05-30 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure having redistribution layer structures
US10879166B2 (en) * 2018-06-25 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure having redistribution structure with photosensitive and non-photosensitive dielectric materials and fabricating method thereof
EP3867677A4 (en) 2018-10-16 2021-12-22 Magic Leap, Inc. METHODS AND APPARATUS FOR CASTING POLYMERIC PRODUCTS
EP3680211B1 (en) * 2019-01-10 2024-03-06 TE Connectivity Solutions GmbH Sensor unit and method of interconnecting a substrate and a carrier
US11211301B2 (en) * 2020-02-11 2021-12-28 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of manufacture
US11852967B2 (en) 2020-12-22 2023-12-26 Taiwan Semiconductor Manufacturing Company Ltd. Methods for making semiconductor-based integrated circuits

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1463038A (zh) * 2002-05-31 2003-12-24 富士通株式会社 半导体器件及其制造方法
CN1670952A (zh) * 2004-03-19 2005-09-21 矽品精密工业股份有限公司 具有增层结构的晶圆级半导体封装件及其制法
CN101452863A (zh) * 2007-11-28 2009-06-10 南茂科技股份有限公司 晶粒重新配置的封装结构中使用顺应层的制造方法
CN102623391A (zh) * 2010-12-22 2012-08-01 新科金朋有限公司 半导体器件和在半导体管芯上方形成集成无源器件的方法
US20130082231A1 (en) * 2010-06-16 2013-04-04 Nec Corporation Semiconductor device and manufacturing method for semiconductor device

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US7220815B2 (en) 2003-07-31 2007-05-22 E.I. Du Pont De Nemours And Company Sulfonated aliphatic-aromatic copolyesters and shaped articles produced therefrom
TWI225670B (en) * 2003-12-09 2004-12-21 Advanced Semiconductor Eng Packaging method of multi-chip module
US8133762B2 (en) 2009-03-17 2012-03-13 Stats Chippac, Ltd. Semiconductor device and method of providing z-interconnect conductive pillars with inner polymer core
KR20080094251A (ko) 2007-04-19 2008-10-23 삼성전자주식회사 웨이퍼 레벨 패키지 및 그 제조방법
US7868445B2 (en) 2007-06-25 2011-01-11 Epic Technologies, Inc. Integrated structures and methods of fabrication thereof with fan-out metallization on a chips-first chip layer
US7851246B2 (en) 2007-12-27 2010-12-14 Stats Chippac, Ltd. Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device
US8084302B2 (en) 2008-03-07 2011-12-27 Stats Chippac, Ltd. Semiconductor package having semiconductor die with internal vertical interconnect structure and method therefor
US8877524B2 (en) * 2008-03-31 2014-11-04 Cree, Inc. Emission tuning methods and devices fabricated utilizing methods
US8354304B2 (en) 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7858441B2 (en) 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
US7642128B1 (en) 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
JP5330065B2 (ja) * 2009-04-13 2013-10-30 新光電気工業株式会社 電子装置及びその製造方法
US8058102B2 (en) 2009-11-10 2011-11-15 Advanced Chip Engineering Technology Inc. Package structure and manufacturing method thereof
US8409926B2 (en) 2010-03-09 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer around semiconductor die
US20120012991A1 (en) * 2010-07-16 2012-01-19 Qualcomm Incorporated Integrated shielding for a package-on-package system
US8097490B1 (en) 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
KR101390628B1 (ko) 2010-11-15 2014-04-29 유나이티드 테스트 엔드 어셈블리 센터 엘티디 반도체 패키지 및 반도체 소자 패키징 방법
US8525344B2 (en) 2011-02-24 2013-09-03 Stats Chippac, Ltd. Semiconductor device and method of forming bond wires between semiconductor die contact pads and conductive TOV in peripheral area around semiconductor die
US8841765B2 (en) * 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US8530277B2 (en) 2011-06-16 2013-09-10 Stats Chippac Ltd. Integrated circuit packaging system with package on package support and method of manufacture thereof
US20130049214A1 (en) 2011-08-29 2013-02-28 Infineon Technologies Ag Method of processing at least one die and die arrangement
US9111949B2 (en) * 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9111896B2 (en) * 2012-08-24 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package semiconductor device
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US8993380B2 (en) * 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9530762B2 (en) * 2014-01-10 2016-12-27 Taiwan Semiconductor Manufacturing Company Limited Semiconductor package, semiconductor device and method of forming the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1463038A (zh) * 2002-05-31 2003-12-24 富士通株式会社 半导体器件及其制造方法
CN1670952A (zh) * 2004-03-19 2005-09-21 矽品精密工业股份有限公司 具有增层结构的晶圆级半导体封装件及其制法
CN101452863A (zh) * 2007-11-28 2009-06-10 南茂科技股份有限公司 晶粒重新配置的封装结构中使用顺应层的制造方法
US20130082231A1 (en) * 2010-06-16 2013-04-04 Nec Corporation Semiconductor device and manufacturing method for semiconductor device
CN102623391A (zh) * 2010-12-22 2012-08-01 新科金朋有限公司 半导体器件和在半导体管芯上方形成集成无源器件的方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107808857A (zh) * 2016-09-09 2018-03-16 力成科技股份有限公司 芯片封装结构及其制造方法
CN107808857B (zh) * 2016-09-09 2020-03-13 力成科技股份有限公司 芯片封装结构及其制造方法
US10840200B2 (en) 2016-09-09 2020-11-17 Powertech Technology Inc. Manufacturing method of chip package structure comprising encapsulant having concave surface
CN110520975A (zh) * 2017-04-21 2019-11-29 应用材料公司 用于半导体封装处理的方法和设备
CN110520975B (zh) * 2017-04-21 2023-09-19 应用材料公司 用于半导体封装处理的方法和设备

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