CN103811394A - 载具晶圆及其制造方法以及封装方法 - Google Patents

载具晶圆及其制造方法以及封装方法 Download PDF

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CN103811394A
CN103811394A CN201310028364.6A CN201310028364A CN103811394A CN 103811394 A CN103811394 A CN 103811394A CN 201310028364 A CN201310028364 A CN 201310028364A CN 103811394 A CN103811394 A CN 103811394A
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glassy layer
carrier wafer
cte
layer
integrated circuit
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CN103811394B (zh
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陈承先
李明机
余振华
胡延章
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了载具晶圆、制造载具晶圆的方法以及封装方法。在一个实施例中，一种载具晶圆包括第一玻璃层。该载具晶圆包括与第一玻璃层连接的第二玻璃层。第一玻璃层具有第一热膨胀系数(CTE)，而第二玻璃层具有第二CTE。

Description

载具晶圆及其制造方法以及封装方法
技术领域
本发明涉及载具晶圆及其制造方法以及使用该载具晶圆封装半导体器件的方法。
背景技术
半导体器件用于各种电子应用，举例来说，诸如个人计算机、手机、数码相机、以及其他电子设备。通常通过在半导体衬底上方依次沉积绝缘或介电材料层、导电材料层和半导电材料层，以及利用光刻使各种材料层图案化以在其上形成电路部件和元件来制造半导体器件。
通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线切割集成电路而分割出单独的管芯。然后分别地封装该单独的管芯，例如以多芯片模块或以其他类型的封装方式。
半导体产业通过不断减小集成电路(IC)的最小部件尺寸，从而能够将更多元件集成到给定面积上，进而持续改进各种电子部件(例如，晶体管、二极管、电阻器、电容器等等)的集成密度。在一些应用中，这些更小的电子元件也需要比过去的封装件利用更少面积的更小的封装件。
已经开发用于半导体器件的一种更小封装是晶圆级封装(WLP)。举例来说，对于半导体器件，在封装方面的其他最近进展包括三维集成电路(3DIC)封装和堆叠封装(PoP)器件。在一些封装工艺流程中，载具晶圆用作封装工艺中的临时安装或支撑表面。
发明内容
为了解决现有技术中存在的问题，根据本发明的一方面，提供了一种载具晶圆，包括：第一玻璃层；以及与所述第一玻璃层连接的第二玻璃层，其中所述第一玻璃层具有第一热膨胀系数(CTE)，而所述第二玻璃层具有第二CTE。
在所述的载具晶圆中，所述第一玻璃层具有第一厚度，而所述第二玻璃层具有第二厚度。在一个实施例中，所述第二厚度与所述第一厚度基本上相同。在另一个实施例中，所述第二厚度不同于所述第一厚度。
在所述的载具晶圆中，所述第二CTE不同于所述第一CTE。
在所述的载具晶圆中，所述第二CTE与所述第一CTE基本上相同。
在所述的载具晶圆中，所述载具晶圆的整体CTE在约3至11的范围内。
在所述的载具晶圆中，所述第一CTE或所述第二CTE是约5以下或者约7以上。
根据本发明的又一方面，提供了一种制造载具晶圆的方法，所述方法包括：提供第一玻璃层，所述第一玻璃层具有第一热膨胀系数(CTE)；以及将第二玻璃层连接至所述第一玻璃层，其中所述第二玻璃层具有第二CTE。
所述的方法还包括将至少一个第三玻璃层连接至所述第二玻璃层或所述第一玻璃层。
在所述的方法中，将所述第二玻璃层连接至所述第一玻璃层包括使用选自基本上由热接合工艺、氢接合工艺、压力接合工艺、胶粘工艺和这些的组合所组成的组的工艺。
所述的方法还包括在将所述第二玻璃层连接至所述第一玻璃层之后，抛光所述第一玻璃层或所述第二玻璃层。
所述的方法还包括使所述第一玻璃层和所述第二玻璃层形成为预定形状。
所述的方法还包括在所述第一玻璃层和所述第二玻璃层的边缘上形成对准部件。
所述的方法还包括选择具有所述第一CTE的第一玻璃层和选择具有所述第二CTE的第二玻璃层从而使所述载具晶圆的整体CTE为预定值。
根据本发明的又一方面，提供了一种封装半导体器件的方法，所述方法包括：将多个集成电路管芯连接至载具晶圆，所述载具晶圆包括与第二玻璃层连接的第一玻璃层；在所述多个集成电路管芯中的每一个集成电路管芯和所述载具晶圆的上方形成封装系统；以及去除所述载具晶圆。
所述的方法还包括分割位于所述多个集成电路管芯上方的所述封装系统从而形成多个单独的封装的半导体器件。
在所述的方法中，形成所述封装系统包括在所述载具晶圆的上方形成多个组件通孔(TAV)，将所述多个集成电路管芯中的每一个集成电路管芯接合至所述载具晶圆，在所述TAV和所述多个集成电路管芯上方形成模塑料，以及在所述模塑料上方形成第一再分布层(RDL)。
在一个实施例中，所述的方法还包括在形成所述模塑料之后，化学机械抛光所述模塑料从而暴露出所述TAV和位于所述多个集成电路管芯上的接触焊盘。
在另一个实施例中，所述载具晶圆包括第一载具晶圆；所述方法还包括：在形成所述第一RDL之后将第二载具晶圆连接至所述第一RDL，以及去除所述第一载具晶圆；并且所述方法还包括：在所述多个集成电路管芯和所述TAV上方形成第二RDL，以及去除所述第二载具晶圆。
附图说明
为了更好地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图3示出根据一些实施例制造载具晶圆的方法的截面图。
图4是图3所示的载具晶圆的俯视图。
图5是根据其他实施例的载具晶圆的截面图。
图6是示出载具晶圆和载具晶圆的玻璃层的一些热膨胀系数(CTE)的图表。
图7至图14是根据一些实施例使用载具晶圆的方法的截面图。
图15是根据一些实施例利用载具晶圆封装半导体器件的方法的流程图。
除非另有说明，不同附图中的相应标号和符号通常是指相应部件。绘制附图用于清楚地示出实施例的相关方面而不必成比例绘制。
具体实施方式
下面，详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅是制造和使用本发明的例证性具体方式，而不用于限制本发明的范围。
本发明的一些实施例涉及用于封装半导体器件的载具晶圆。本文将描述新颖的载具晶圆及其制造方法和半导体器件的封装方法。
图1至图3示出根据一些实施例制造载具晶圆110(见图2)的方法的截面图。首先参照图1，根据本发明的实施例示出第一玻璃层100a以及与第一玻璃层100a连接的第二玻璃层100b的截面图。第一玻璃层100a和第二玻璃层100b包含玻璃材料，作为实例，诸如硼硅酸盐玻璃、铝硅酸盐玻璃、碱-钡硅酸盐玻璃或石英。举例来说，在一些实施例中，第一玻璃层100a和第二玻璃层100b可以包括主要成分SiO2以及为实现玻璃所需特性而包括的一种或多种元素。可选地，第一玻璃层100a和第二玻璃层100b可以包含其他材料。
第一玻璃层100a的厚度为尺寸d1，其中尺寸d1是约1.2mm或1.2mm以下。第二玻璃层100b的厚度为尺寸d2，其中尺寸d2是约1.2mm或1.2mm以下。在一些实施例中，尺寸d2与尺寸d1基本上相同。在其他实施例中，尺寸d2与尺寸d1不相同。可选地，尺寸d1和d2可以包括其他值。
第一玻璃层100a具有第一热膨胀系数(CTE)，而第二玻璃层100b具有第二CTE。在一些实施例中，第二玻璃层100b的第二CTE不同于第一玻璃层100a的第一CTE。根据本发明的一些实施例，例如将在本文中进一步描述的，选择第一玻璃层100a和第二玻璃层100b的材料以获得具有用于载具晶圆110的预定值的所需整体CTE。例如，在一些实施例中，第一玻璃层100a的第一CTE和第二玻璃层100b的第二CTE为约5或小于5或者约7或大于7。可选地，在其他实施例中，第一CTE和第二CTE可以包括其他值，而且第二CTE可以与第一CTE基本上相同。
图2是包括第一玻璃层100a和第二玻璃层100b的复合载具晶圆110的截面图。根据一些实施例，利用热接合工艺、氢接合工艺、压力接合工艺、胶粘工艺和/或这些的组合将第二玻璃层100b连接至第一玻璃层100a。例如，可以使用胶粘剂102将第一玻璃层100a和第二玻璃层100b接合起来。作为实例，胶粘剂102可以包括粘合剂或胶带。在一些实施例中，在施加胶粘剂102之前，可以对第一玻璃层100a和第二玻璃层100b中的一个或者两个都实施旋转涂布。作为实例，胶粘剂102可以包括诸如苯并环丁烯(BCB)或SU-8(其可以包含环氧树脂，γ-丁内酯和三芳基锍盐)的材料，但是可选地也可以使用其他材料。在热接合工艺的接合工艺期间，第一玻璃层100a和第二玻璃层100b可以暴露于热量104。例如，可以在约100℃至约250℃的温度下加热第一玻璃层100a和第二玻璃层100b。可选地，可以使用其他温度。在压力接合工艺中，也可以使用压力106将第一玻璃层100a和第二玻璃层100b接合起来。例如，压力106的量可以为约20至100KN并持续预定的一段时间。可选地，可以使用其他量的压力106。例如，可以利用夹具或其他工具或通过室内施加的压力施加压力106。例如，在一些实施例中，可以使用压力、氢气、和/或热量104借助范德华力将第一玻璃层100a和第二玻璃层100b接合起来。可选地，可以使用其他类型的接合工艺。
在一些实施例中，在接合工艺之后，载具晶圆110的总厚度为尺寸d3，其中尺寸d3是1.5mm或1.5mm以下。在一些实施例中，作为另一个实例，尺寸d3可以是约0.85mm。可选地，尺寸d3可以是其他值。在一些实施例中，在复合载具晶圆110中不包括粘合剂102。
在将第二玻璃层100b连接至第一玻璃层100a之后，在一些实施例中，分别利用抛光工艺114a或114b抛光第一玻璃层100a和/或第二玻璃层100b，如图3所示。例如，抛光工艺114a和/或114b制备载具晶圆110的一个或多个表面。还如图3所示，在一些实施例中，利用形成工艺112形成载具晶圆110。形成工艺112包括通过将载具晶圆110的边缘研磨和/或抹平至预定的所需尺寸和形状而重塑载具晶圆110的第一玻璃层100a和第二玻璃层100b的边缘。如图4所示，在一些实施例中，载具晶圆110在俯视图中的形状基本上是圆形。
图4是图3所示的载具晶圆110的俯视图。在接合工艺之后，包括槽口或其他类型的对准部件的对准部件116形成在第一玻璃层100a和第二玻璃层100b的边缘上。多个对准部件116可以可选地形成在载具晶圆110的边缘上，未在图中示出。在一些实施例中，载具晶圆110的直径可以为约300mm。可选地，载具晶圆110可以包括其他大小或尺寸。
图5是根据其他实施例的载具晶圆110的截面图。载具晶圆110是包括多个玻璃层100a、100b、100c和100d的复合晶圆。图5中示出四个玻璃层100a、100b、100c和100d；然而根据本发明的实施例，载具晶圆110包括两个或两个以上的玻璃层100a、100b、100c和100d。在一些实施例中，至少一个第三玻璃层100c和100d与第二玻璃层100b或第一玻璃层100a连接。载具晶圆110也可以包括多于四个的玻璃层100a、100b、100c和100d。例如，在一些实施例中，可以依次将玻璃层100a、100b、100c和100d接合起来，或者可以同时将玻璃层100a、100b、100c和100d的整体堆叠件接合起来。
图6是示出载具晶圆110和载具晶圆110的玻璃层100a、100b、100c和100d的一些热膨胀系数(CTE)的图表。在该图表中标绘出一些目前可商购获得的玻璃层的厚度和CTE。示出了从若干供应商V1、V2、V3和V4获得的玻璃层的CTE(单位为百万分之一(ppm)/°K)相对于厚度(单位为mm)的绘图。区域118示出约4.8至7.0的CTE范围，目前可购买获得的玻璃层都不在该范围内。
有利的是，通过制造具有如图2所示的多个玻璃层100a和100b或如图5所示的玻璃层100a、100b、100c和/或100d的复合载具晶圆110，可以获得整体CTE落入图6所示图表的区域118内的载具晶圆110。这在封装应用中是令人满意的，其中该CTE范围是有利的，因为部分封装系统或整个封装系统的CTE落入该范围。因此，通过本发明的实施例可以实现与封装系统材料的CTE的近似匹配或准确匹配。例如，在一些实施例中，载具晶圆110的整体CTE在约3至11的范围内。可选地，整体CTE可以包括其他值。
作为一个实例，第一玻璃层100a可以包括图6所示图表上CTE为约3.8的位置117，以及第二玻璃层100b可以包括图表上CTE为约8.0的位置119，从而使得载具晶圆110的整体CTE是约5.9。有利的是，可以选择载具晶圆110的玻璃层100a、100b、100c和100d的厚度和CTE的各种组合从而获得载具晶圆110所期望的预定整体CTE值，该整体CTE值落入区域118内或落在低于或者高于区域118的CTE值的区域内。图6中的图表可以用于选择玻璃层100a、100b、100c和100d从而获得复合载具晶圆110所需的整体CTE值并实现更宽的工艺窗口。
图7至图14是根据一些实施例的使用本文描述的载具晶圆110的方法的截面图。载具晶圆110用于封装半导体器件，诸如图10至图14示出的集成电路管芯130。在图10至图14中仅示出一个集成电路管芯130；然而，根据一些实施例，在载具晶圆110的表面上方同时封装多个集成电路管芯130。下文将要进一步描述的，在去除载具晶圆110之后，将经过封装的集成电路管芯130分割成单独的封装的半导体器件。
在图7中，首先提供本文所描述的包括多个玻璃层100a、100b、100c和/或100d并获得具体封装系统所需的CTE的载具晶圆110。在本文中，载具晶圆110也被称为第一载具晶圆110。包括胶粘剂或胶带的粘合剂120形成在载具晶圆110上方。包含聚苯并恶唑(PBO)、聚酰亚胺或其他材料的绝缘层122形成在粘合剂120的上方。晶种层124形成在绝缘层122的上方。晶种层124包括金属，该金属用作用于形成组件通孔(throughassembly vias，TAV)128(参见图8)的镀工艺的晶种。
在图8中，包括绝缘材料的干膜126形成在晶种层124的上方。利用光刻工艺使干膜126图案化，从而在干膜126中留下用于TAV128的图案。在一些实施例中，通过在干膜126上方沉积光刻胶层(未示出)，然后将光刻胶层暴露于从其上形成有所需图案的光刻掩模反射或穿过该光刻掩模的光或能量，利用光刻图案化干膜126。使光刻胶层显影，部分光刻胶层被灰化或蚀刻去除，从而在干膜126的顶部上留下经过图案化的光刻胶层。然后将光刻胶层用作掩模同时蚀刻去除干膜126的暴露部分。然后去除光刻胶层。作为另一个实例，也可以使用直接图案化工艺使干膜126图案化。
利用镀工艺在干膜126的图案中形成TAV128。在一些实施例中，TAV128包含Cu或Cu合金。在一些实施例中，在俯视图中TAV128具有圆形、椭圆形、正方形或矩形形状。可选地，TAV128可以包括其他材料和形状。然后，如图9所示，去除干膜126。
然后，如图10所示，利用包含胶粘剂或胶带的粘合剂132将集成电路管芯130接合至晶种层124。集成电路管芯130包括形成在半导体衬底上方的半导体电路，该半导体衬底包括例如硅或其他类型的半导体材料。集成电路管芯130包括有源元件或电路(未示出)，该有源元件或电路可以包括晶体管、二极管、电容器、电感器和其他类型的器件。作为实例，集成电路管芯130可以包括存储器器件、逻辑器件或其他类型的电路。集成电路管芯130包括多个设置在绝缘材料135内的接触焊盘134，绝缘材料135形成在集成电路管芯130的顶面上。作为实例，接触焊盘134包含Cu、Cu合金或其他金属或材料。
还如图10所示，模塑料136形成在集成电路管芯130、TAV128和晶种层124的暴露部分的上方。如图11所示，化学机械抛光模塑料136从而暴露TAV128的顶面和集成电路管芯130的接触焊盘134的顶面。
如图12所示，在模塑料136以及TAV128和集成电路管芯130的接触焊盘134的暴露顶面上方形成第一再分布层(RDL)138。第一RDL138包括一个或多个绝缘材料层和一个或多个导线层，未在图中示出。作为实例，导线层可以包含Cu、Al、这些的合金或其他材料。作为实例，绝缘材料层可以包括二氧化硅、氮化硅、其他绝缘体或这些的组合。例如，在一些实施例中，第一RDL层138可以包括适用于将集成电路管芯130的接触焊盘134的足迹(footprint)扇出至封装件的更大足迹的扇出区(未示出)。在一些实施例中，第一RDL138可以包括位于其顶面上用于连接多个焊料凸块或焊球的球下金属化层(UBM)，也未在图中示出。例如，在一些实施例中，部分第一RDL138将集成电路管芯130上的接触焊盘134电连接至TAV128。
还如图12所示，然后将载具晶圆110’连接至第一RDL138。在本文中，载具晶圆110’也被称为第二载具晶圆110’。在一些实施例中，第二载具晶圆110’可以包括本文对第一载具晶圆110所描述的相似或不同的多个玻璃层100a、100b、100c和100d。在其他实施例中，第二载具晶圆110’包括单个玻璃层。在又一个实施例中，第二载具晶圆110’包括多个玻璃层100a、100b、100c和100d，而第一载具晶圆110包括单个玻璃层。根据本发明的一些实施例，第一载具晶圆110和第二载具晶圆110’中的至少一个包括多个玻璃层100a、100b、100c和100d。
在将第二载具晶圆110’与第一RDL138连接之后，使用去接合工艺去除第一载具晶圆110，如图13所示。还使用一种或多种蚀刻工艺或去接合工艺去除粘合剂120、绝缘层122和晶种层124。然后在模塑料136的底面上、TSV128的暴露底面上以及集成电路管芯130的底面上方形成第二RDL140。例如，第二RDL140可以包括如对第一RDL138所描述的类似的材料层。然后，如图14所示，使用去接合工艺去除第二载具晶圆110’。
如图所示，经过封装的半导体器件150包括封装系统152和集成电路管芯130。在一些实施例中，在集成电路管芯130上方形成的封装系统152包括第一RDL138和第二RDL140两者。在其他实施例中，如图14中的虚线所示，封装系统152只包括第一RDL138。封装系统152包括图14中示出的除了集成电路管芯130之外的元件；即利用封装系统152封装集成电路管芯130。TAV128为封装系统152提供垂直连接，例如在第一RDL138和第二RDL140之间。在一些实施例中，第一RDL138和第二RDL140为封装系统152提供水平连接。
在图7至图14所示的工艺流程之后，如图14所示，沿着划线154分割包括经过封装的半导体器件150的封装的集成电路管芯130。例如，在划线154处分割设置在集成电路管芯130上方的封装系统从而形成多个单独的封装的半导体器件150。可以通过将多个焊料凸块或焊球连接至第一RDL138和/或第二RDL140将每个经过封装的半导体器件150连接至另一个经过封装的半导体器件150。然后可以将焊料凸块或焊球连接至本文所描述的另一个经过封装的半导体器件150的RDL138或140，或连接至另一种类型的经过封装的半导体器件，从而形成堆叠封装(PoP)器件(未示出)。
图15是根据一些实施例封装半导体器件的方法的流程图160。在步骤162，将集成电路管芯130连接至载具晶圆110，载具晶圆110包括与第二玻璃层100b连接的第一玻璃层100a(也参见图10)。在步骤164，在集成电路管芯和载具晶圆110的上方形成封装系统152(图14)。在步骤166，去除载具晶圆110(图12和13)。
本发明的一些实施例包括形成具有多个玻璃层100a、100b、100c和/或100d的复合载具晶圆110的方法，并且也包括具有多个玻璃层100a、100b、100c和100d的载具晶圆110。本发明的一些实施例包括利用新颖的载具晶圆110封装半导体器件的方法。
本发明的一些实施例的优点包括提供了新颖的具有多个玻璃层100a、100b、100c和/或100d的复合载具晶圆110。通过本文描述的一些实施例，可以获得CTE值与各种封装系统和结构的CTE值基本上等同的载具晶圆110。通过在载具晶圆110结构中包括多个玻璃层100a、100b、100c和100d可以获得灵活的CTE值。CTE与封装系统的CTE匹配的能力为经过封装的半导体器件150带来翘曲减少、翘曲优化和翘曲控制，还为例如在第一RDL138或第二RDL140上后续形成的焊料凸块带来更宽的凸块工艺裕度(bumping process margin)。有利的是，得到的载具晶圆110的整体CTE范围所在的CTE范围是目前可商购得到的单层载具晶圆所达不到的。新颖的载具晶圆110的结构和设计可以很容易地应用于封装工艺流程中。
根据本发明的一些实施例，一种载具晶圆包括第一玻璃层以及与第一玻璃层连接的第二玻璃层。第一玻璃层具有第一CTE，而第二玻璃层具有第二CTE。
根据其他实施例，一种制造载具晶圆的方法包括提供第一玻璃层以及将第二玻璃层连接至第一玻璃层。第一玻璃层具有第一CTE，而第二玻璃层具有第二CTE。
根据其他实施例，一种封装半导体器件的方法包括提供载具晶圆，该载具晶圆包括与第二玻璃层连接的第一玻璃层。该方法包括在载具晶圆上方连接多个集成电路管芯，在多个集成电路管芯中的每一个集成电路管芯和载具晶圆的上方形成封装系统，以及去除载具晶圆。
尽管已经详细地描述了本发明的一些实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，进行各种改变、替换和更改。例如，本领域普通技术人员将很容易理解，本文描述的许多部件、功能、工艺和材料可以发生变化而仍然在本发明的范围内。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种载具晶圆，包括：
第一玻璃层；以及
与所述第一玻璃层连接的第二玻璃层，其中所述第一玻璃层具有第一热膨胀系数(CTE)，而所述第二玻璃层具有第二CTE。
2.根据权利要求1所述的载具晶圆，其中所述第一玻璃层具有第一厚度，而所述第二玻璃层具有第二厚度。
3.根据权利要求2所述的载具晶圆，其中，所述第二厚度与所述第一厚度基本上相同；或者所述第二厚度不同于所述第一厚度。
4.根据权利要求1所述的载具晶圆，其中所述第二CTE不同于所述第一CTE；或者所述第二CTE与所述第一CTE基本上相同。
5.根据权利要求1所述的载具晶圆，其中所述载具晶圆的整体CTE在约3至11的范围内。
6.根据权利要求1所述的载具晶圆，其中所述第一CTE或所述第二CTE是约5以下或者约7以上。
7.一种制造载具晶圆的方法，所述方法包括：
提供第一玻璃层，所述第一玻璃层具有第一热膨胀系数(CTE)；以及
将第二玻璃层连接至所述第一玻璃层，其中所述第二玻璃层具有第二CTE。
8.根据权利要求7所述的方法，还包括将至少一个第三玻璃层连接至所述第二玻璃层或所述第一玻璃层。
9.根据权利要求7所述的方法，还包括选择具有所述第一CTE的第一玻璃层和选择具有所述第二CTE的第二玻璃层从而使所述载具晶圆的整体CTE为预定值。
10.一种封装半导体器件的方法，所述方法包括：
将多个集成电路管芯连接至载具晶圆，所述载具晶圆包括与第二玻璃层连接的第一玻璃层；
在所述多个集成电路管芯中的每一个集成电路管芯和所述载具晶圆的上方形成封装系统；以及
去除所述载具晶圆。
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