TWI613784B - 半導體結構和製造半導體結構的方法 - Google Patents

半導體結構和製造半導體結構的方法 Download PDF

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TWI613784B
TWI613784B TW104138917A TW104138917A TWI613784B TW I613784 B TWI613784 B TW I613784B TW 104138917 A TW104138917 A TW 104138917A TW 104138917 A TW104138917 A TW 104138917A TW I613784 B TWI613784 B TW I613784B
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bump
section
group
sections
semiconductor wafer
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TW104138917A
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TW201631729A (zh
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曹佩華
安泰 徐
蕭煥廷
張國欽
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台灣積體電路製造股份有限公司
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Abstract

提供了一種半導體結構以及形成該半導體結構的方法。該半導體結構包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面；以及傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段高度，並且每一個凸塊區段具有以該區段高度與該凸塊區段的平均截面面積的乘積定義的體積；其中該凸塊區段的該第一組的總體積與該凸塊區段的該第二組的總體積之比約在0.03和0.8之間。

Description

半導體結構和製造半導體結構的方法
本發明係有關於半導體結構。
由於積體電路的出現，半導體工業因各種電子零件(即，電晶體、二極體、電阻器、電容等)的積體密度和IC半導體封裝的不斷改進而經歷了持續快速地發展。在很大程度上，積體密度的這些改進在減小結構尺寸方面已實現了不斷地遞減，其允許更多的零件集成在半導體晶片或半導體封裝中。
允許更多的零件集成在半導體封裝中的一種方法是採用倒置晶片結構，其中半導體晶片通過傳導凸塊結合至基板，並且該半導體晶片倒置在活性電路表面上。這種倒置晶片封裝具有以下問題：在封裝工藝期間會經受不同的溫度。因此，該封裝由於各種封裝結構和晶片材料的不同膨脹係數(CTE)而產生高應力，從而引起基板發生板彎、板翹或斷裂。該應力可導致半導體晶片的介電層產生斷裂/分層，並且導致IC產品失效(尤其是對於具有極低介電材料層的半導體晶片/晶圓而言)。減小應力的傳統方法是增大尺寸以及增加傳導凸塊的數量。然而，該方法由於凸塊跨距的限制以及IC金屬線路佈線區域的限制而不能實現。因此，所需要的是一種可以承受結構內部應力的封裝結構，以防止半導體晶片的介電層產生斷裂/分層並且用以提高 其可靠度。
本揭露的一些實施例提供了半導體結構，其包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面；以及傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段高度，並且每一個凸塊區段具有以該區段高度與該凸塊區段的平均截面面積的乘積定義的體積；其中該凸塊區段的該第一組的總體積與該凸塊區段的該第二組的總體積之比約在0.03和0.8之間。
本揭露的一些實施例提供了半導體結構，其包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面，其中該基板包括形成在其表面上的傳導路徑；傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸；在該傳導凸塊上的金屬封蓋層；導體將金屬封蓋層耦合至傳導路徑，其中傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段高度，並且每一個凸塊區段具有以該區段高度與該凸塊區段的平均截面面積的乘積定義的體積；其中該凸塊區段的該第一組的總體積與該凸塊區段的該第二組的總體積之比約在0.03和0.8之間。
本揭露的一些實施例提供了製造半導體結構的方法。其包括：提供具有主動表面的半導體晶片；在該半導體晶片的該主動表面上形成傳導凸塊；以及將該傳導凸塊耦合至基板，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中每一個凸塊區段在與該半導體晶片的該主動表面垂 直之方向上具有相同的區段高度，並且每一個凸塊區段具有以該區段高度與該凸塊區段的平均截面面積的乘積定義的體積。其中該凸塊區段的該第一組的總體積與該凸塊區段的該第二組的總體積之比約在0.03和0.8之間。
100‧‧‧半導體結構
101‧‧‧基板
102‧‧‧半導體晶片
103‧‧‧傳導凸塊
104‧‧‧導體
105‧‧‧金屬封蓋層
106‧‧‧主動表面
1011‧‧‧傳導元件
1012‧‧‧接觸墊
1013‧‧‧球墊
1014‧‧‧銲錫球
1015‧‧‧核心結構
1016‧‧‧增層結構
1017‧‧‧鍍通孔
1021‧‧‧凸塊下金屬(UBM)結構
1022‧‧‧結合墊
1023‧‧‧鈍化層
1024‧‧‧介電層
103s‧‧‧凸塊區段
A103s‧‧‧平均截面面積
H103s‧‧‧區段高度
1031‧‧‧凸塊區段第一組
1032‧‧‧凸塊區段第二組
800‧‧‧半導體結構
1001、1002、1003‧‧‧方法
PR1、PR2、PR3‧‧‧光阻層
為達到最佳理解效果，建議在閱讀本揭露時同時應閱讀以下具體描述。應理解的是，根據工業中的常規標準，各種特徵並未按比例示出。事實上，為更清楚地論述，各種特徵尺寸可任意地增大或減小。
圖1是根據本揭露的一個實施例示出的半導體結構的截面圖。
圖2是圖1中半導體結構的局部放大圖。
圖3是根據本揭露的一個實施例示出的傳導凸塊的截面圖。
圖4是根據本揭露的一個實施例示出的傳導凸塊的截面圖。
圖5是根據本揭露的一個實施例示出的傳導凸塊的截面圖。
圖6是根據本揭露的一個實施例示出的傳導凸塊的截面圖。
圖7A-7H是根據本揭露的一些實施例示出的傳導凸塊的截面圖。
圖8是根據本揭露的一個實施例示出的半導體結構的截面圖。
圖9是圖8中半導體結構的俯視圖。
圖10根據本揭露的一個實施例示出了製造半導體結構的 流程圖。
圖11A-11K根據本揭露的一個實施例示範性地示出了在半導體晶片上形成傳導凸塊的方法。
圖12A-12G根據本揭露的一個實施例示範性地示出了形成凸塊下金屬(UBM)結構的方法。
以下將詳細論述製造和使用本揭露的實施例。然而，應理解的是，該實施例提供了能夠在多種特定環境下實施的多個適用的發明構思。還應理解的是，本說明書提供了多個不同的實施方式或示例，其可用於實現各種實施例的不同特徵。以下所描述的零件和裝置的具體示例用以簡化本揭露。當然，這些只是示例並且旨在不局限於此。
以下將採用特定的文字論述附圖中所示出的實施例或示例。然而應理解的是，該實施例和示例旨在不局限於此。與本領域相關的技術人員可對本揭露的實施例進行任何替換和修改，並且可將本文所揭露的原理進一步應用於其它領域。
此外，應理解的是一些操作工藝和/或元件的結構可僅作簡要描述。同樣，也可增加額外的操作工藝和/或結構，並且在實施本請求項的同時也可移除或改變以下某些操作工藝和/或結構。因此，以下的描述應理解為僅代表了示例，並且並不旨在顯示要求一個或多個操作或結構。
另外，本揭露在各種示例中可重複參考數字和/或參考字母。該重複的目的在於簡明及清楚，但其本身並不決定所描述的各種實施例和/或構造之間的關係。
此外，空間上的相關術語，諸如“在...的下面”、“在...的下方”、“低於”、“在...的上方”以及“上面”等，此處可用於 簡單地描述如圖中所示的一個元件或特徵相對於另一(多個)元件或另一(多個)特徵的關係。該空間上的相關術語旨在包括除了圖中所描述的方向外，還包括在使用或操作中的元件的不同方向。另外，裝置可被定向(旋轉90度或以其它方向定向)，並且此處所用的空間上的相關描述符號可同樣作相應地說明。
現參考附圖，圖1是根據本揭露的一個實施例示出的半導體結構100的截面圖。如圖1所示，半導體結構100設置在倒置晶片構造(也稱為可掌握熔塌焊接高度之覆晶互連或C4)中。與封裝技術(諸如導線結合以及倦帶自動結合技術(TAB))相比，倒置晶片封裝在半導體晶片和基板之間具有較短的單一傳輸路徑，並且因此而具有較好的電性能。另外，倒置晶片封裝可設計為暴露半導體晶片的背面(不朝向基板的幹線表面之一)以增加散熱率。
根據圖1，半導體結構100包括半導體晶片102和基板101。半導體晶片102可通過傳導凸塊103(具有金屬封蓋層105)和導體104(例如，銲錫)直接與基板101結合。在封裝期間，半導體晶片102在其主動表面106上“倒置”，從而使傳導凸塊103在半導體晶片102和基板101之間形成電連接及機械連接。在由傳導凸塊103形成的間隙之間施加的底膠材料(未示出)用於進一步將半導體晶片102固定至基板101。在一個實施例中，導體104可由無鉛銲錫或共晶銲錫等製成。
半導體晶片102是一種包括半導體材料的結構。該半導體材料包括主體矽、半導體晶圓、矽上絕緣(SOI)基板或鍺矽基板。也可採用包含組III、組IV和組V元素的其它半導體材料。半導體晶片102還可包括多個絕緣結構(未示出)，諸如淺溝道絕緣(STI)結構或矽的局部氧化(LOCOS)結構。該絕緣結構可定義並且絕緣各種微電子元件(未示出)。該微電子元件可包括電晶體(例如，MOSFET)、互補性金屬氧化物半導體(CMOS)電晶體、雙極性接合電晶體(BJT)、 高壓電晶體、高頻電晶體、p型溝道和/或n型溝道場效電晶體(PFETs/NFETs)、二極體、電阻器、電容、電感器或其它適合的元件。這些微電子元件的製造工藝包括沉積、蝕刻、佈植、光刻、韌化或其它適合的工藝。這些微電子元件彼此互連以形成邏輯元件、存儲元件(例如，靜態隨機存取記憶器或SRAM)、無線電波(RF)元件、輸入/輸出(I/O)元件、系統積體晶片(SoC)元件、eFlash元件、微機電(MEMS)元件、類比元件、CMOS元件或其組合。
半導體晶片102可以是包括多個傳導層和多個介電層的積層結構。在一個實施例中，半導體晶片102可包括多個極低介電係數(ELK)的介電層1024(參見圖1)。ELK層1024具有小於約2.5的介電常數(所給出的SiO2的介電常數約為4)。ELK層1024可用於提供良好的電絕緣並且防止半導體102的相鄰傳導層之間發生串訊，並且也可用於減少元件的功率消耗。普通ELK材料包括多孔的低介電係數的材料(該材料具有高疏孔度)。
在一個實施例中，半導體晶片102包括形成在主動表面106上的結合墊1022。結合墊1022用於將外部電接觸電連接至半導體晶片102的微電子元件I/O中的一個。結合墊1022可包括鋁、銅或其合金。鈍化層1023形成在主動表面106上並且形成在結合墊1022的頂部上，用以提供結構支撐和物理絕緣。鈍化層1023能夠保護半導體晶片102免受機械損壞(顆粒/劃痕/污染)和其它化學腐蝕。鈍化層1023可用氮化矽(SiN)、二氧化矽(SiO2)、氮氧化矽(SiON)、聚亞酰胺(PI)、苯並環丁烯(BCB)、聚苯並惡唑(PBO)或其它絕緣材料製作而成。圖案化鈍化層1023，使其形成開口以暴露結合墊1022。如圖1所示的該開口的尺寸、形狀和位置，其目的僅在於圖示說明並且並不局限於此。
在一個實施例中，凸塊下金屬(UBM)結構1021(通常採用濺射、蒸發和鍍等)形成在結合墊1022的暴露部分上，其用於將 傳導凸塊103連接至結合墊1022。UBM結構1021可包括形成在結合墊1022上的金屬粘合層、防止擴散的障礙層以及用於連接傳導凸塊103的銲錫潤濕層(solder wettable layer)。UBM結構1021在傳導凸塊103和結合墊1022之間提供如下功能：凸塊連接、防止擴散以及適合的粘合。
返回至圖1，傳導凸塊103用於在半導體晶片102(UBM結構1021)和基板101(接觸墊1012)之間提供物理連接和電連接。傳導凸塊103可以是柱形形狀(例如，頸狀柱形)，並且該傳導凸塊103的材料可選自於：銅、金、銀、鋅、鉍、鎂、銻、銦以及其合金。採用銅作為傳導凸塊103的材料具有以下有益效果：使用銅柱作為結合元件不僅有助於實現具有凸塊橋接最小概率的密距，而且還減少電路的電容負載(電子互連)。銅柱提供了較高的可靠度，改進了電性能和熱性能。同時，在銲錫回流期間，當傳統的銲錫失效時，銅柱仍保持了其形狀。
在一個實施例中，金屬封蓋層105形成在導體104和傳導凸塊103之間。金屬封蓋層105可用作障礙層以防止傳導凸塊103中的金屬擴散至導體104(結合材料，諸如銲錫合金)中，其用於將基板101結合至傳導凸塊103，或用於防止導體104中的金屬擴散至傳導凸塊103中。防止金屬擴散可增加半導體封裝的可靠度和結合強度。金屬封蓋層105可包括鎳(Ni)、錫、錫-鉛合金(SnPb)、金(Au)、銀、鈀(Pd)、銦(In)、鎳-鈀-金合金(NiPdAu)、鎳-金合金(NiAu)、其它類似材料，或通過鍍法而沉積的合金。在一些實施例中，金屬封蓋層105可具有約1-10μm的厚度。在一些實施例中，金屬封蓋層105是多層結構。在一些實施例中，金屬封蓋層105是鎳膜或通過電鍍工藝、無電鍍工藝或浸鍍工藝而形成的鎳合金膜。
基板101可包括多層式基板、梯度式基板、混合定向式基 板和/或其組合等，從而使半導體封裝能夠容納更多的主動和被動零件以及主動和被動電路。提供傳導元件1011(例如，傳導插腳、傳導孔、傳導接線柱、填充材料或傳導線路)，以在垂直方向上形成傳導路徑。在一個實施例中，防焊膜1012圍繞球墊1013設置在基板101的底面上，其構造為接收外部端子(諸如銲錫球1014)，用於形成半導體結構的外部連接器。在一個實施例中，基板101包括PCB(印刷電路板)。
在一個實施例中，基板101可包括介電核心結構(層)1015和設置在該核心結構1015兩側上的增層結構(積層)1016。通過鍍通孔1017而完成兩個增層結構1016與核心結構1015的互連。鍍通孔1017可採用打孔機或雷射二者之一而形成，以切割通孔使其貫穿核心結構1015。鍍通孔1017可採用導體(諸如銅及其合金)電鍍而成，或採用其它傳導金屬及其合金電鍍而成，並且可用傳導插腳或填充材料填充該鍍通孔1017。增層結構1016可包括多個傳導層和多個絕緣層。增層結構1016可包括用於連接至傳導凸塊103或銲錫球1014的傳導元件1011(例如，傳導插腳或填充材料)。在一個實施例中，基板101可包括多個沒有核心結構的增層結構1016(即，基板101可形成為無芯基板)。由於無芯基板101不具有任何鍍通孔，所以增加了無芯封裝基板的佈線密度。另外，不安裝核心基板很容易降低了基板101的整體厚度。在一個實施例中，用於基板101的材料可選擇為能夠使基板101的彈性係數保持相對較低的材料，其允許在基板101和半導體晶片102之間的整體連接中具有更多的柔韌性，並且因此而有助於避免基板101發生板翹。在一個實施例中，用於基板101的材料可選自於(但不限於)環氧樹脂、多硫醇固化劑或三級胺加速固化劑。
應理解的是，傳統的倒置晶片封裝具有以下問題：在封裝工藝期間會經受不同的溫度。例如，隨著銲錫結合溫度和底膠固化溫度的冷卻而使不同溫度升高。這造成該封裝由於各種封裝結構和晶 片材料的不同膨脹係數(CTE)而產生高應力。進而，基板101在高溫中或在冷卻期間所經受的高應力可引起基板101發生板彎、板翹或斷裂。這種問題對於相對較大晶片而言會更加惡化。另外，該應力可導致半導體晶片的介電層產生斷裂/分層(尤其是對於具有ELK層的半導體晶片/晶圓而言，其由於用於ELK層的普通材料通常具有高疏孔度)。為解決該問題，本揭露的傳導凸塊103構造為頸狀柱形，該頸狀柱形(與具有均勻截面面積的傳導柱形凸塊的體積相比)具有不均勻的截面面積和減小的體積，從而使其能夠承受結構內部應力，以防止半導體晶片的介電層產生斷裂/分層並且用以提高其可靠度。
圖2-7進一步描述了傳導凸塊103的各種實施例的詳細構造。如圖2所示(圖2為圖1中半導體結構100的局部放大圖)，傳導凸塊103包括多個凸塊區段103s，其中每一個凸塊區段103s可具有平坦的柱形(盤形)形狀或平坦的錐形形狀。一般而言，傳導凸塊103的高度可以約為20μm至約50μm，並且傳導凸塊103的直徑可以約為30μm至約90μm。圖3是根據本揭露的一個實施例所示出的半導體凸塊103的截面圖。根據圖3，多個凸塊區段103s包括凸塊區段第一組1031和凸塊區段第二組1032。例如，如圖3中的實施例所示，傳導凸塊103包括6個凸塊區段，其中第一區段組1031具有3個凸塊區段103s，並且第二區段組1032也具有3個凸塊區段103s。關於該多個凸塊區段103s，其每一個凸塊區段103s在與半導體晶片102的主動表面106垂直的方向上具有相同的區段高度H103s。由於傳導凸塊103具有不均勻截面面積，因此每一個凸塊區段103s中的截面面積互不相同。為方便起見，每一個凸塊區段103s的平均截面面積A103s用於表示凸塊區段103s平行於主動表面106的平面尺寸。根據本揭露，第一區段組1031的每一個凸塊區段的平均截面面積A103s小於第二區段組1032的任一凸塊區段的平均截面面積A103s。另外，每一個凸塊區段103s具有以區段高度H103s與相 關凸塊區段的平均截面面積A103s的乘積定義的體積。
如上所述，與具有均勻截面面積的傳導柱形凸塊的體積相比，本揭露的傳導凸塊103具有不均勻的截面面積和減小的體積。根據本揭露，傳導凸塊103具有如下構造：第一區段組1031的總體積小於第二區段組1032的總體積。根據本揭露，第一和第二區段組1031和1032的總體積比(總體積比是指第一區段組1031的總體積與第二區段組1032的總體積之比)在約0.03和約0.8之間。在一個實施例中，兩組之間的總體積比在約0.03和約0.1之間。在一個實施例中，兩組之間的總體積比在約0.1和約0.5之間。在一個實施例中，兩組之間的總體積比在約0.5和約0.8之間。
圖4-6是根據本揭露的另一實施例示出的半導體凸塊103的截面圖。在圖4中，第一區段組1031夾在第二區段組1032的凸塊區段之間；同時，在圖5中，第二區段組1032夾在第一區段組1031的凸塊區段之間。
在圖6中，第一區段組1031包括彼此鄰接/相鄰的凸塊區段的組，並且第二區段組1032也包括彼此鄰接/相鄰的凸塊區段的組。第一區段組1031的所有凸塊區段可具有相同的平均截面面積，並且第二區段組1032的所有凸塊區段也可具有相同的平均截面面積。對於第一和第二區段組(其具有彼此鄰接/相鄰的凸塊區段)而言，第一區段組1031的總區段高度以H1031表示，並且第二區段組1032的總區段高度以H1032表示。在一個實施例中，H1031與H1032之比在約0.3和約1之間，即，H1031與“H1031和H1032之和”之比在約0.25和約0.5之間。在一個實施例中，H1031與H1032之比在約0.3和約0.7之間。在一個實施例中，H1031與H1032之比在約0.7和約1之間。
再次參考圖6，第一區段組1031的平均截面面積以A1031表示，並且第二區段組1032的平均截面面積以A1032表示。在一個實 施例中，A1031與A1032之比在約0.06和約0.65之間。在一個實施例中，A1031與A1032之比在約0.06和約0.1之間。在一個實施例中，A1031與A1032之比在約0.1和約0.3之間。在一個實施例中，A1031與A1032之比在約0.3和約0.65之間。
圖7A-7H是根據圖6中一些實施例所示的傳導凸塊的截面圖。在圖7A-7H中，第一區段組1031的凸塊區段整體形成為具有柱形或錐形的形狀，同樣，並且第二區段組1032的凸塊區段也整體形成為具有柱形或錐形的形狀。
圖8是根據本揭露的一個實施例所示的半導體結構800的截面圖。半導體結構800包括基板101和半導體晶片102。被圖案化的傳導線路107提供在基板101的表面(該表面朝向半導體晶片102的主動表面106)上。傳導凸塊103設置在傳導線路107上並且耦合至傳導線路107。傳導凸塊103可通過導體104耦合至傳導線路107。半導體晶片102和基板101通過傳導凸塊103電連接且彼此耦合。
圖9示出了圖8中半導體結構800的俯視圖。根據上述的凸塊在線路上(BOT)的結構，傳導凸塊103直接設置在基板101的傳導線路107上。BOT結構的有益效果包括滿足較小晶片面積的要求以及降低製造成本。傳導線路104可採用實質上純銅、鋁銅合金或其它金屬材料(諸如鎢、鎳、鈀、金和/或其合金)而形成。
再次參考圖8，傳導凸塊103可具有如圖2-7中所示的相同構造。在下文中，可參照圖2-7來論述圖8中的傳導凸塊103。在一個實施例中，圖8中的傳導凸塊103包括多個凸塊區段103s。多個凸塊區段103s包括凸塊區段第一組1031和凸塊區段第二組1032，其中每一個凸塊區段在與半導體晶片102的主動表面106垂直的方向上具有相同的區段高度。每一個凸塊區段103s具有平均截面面積，其中每一個第一區段組1031的平均截面面積小於每一個第二區段組1032的平均截面面 積。另外，每一個凸塊區段103s具有以區段高度與相關凸塊區段103s的平均截面面積的乘機定義的體積。根據本揭露，第一和第二區段組1031和1032的總體積比在約0.03和約0.8之間。在一個實施例中，第一區段組1031的總區段高度與第二區段組1032的總區段高度之比在約0.3和約1之間。在一個實施例中，第一區段組1031的平均截面面積與第二區段組1032的平均截面面積之比在約0.06和約0.65之間。
圖10是根據本揭露的一個實施例製造半導體的方法的流程圖。在操作1001中，提供了具有主動表面106的半導體晶片102。在操作1002中，傳導凸塊103形成在半導體晶片102的主動表面106上。在操作1003中，傳導凸塊103耦合至基板101。傳導凸塊103可具有如圖2-7所示的相同構造。在一個實施例中，傳導凸塊103具有多個凸塊區段103s。多個凸塊區段103s包括凸塊區段第一組1031合凸塊區段第二組1032，其中每一個凸塊區段在與半導體晶片102的主動表面106垂直的方向上具有相同的區段高度。每一個凸塊區段103s具有平均截面面積，其中每一個第一區段組1031的平均截面面積小於每一個第二區段組1032的平均截面面積。另外，每一個凸塊區段103s具有以區段高度與相關凸塊區段103s的平均截面面積的乘機定義的體積。根據本揭露，第一和第二區段組1031和1032的總體積比在約0.03和約0.8之間。在一個實施例中，第一區段組1031的總區段高度與第二區段組1032的總區段高度之比在約0.3和約1之間。在一個實施例中，第一區段組1031的平均截面面積與第二區段組1032的平均截面面積之比在約0.06和約0.65之間。
圖11A-11K根據本揭露的一個實施例示範性地示出了在半導體晶片上形成傳導凸塊的方法。在圖11A中，提供了具有結合墊1022的半導體晶片102，該結合墊1022形成在半導體晶片102的表面上，其中鈍化層1023形成在半導體晶片102和結合墊1022上，並且凸塊 下金屬(UBM)結構1021設置在結合墊1022的暴露部分上。在圖11B中，第一光阻層PR1塗覆在鈍化層1023和UBM結構1021上。在圖11C中，圖案化該第一光阻層PR1以暴露UBM結構1021。在一個實施例中，在第一光阻層PR1上提供具有預定義圖案(或開口)的光罩(未示出)，並且通過該光罩開啟在第一光阻層PR1上的UV光。在開啟后，圖案化該第一光阻層PR1，從而形成暴露UBM結構1021的第一開口1101，其中第一開口1101具有柱形或錐形的形狀。在圖11D中，第一凸塊區段103s通過濺射或鍍而形成在第一開口1101中。在圖11E中，第二光阻層PR2塗覆在第一光阻層PR1和第一凸塊區段103s上。在圖11F中，圖案化該第二光阻層以暴露第一凸塊區段103s，其中圖案化該第二光阻層以形成具有柱形或錐形形狀的第二開口1102。在圖11G中，第二凸塊區段103s通過濺射或鍍而形成在第二開口1102。應理解的是，第一凸塊區段103s的平均截面面積和區段高度與第二凸塊區段103s的平均截面面積和區段高度不同。在圖11H中，第三光阻層PR3塗覆在第二光阻層PR2和第二凸塊區段103s上。在圖11I中，圖案化該第三光阻層PR3以暴露第二凸塊區段103s，其中圖案化該第三光阻層PR3以形成第三開口1103。在圖11J中，金屬封蓋層105通過濺射或鍍而形成在第三開口1103中。在圖11K中，剝除光阻層PR1、PR2和PR3以形成包括第一和第二凸塊區段103s的傳導凸塊。
圖12A-12G根據本揭露的一個實施例示範性地示出了形成凸塊下金屬(UBM)結構的方法。在圖12A中，提供了具有結合墊1022的半導體晶片102，該結合墊1022形成在半導體晶102的表面上。在圖12B中，鈍化層1023形成在半導體晶片102和結合墊1022上。在圖12C中，圖案化該鈍化層1023以形成暴露結合墊1022的開口。在圖12D中，粘合層1021a通過濺射或鍍而形成在鈍化層1023和暴露的結合墊1022上。在圖12E中，障礙層1021b通過濺射或鍍而形成在粘合層1021a 上。在圖12F中，潤濕層1021c通過濺射或鍍而形成在障礙層1021b上。在圖12G中，圖案化該粘合層1021a、障礙層1021b和潤濕層1021c從而在暴露的結合墊1022上形成UBM結構1021(移除該三層的多餘部分)。圖案化該粘合層1021a、障礙層1021b和潤濕層1021c可包括：在潤濕層1021c上形成光阻層；圖案化該光阻層以暴露潤濕層1021c的一部分；移除(蝕刻)潤濕層1021c的該暴露部分，並且移除位於潤濕層1021c該暴露部分下方的障礙層1021b和粘合層1021a的部分；(採用丙酮、n-甲基吡咯烷酮溶剂(NMP)、二甲亚砜(DMSO)和氨乙基乙醇等)剝除光阻層。在一個實施例中，蝕刻UBM層的多餘部分包括濕蝕刻和干蝕刻。對於濕蝕刻而言，UBM層的多餘部分當浸泡在液相(“濕”)蝕刻劑中時而被溶解，該蝕刻劑必須是易於攪拌的以實現良好的工藝控制，其中濕蝕刻劑通常是均向的。對於干蝕刻而言，UBM層的多餘部分通過離子(通常是活性氣體(諸如碳氟化合物、氧氣、氯氣、三氯化硼)的等離子；有時添加了氮氣、氬氣、氦氣和其它氣體)而被轟擊。與用於濕蝕刻的多數化學濕蝕刻不同，干蝕刻工藝典型地定向或單向地蝕刻。干蝕刻工藝包括離子研磨(濺射蝕刻)、反應離子蝕刻(RIE)和深反應離子蝕刻(DRIE)等。
在上述的示例和說明中已充分地論述了本揭露的方法和特徵。應理解的是，在不背離本揭露精神的情況下，任何修改或改變旨在覆蓋本揭露的保護範圍。
此外，本申請的範圍並不旨在局限於說明書中所描述的事件、方式、方法和操作的工藝、機器、製造和組分的特殊實施例。本領域技術人員從目前存在的或以後將發展的事件、方式、方法或操作的本揭露、工藝、機器、製造和組分中的公開中可容易地理解：根據本揭露，可採用實施與此處所描述的相應實施例實質上相同的功能或實現與此處所描述的相應實施例實質上相同的結果。因此，所附請 求項旨在包括諸如事件、方式、方法或操作的工藝、機械、製造和組分的範圍。另外，每一個請求項構成一單獨的實施例，並且各請求項和實施例的組合均在本揭露的範圍內。
100‧‧‧半導體結構
101‧‧‧基板
102‧‧‧半導體晶片
103‧‧‧傳導凸塊
104‧‧‧導體
105‧‧‧金屬封蓋層
106‧‧‧主動表面
1011‧‧‧傳導元件
1012‧‧‧接觸墊
1013‧‧‧球墊
1014‧‧‧銲錫球
1015‧‧‧核心結構
1016‧‧‧增層結構
1017‧‧‧鍍通孔
1021‧‧‧凸塊下金屬(UBM)結構
1022‧‧‧結合墊
1023‧‧‧鈍化層
1024‧‧‧介電層

Claims (10)

  1. 一種半導體結構，其包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面，以及傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中該凸塊區段的該第一組和凸塊區段的該第二組之每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段厚度，並且該每一個凸塊區段具有以該相同區段厚度與該每一凸塊區段的平均截面面積的乘積定義的體積，其中該凸塊區段的該第二組被分成一第一段和一第二段，該凸塊區段的該第一組被夾在該凸塊區段的該第二組的該第一段和該第二段之間，及該凸塊區段的該第一組之平均截面面積小於該凸塊區段的該第二組的該第一段和該第二段之平均截面面積。
  2. 根據請求項1所述的半導體結構，其中該凸塊區段的該第一組中的每一個的該平均截面面積小於該凸塊區段的該第二組中的每一個的該平均截面面積。
  3. 根據請求項1所述的半導體結構，其中該凸塊區段的該第一組包括一組相鄰的凸塊區段，並且該凸塊區段的該第二組包括一組相鄰的凸塊區段。
  4. 根據請求項1所述的半導體結構，其中每一個凸塊區段具有柱形或錐形的形狀。
  5. 根據請求項1所述的半導體結構，其中金屬封蓋層設置在該傳導凸塊和該基板之間。
  6. 一種半導體結構，其包括：半導體晶片；基板，該基板朝向該半導體晶片的主動表面，其中該基板包括形成在其表面上的傳導線路；傳導凸塊，該傳導凸塊從該半導體晶片的主動表面朝著該基板延伸；在該傳導凸塊上的金屬封蓋層；導體，該導體將該金屬封蓋層耦合至該傳導線路，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中該凸塊區段的該第一組和凸塊區段的該第二組之每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段厚度，並且該每一個凸塊區段具有以該相同區段厚度與該每一凸塊區段的平均截面面積的乘積定義的體積，其中該凸塊區段的該第一組被分成一第一段和一第二段，該凸塊區段的該第二組被夾在該凸塊區段的該第一組的該第一段和該第二段之間，及該凸塊區段的該第二組之平均截面面積大於該凸塊區段的該第一組的該第一段和該第二段之平均截面面積。
  7. 根據請求項6所述的半導體結構，其中該凸塊區段的該第一組包括一組相鄰的凸塊區段，並且該凸塊區段的該第二組包括一組相鄰的凸塊區段，並且其中該凸塊區段的該第一組和該凸塊區段的該第二組都形成為柱形或錐形。
  8. 一種製造半導體結構的方法，其包括：提供具有主動表面的半導體晶片；在該半導體晶片的該主動表面上形成傳導凸塊；以及將該傳導凸塊耦合至基板，其中該傳導凸塊包括：多個凸塊區段，該多個凸塊區段包括凸塊區段的第一組和凸塊區段的第二組，其中該凸塊區段的該第一組和凸塊區段的該第二組之每一個凸塊區段在與該半導體晶片的該主動表面垂直之方向上具有相同的區段厚度，並且該每一個凸塊區段具有以該相同區段厚度與該每一凸塊區段的平均截面面積的乘積定義的體積，其中該凸塊區段的該第二組被分成一第一段和一第二段，該凸塊區段的該第一組被夾在該凸塊區段的該第二組的該第一段和該第二段之間，及該凸塊區段的該第一組之平均截面面積小於該凸塊區段的該第二組的該第一段和該第二段之平均截面面積。
  9. 根據請求項8所述的方法，其中在該半導體晶片上形成該傳導凸塊包括：用不同的操作而形成不同的凸塊區段；在該半導體晶片上設置結合墊；在該半導體晶片和該結合墊上形成鈍化層；圖案化該鈍化層以暴露該結合墊；在該暴露的結合墊上形成凸塊下金屬(UBM)結構；或將該傳導凸塊耦合至該UBM結構。
  10. 根據請求項8所述的方法，其中將該傳導凸塊耦合至基板包括：在該傳導凸塊上形成金屬封蓋層；以及 通過導體將該金屬封蓋層耦合至該基板。
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