TW201419394A - 承載晶圓與其製造方法、封裝半導體元件之製造方法 - Google Patents

承載晶圓與其製造方法、封裝半導體元件之製造方法 Download PDF

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TW201419394A
TW201419394A TW102138194A TW102138194A TW201419394A TW 201419394 A TW201419394 A TW 201419394A TW 102138194 A TW102138194 A TW 102138194A TW 102138194 A TW102138194 A TW 102138194A TW 201419394 A TW201419394 A TW 201419394A
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carrier wafer
glass layer
thermal expansion
coefficient
layer
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TW102138194A
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TWI655683B (zh
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Chen-Shien Chen
Mirng-Ji Lii
Chen-Hua Yu
Yen-Chang Hu
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Taiwan Semiconductor Mfg
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    • B32B17/00—Layered products essentially comprising sheet glass, or glass, slag, or like fibres
    • B32B17/06—Layered products essentially comprising sheet glass, or glass, slag, or like fibres comprising glass as the main or only constituent of a layer, next to another layer of a specific material
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Abstract

本發明提供一種承載晶圓，包括：一第一玻璃層；以及一第二玻璃層耦合到該第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數，且其中該第二玻璃層包括一第二熱膨脹係數。

Description

承載晶圓與其製造方法、封裝半導體元件之製造方法
本發明係有關於一種半導體元件，且特別是有關於一種承載晶圓與其製法。
半導體元件廣泛使用於各種電子應用中，例如個人化電腦、行動電話、數位相機以及其他電子元件。半導體元件的製造通常是藉由在半導體基板上依序沉積絕緣層或介電層、導電層以及半導體材料層，並且利用微影技術(lithography)圖案化所形成的各種材料層，以形成電路零件及組件於半導體基板上。
通常是在一個單一半導體晶圓上製造數十個或數百個積體電路。藉由沿著切割線(scribe line)切割積體電路以分割成單一晶粒。舉例而言，在多晶片模組(multi-chip modules)中，或在其他的封裝類型中，接著將分別封裝單一晶粒。
藉由持續降低最小特徵尺寸(minimum faeature size)，半導體工業持續改善各種電子組件(例如電晶體、二極體、電阻、電容等等)的集積密度(integration density)，如此一來，可使更多元件整合於一特定區域中。在一些應用中，這些 尺寸較小的電子組件也僅需要使用較小型封裝即可，其中這些較小型封裝所需使用的區域較傳統的封裝更小。
就半導體元件的應用而言，近來所發展的一種較小型封裝技術為晶圓級封裝層疊(wafer level packaging,WLPs)。舉例而言，在半導體元件的應用方面，近來所發展的其他封裝技術包括三維積體電路(three dimensional integrated circuit,3DIC)與封裝層疊(package on package,PoP)。對於部份封裝製程而言，承載晶圓(carrier wafer)在封裝過程中作為一個臨時安裝或支撐表面使用。
本發明提供一種承載晶圓，包括：一第一玻璃層；以及一第二玻璃層耦合到該第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數，且其中該第二玻璃層包括一第二熱膨脹係數。
本發明另提供一種承載晶圓之製造方法，包括：提供一第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數；以及耦合一第二玻璃層到該第一玻璃層，其中該第二玻璃層包括一第二熱膨脹係數。
本發明亦提供一種封裝半導體元件之製造方法，包括：耦合複數個積體電路晶粒到一承載晶圓之上，其中該承載晶圓包括一第一玻璃層耦合到一第二玻璃層；形成一封裝系統於每一個該些積體電路晶粒及該承載晶圓之上，以及移除該承載晶圓。
100a‧‧‧第一玻璃層
100b‧‧‧第二玻璃層
100c‧‧‧玻璃層
100d‧‧‧玻璃層
102‧‧‧膠黏劑
104‧‧‧熱源
106‧‧‧壓力
110‧‧‧承載晶圓
110’‧‧‧承載晶圓
112‧‧‧承載晶圓之形成製程
114a‧‧‧研磨製程
114b‧‧‧研磨製程
116‧‧‧對準特徵結構
117‧‧‧區域
118‧‧‧區域
119‧‧‧區域
120‧‧‧黏合劑
122‧‧‧絕緣層
124‧‧‧晶種層
126‧‧‧乾膜
128‧‧‧組裝體通孔(through assembly vias,TAVs)
130‧‧‧積體電路晶粒
132‧‧‧黏合劑
134‧‧‧接觸墊
135‧‧‧絕緣材料
136‧‧‧模造成型化合物
138‧‧‧第一重新分配層
140‧‧‧第二重新分配層
150‧‧‧封裝半導體元件
152‧‧‧封裝系統
154‧‧‧切割線
160‧‧‧封裝半導體元件的方法流程圖
162‧‧‧耦合積體電路晶粒到承載晶圓，其中承載晶圓包括第 一玻璃層耦合到第二玻璃層
164‧‧‧形成封裝系統於積體電路晶粒及承載晶圓之上
166‧‧‧移除承載晶圓
d1‧‧‧第一玻璃層之厚度
d2‧‧‧第二玻璃層之厚度
d3‧‧‧承載晶圓之總厚度
第1圖至第3圖為一系列剖面圖，用以顯示製造承載晶圓的方法。
第4圖為第3圖所示之承載晶圓的俯視圖。
第5圖為一承載晶圓的剖面圖。
第6圖為一圖表，顯示承載晶圓及承載晶圓之玻璃層的熱膨脹係數(CTE)。
第7圖至第14圖為一系列剖面圖，用以顯示使用本文所描述之承載晶圓的方法。
第15圖為一流程圖，用以顯示封裝半導體元件的方法。
本發明所揭露的部份實施例係關於用於封裝半導體元件的承載晶圓(carrier wafer)。本發明將描述新穎的承載晶圓、及其製造方法以及將其用於半導體元件的封裝方法。
依據本發明所揭露之部份實施例，第1圖至第3圖為一系列剖面圖，用以顯示製造承載晶圓110(請參照第2圖)的方法。首先請參照第1圖，依據本發明所揭露之實施例，第1圖為一剖面圖，顯示第一玻璃層100a以及第二玻璃層100b，其中第二玻璃層100b耦合到第一玻璃層100a。舉例而言，第一玻璃層100a及第二玻璃層100b包括玻璃材料，例如硼矽酸鹽玻璃(borosilicate glass)、鋁矽酸鹽玻璃(alumino-silicate glass)、鹼基鋇矽酸鹽玻璃(alkali-barium silicate glass)或石英(quartz)。舉例而言，在本發明之部份實施例中，第一玻璃層100a及第二玻璃層100b可包括主要成分SiO2，一個或複數個其他成分，以 實現所需的玻璃特性。此外，第一玻璃層100a及第二玻璃層100b可包括其他材料。
第一玻璃層100a包括厚度為尺寸d1，其中尺寸d1為約1.2mm或小於1.2mm。第二玻璃層100b包括一厚度為尺寸d2，其中尺寸d2為約1.2mm或小於1.2mm。在本發明之部份實施例中，尺寸d2基本上與尺寸d1相同。在其他實施例中，尺寸d2與尺寸d1不同。此外，尺寸d1及d2可包括其他數值。
第一玻璃層100a包括第一熱膨脹係數(coefficient of thermal expansion,CTE)，以及第二玻璃層100b包括第二熱膨脹係數。在本發明之部份實施例中，第二玻璃層100b之第二熱膨脹係數不同於第一玻璃層100a之第一熱膨脹係數。舉例而言，依據本發明所揭露之部份實施例，藉由選擇第一玻璃層100a及第二玻璃層100b的材料，以達到所需的整體熱膨脹係數(desired overall CTE)，符合承載晶圓110預定的整體熱膨脹係數值，本文將針對此部份進一步說明。舉例而言，在本發明之部份實施例中，第一玻璃層100a之第一熱膨脹係數及第二玻璃層100b之第二熱膨脹係數包括約5、小於5、7或大於7。此外，在其他實施例中，第一熱膨脹係數及第二熱膨脹係數可包括其他數值，且第二熱膨脹係數基本上(substantially)可與第一熱膨脹係數相同。
第2圖為一剖面圖，用以顯示包括第一玻璃層100a及第二玻璃層100b的複合承載晶圓(composite carrier wafer)110。依據部份實施例，可使用熱接合製程(thermal bonding process)、氫鍵接合製程(hydrogen bonding process)、 壓力接合製程(pressure bonding process)、膠黏劑黏接合製程(gluing process)及/或上述方法之組合，將第二玻璃層100b耦合到第一玻璃層100a。舉例而言，膠黏劑102可用於將第一玻璃層100a與第二玻璃層100b接合在一起。舉例而言，膠黏劑102可包括接著劑(adhesive)或膠帶(tape)。在本發明之部份實施例中，施加膠黏劑102之前，可對第一玻璃層100a及第二玻璃層100b其中之一實施塗轉塗佈(spin-coating)，或對第一玻璃層100a及第二玻璃層100b兩者皆實施塗轉塗佈。舉例而言，膠黏劑102可包括一材料，例如苯並環丁烯(benzocyclobutene,BCB)或SU-8，其中膠黏劑102可包括環氧樹脂(epoxy resin)、γ-丁內酯(gamma butyrolactone)及三芳香基鋶鹽(triaryl sulfonium salt)，此外，膠黏劑102亦可使用其他材料。在熱接合製程的接合步驟中，可將第一玻璃層100a及第二玻璃層100b暴露於熱源104中。舉例而言，第一玻璃層100a及第二玻璃層100b可被加熱至約100℃~約250℃。此外，也可使用其他的溫度。在壓力接合製程中，也可使用壓力106將第一玻璃層100a及第二玻璃層100b接合在一起。舉例而言，壓力106的大小可包括約20到100KN並持續一段預定的時間。此外，也可使用其他數量的壓力106。舉例而言，可使用夾具(clamp)或其他器械施加壓力106，或利用在一腔室中所施加的內部壓力施加壓力106。舉例而言，在本發明之部份實施例中，可使用壓力、氫及/或熱源104，藉由凡德瓦力(Van der Waal’s force)的作用將第一玻璃層100a及第二玻璃層100b接合在一起。此外，可使用其他類型的接合製程。
在本發明之部份實施例中，進行接合製程之後，承載晶圓110包括總厚度為尺寸d3，其中尺寸d3為約1.5mm或小於1.5mm。在其他實施例中，尺寸d3可為約0.85mm。此外，尺寸d3的可包括其他數值。在本發明之部份實施例中，複合承載晶圓110並未包括膠黏劑102。
在本發明之部份實施例中，在耦合第二玻璃層100b到第一玻璃層100a之後，分別利用研磨製程114a或研磨製程114b研磨第一玻璃層100a及/或第二玻璃層100b，如第3圖所示。舉例而言，研磨製程或製程114a及/或114b用於製備承載晶圓110的表面或複數個表面。在本發明之部份實施例中，利用形成製程(forming process)112形成承載晶圓110，同樣顯示於第3圖中。形成製程112包括研磨及/或平坦化(smoothing)承載晶圓110的邊緣，使其成為預定的尺寸及形狀，藉此重新整形(re-shaping)承載晶圓110之第一玻璃層100a及第二玻璃層100b的邊緣。在本發明之部份實施例中，從俯視方向觀察，承載晶圓110的形狀基本上是圓形的，如第4圖所示。
第4圖為第3圖所示之承載晶圓110的俯視圖。在接合製程之後，對準特徵結構(alignment feature)116形成於第一玻璃層100a及第二玻璃層100b的邊緣上，其中對準特徵結構116包括凹口(notch)或其他類型的對準特徵。複數個對準特徵116可交錯地形成於承載晶圓110的邊緣上，圖中未顯示。在本發明之部份實施例中，承載晶圓110可包括直徑為約300mm。此外，承載晶圓110可包括其他的大小或尺寸。
依據其他實施例，第5圖為一承載晶圓110的剖面 圖。承載晶圓110是一個複合的晶圓(composite wafer)，包括複數個玻璃層100a、100b、100c及100d。四個玻璃層100a、100b、100c及100d顯示在第5圖中，然而，依據本發明所揭露之實施例，在承載晶圓100中包括兩個或兩個以上的玻璃層100a、100b、100c及100d。在本發明之部份實施例中，至少一個第三(third)玻璃層100c及100d耦合到第二玻璃層100b或第一玻璃層100a。在承載晶圓110中亦可包括多於四個玻璃層100a、100b、100c及100d。舉例而言，在本發明之部份實施例中，可依序將玻璃層100a、100b、100c及100d接合在一起，或是將玻璃層100a、100b、100c及100d的整體堆疊(entire stack)同時接合在一起。
第6圖為一圖表，顯示承載晶圓110及承載晶圓110之玻璃層100a、100b、100c及100d的熱膨脹係數(CTE)。一些目前可用的市售玻璃層之厚度及熱膨脹係數(CTE)繪製在此圖表中。來自複數個供應商V1、V2、V3、V4的市售玻璃層，以玻璃層的熱膨脹係數(單位：ppm/°K)對玻璃層的厚度(單位：mm)作圖，獲得第6圖。區域118顯示的熱膨脹係數範圍約在4.8-7.0之間，在區域118中，目前尚未有可用的市售玻璃層可以購買。
此方法的優點在於，所製造的複合承載晶圓110具有複數個玻璃層100a及100b，如第2圖所示，或是具有複數個玻璃層100a、100b、100c及/或100d，如第5圖所示，可使承載晶圓110具有落入區域118(如第6圖的圖表所示)中的整體熱膨脹係數。由於部份的封裝系統或整體封裝系統的熱膨脹係數落 入此範圍內，而在封裝應用領域中需要落於該範圍內的熱膨脹係數，因此元件的熱膨脹係數落於該範圍內是非常有利的。本發明所揭露的實施例提供之封裝系統材料的熱膨脹係數是接近或精確匹配的(exact matching of CTE)。舉例而言，在本發明之部份實施例中，承載晶圓110包括整體熱膨脹係數介於約3-11的範圍內。此外，此整體熱膨脹係數可包括其他數值。
舉例而言，第一玻璃層100a可包括在第6圖的圖表上所示的區域117，其中區域117具有熱膨脹係數為約3.8，及第二玻璃層100b可包括在第6圖的圖表上所示的區域119，其中區域119具有熱膨脹係數為約8.0，使承載晶圓110的整體熱膨脹係數為約5.9。此方法的優點在於，可選擇承載晶圓110的玻璃層100a、100b、100c及100d之厚度及熱膨脹係數的各種不同組合，藉以達到所需的承載晶圓110之整體熱膨脹係數值，使承載晶圓110之整體熱膨脹係數值落在區域118內，或低於或高於區域118的熱膨脹係數值。可利用第6圖的圖表選擇玻璃層100a、100b、100c及100d，以達到所需的複合承載晶圓110之整體熱膨脹係數值，並實現更寬的製程容許度(process window)。
依據本發明所揭露之部份實施例，第7圖至第14圖為一系列剖面圖，用以顯示使用本文所描述之承載晶圓110的方法。承載晶圓110用於封裝半導體元件，例如顯示於第10圖至第14圖中的積體電路晶粒130。雖然在第10圖至第14圖中僅顯示一個積體電路晶粒130，然而，依據本發明所揭露之部份實施例，複數個積體電路晶粒130同時封裝在承載晶圓110的表 面上方。移除承載晶圓110之後，切割封裝積體電路晶粒130成單獨的封裝半導體元件，此部份於下文中將進一步描述。
在第7圖中，首先提供本文所述的承載晶圓110，其中此承載晶圓110包括複數個玻璃層100a、100b、100c及/或100d，以達到特定封裝系統所需的熱膨脹係數。在本文中，承載晶圓110亦稱為第一承載晶圓110。黏合劑(adhesive)120形成於承載晶圓110之，其中黏合劑120包括膠黏劑(glue)或膠帶(tape)。絕緣層122形成於黏合劑120之上，其中絕緣層122包括聚苯噁唑(polybenzoxazole,PBO)、聚亞醯胺(polyimide)或其他材料。晶種層(seed layer)124形成於絕緣層122之上。晶種層124包括一金屬，此金屬在電鍍製程中的功能是作為晶種，藉以形成組裝體通孔(through assembly vias,TAVs)128(參照第8圖)。
在第8圖中，乾膜126形成於晶種層122之上，其中乾膜126包括一絕緣材料。使用微影製程圖案化乾膜126，在乾膜126中留下形成組裝體通孔(TAVs)128圖案。在本發明之部份實施例中，使用微影製程圖案化乾膜126，藉由在乾膜126之上沉積一光阻層(圖中未顯示)，並且將光阻層暴露於光源或能量之下，其中此光源或能量係來自於具有所需圖案形成於其上的光罩(lithography mask)所反射。顯影光阻層，並且灰化(ashed)或蝕刻移除部份的光阻層，留下已圖案化的光阻層於乾膜126的頂部之上。接著利用光阻層作為蝕刻罩幕(etch mask)，蝕刻移除乾膜126的暴露部份。接著移除光阻層。又例如，也可使用直接圖案化製程(direct patterning process)圖案化乾膜126。
利用電鍍製程形成組裝體通孔(TAVs)128於乾膜 126的圖案中。在本發明之部份實施例中，組裝體通孔(TAVs)128包括銅(Cu)或銅合金。在本發明之部份實施例中，從俯視的方向觀察，組裝體通孔(TAVs)128包括圓形，橢圓形，正方形或矩形的形狀。此外，組裝體通孔(TAVs)128可包括其他材料及其他形狀。接著移除乾膜126，如第9圖所示。
接著使用黏合劑132將積體電路晶粒130接合到晶種層124，其中黏合劑132包括膠黏劑(glue)或膠帶(tape)，如第10圖所示。舉例而言，積體電路晶粒130包括形成於半導體基板之上的半導體電路，其中半導體基板包括矽或其他類型的半導體材料。積體電路晶粒130包括主動元件或電路，圖中未顯示，其中主動元件或電路可包括電晶體(transistors)、二極體(diodes)、電容(capacitors)、電感(inductors)及其他類型的元件。舉例而言，積體電路晶粒130可包括記憶體元件(memory device)、邏輯元件(logic device)或其他類型的電路。積體電路晶粒130包括複數個接觸墊134設置於絕緣材料135之中，其中絕緣材料135形成於積體電路晶粒130的頂部表面之上。舉例而言，接觸墊134包括銅、銅合金或其他金屬或材料。
同樣顯示於第10圖中，模造成型化合物(molding compound)136形成於積體電路晶粒130、組裝體通孔(TAVs)128及晶種層124的暴露部份之上。如第11圖所示，對模造成型化合物136進行化學機械研磨，以暴露組裝體通孔(TAVs)128的頂部表面以及積體電路晶粒130之接觸墊134的頂部表面。
如第12圖所示，第一重新分配層(RDL)138形成於模造成型化合物136之上，組裝體通孔(TAVs)128的暴露頂部表 面及積體電路晶粒130的接觸墊134之上。第一重新分配層138包括一層或複數層絕緣材料層及一層或複數層導電線層，圖中未顯示。舉例而言，導電線層可包括銅、鋁及其合金或其他材料。舉例而言，絕緣材料層可包括二氧化矽(silicon dioxide)、氮化矽(silicon nitride)、其他絕緣體或上述材料之組合。舉例而言，第一重新分配層層138可包括扇形展開區域(fan-out regions)，圖中未顯示，其中此扇形展開區域適於扇形展開積體電路晶粒130之接觸墊134的足跡範圍(footprint)，在本發明之部份實施例中的擴大到更大的足跡範圍(footprint)。在本發明之部份實施例中，第一重新分配層138可包括凸塊下方金屬化層(under-ball metallization layer,UBM)於其頂部表面上方，用以耦合複數個焊料凸塊(solder bumps)或焊料球(solder balls)，圖中亦未顯示。舉例而言，在本發明之部份實施例中，第一重新分配層138的部份將位於積體電路晶粒130上的接觸墊134電性連接到組裝體通孔(TAVs)128。
同樣顯示於第12圖中，接著承載晶圓110'耦合到第一重新分配層138。承載晶圓110'在本文中也稱為第二承載晶圓110'。在本發明之部份實施例中，第二個承載晶圓110'可包括複數個玻璃層100a、100b、100c及100d，其中複數個玻璃層100a、100b、100c及100d與本文所述用於第一承載晶圓110的複數個玻璃層100a、100b、100c及100d相似或不同。在其他實施例中，第二承載晶圓110'包括單一的玻璃層。在其他實施例中，第二承載晶圓110'包括複數個玻璃層100a、100b、100c及100d，以及第一承載晶圓110包括單一的玻璃層。依據本發 明所揭露的部份實施例，至少第一承載晶圓110及第二承載晶圓110'的其中之一包括複數個玻璃層100a、100b、100c及100d。
如第13圖所示，當第二承載晶圓110'接合到第一重新分配層138之後，使用去接合製程(de-bonding process)移除第一承載晶圓110。也使用一個或複數個蝕刻製程或去接合製程(de-bonding process)移除黏合劑120、絕緣層122及晶種層124。接著，第二重新分配層140形成於模造成型化合物136的底部表面、組裝體通孔(TAVs)128暴露的底部表面以及積體電路晶粒130的底部表面之上。舉例而言，如第14圖所示，第二重新分配層140可包括與上述第一重新分配層138相似的材料層。接著使用去接合製程(de-bonding process)移除第二承載晶圓110'。
封裝半導體元件150包括封裝系統152及積體電路晶粒130。在本發明之部份實施例中，形成於體電路晶粒130之上的封裝系統152包括第一重新分配層138及第二重新分配層140。在其他實施例中，如在第14圖中虛線部份所示，封裝系統152僅包括第一重新分配層138。封裝系統152包括顯示於第14圖中除了積體電路晶粒130之外的組件，亦即，使用封裝系統152封裝積體電路晶粒130。對封裝系統152而言，組裝體通孔(TAVs)128提供垂直連接，例如，介於第一重新分配層138及第二重新分配層140之間的垂直連接。在本發明之部份實施例中，對封裝系統152而言，第一重新分配層138及第二重新分配層140提供水平連接。
在第7圖到第14圖所示的製造流程之後，沿著切割線154分割包括封裝半導體元件150的封裝積體電路晶粒130，如第14圖所示。舉例而言，沿著切割線154分割設置於積體電路晶粒130之上的封裝系統，以形成複數個獨立的封裝半導體元件150。藉由耦合複數個焊料凸塊或焊料球到第一重新分配層138及/或第二重新分配層140，可以耦合每一個封裝半導體元件150到另一個封裝半導體元件150。接著，可將焊料凸塊或焊料球耦合到本文所述之另一個封裝半導體元件150的重新分配層138或重新分配層140，或將焊料凸塊或焊料球耦合到另一種類型的封裝半導體元件，以形成一個封裝體層疊(package-on-package,PoP)元件(圖中未顯示)。
依據本發明所揭露之部份實施例，第15圖為一流程圖，用以顯示封裝半導體元件的方法160。在步驟162中，耦合積體電路晶粒130到承載晶圓110，其中承載晶圓110包括第一玻璃層100a耦合到第二玻璃層100b(也可參照第10圖)。在步驟164中，封裝系統152形成於積體電路晶粒及承載晶圓110之上(第14圖)。在步驟166中，移除承載晶圓110(第12圖及第13圖)。
本發明所揭露的某些實施例包括形成複合承載晶圓110的方法，其中複合承載晶圓110具有複數個玻璃層100a、100b、100c及/或100d，同時也包括形成承載晶圓110的方法，其中承載晶圓110包括複數個玻璃層100a、100b、100c及100d。本發明所揭露的部份實施例包括使用此新穎承載晶圓110封裝半導體元件的方法。
本發明所揭露之部份實施例的優點包括提供新穎的複合承載晶圓110，其中複合承載晶圓110包括複數個玻璃層100a、100b、100c及/或100d。由本文所描述的部份實施例中，可以實現承載晶圓(Carrier wafer)110具有與各種封裝系統及結構的熱膨脹係數值基本上等效(substantially equivalent)的熱膨脹係數。在承載晶圓110的結構中包括複數個玻璃層100a、100b、100c及100d，可實現承載晶圓110之熱膨脹係數值的可調整性。使熱膨脹係數與封裝系統的熱膨脹係數相匹配的能力，能夠達到封裝半導體元件150的翹曲降低(warpage reduction)、翹曲優化(warpage optimization)及翹曲控制(warpage control)，並且也可實現更廣泛的凸塊製程限度(bumping process margin)，例如，後續焊料凸塊形成於第一重新分配層138或第二重新分配層140之上。本方法的優點在於，能夠使承載晶圓110的整體熱膨脹係數落於有利的範圍，此有利的範圍是目前市售的單層承載晶圓所無法實現的熱膨脹係數範圍。新型承載晶圓110的結構及設計易於與封裝製造流程結合。
依據本發明所揭露的部份實施例，提供一承載晶圓，包括：一第一玻璃層，以及一第二玻璃層耦合到該第一玻璃層。該第一玻璃層包括一第一熱膨脹係數，以及該第二玻璃層包括一第二熱膨脹係數。
依據本發明所揭露的其他實施例，提供一承載晶圓的製造方法，包括：提供一第一玻璃層，以及耦合一第二玻璃層到該第一玻璃層。該第一玻璃層包括一第一熱膨脹係數， 以及該第二玻璃層包括一第二熱膨脹係數。
依據本發明所揭露的其他實施例，提供一封裝半導體元件的製造方法，包括：提供一承載晶圓，其中該承載晶圓包括一第一玻璃層耦合到一第二玻璃層。此封裝半導體元件的製造方法尚包括：耦合複數個積體電路晶粒到該承載晶圓之上，形成一封裝系統於每一個該些複數個積體電路晶粒及該承載晶圓之上，以及移除該承載晶圓。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
160‧‧‧封裝半導體元件的方法流程圖
162‧‧‧耦合積體電路晶粒到承載晶圓，其中承載晶圓包括第 一玻璃層耦合到第二玻璃層
164‧‧‧形成封裝系統於積體電路晶粒及承載晶圓之上
166‧‧‧移除承載晶圓

Claims (10)

  1. 一種承載晶圓，包括：一第一玻璃層；以及一第二玻璃層耦合到該第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數，且其中該第二玻璃層包括一第二熱膨脹係數。
  2. 如申請專利範圍第1項所述之承載晶圓，其中該第一玻璃層包括一第一厚度，且其中該第二玻璃層包括一第二厚度，其中該第二厚度基本上與該第一厚度相同或不同。
  3. 如申請專利範圍第1項所述之承載晶圓，其中該第二熱膨脹係數與該第一熱膨脹係數不同或相同。
  4. 如申請專利範圍第1項所述之承載晶圓，其中該承載晶圓包括一整體熱膨脹係數介於約3-11的範圍內。
  5. 如申請專利範圍第1項所述之承載晶圓，其中該第一熱膨脹係數及第二熱膨脹係數包括約5、小於5、7或大於7。
  6. 一種承載晶圓之製造方法，包括：提供一第一玻璃層，其中該第一玻璃層包括一第一熱膨脹係數；以及耦合一第二玻璃層到該第一玻璃層，其中該第二玻璃層包括一第二熱膨脹係數。
  7. 如申請專利範圍第6項所述之承載晶圓之製造方法，尚包括耦合至少一第三玻璃層到該第二玻璃層或該第一玻璃層。
  8. 如申請專利範圍第7項所述之承載晶圓之製造方法，尚包括選擇該第一玻璃層之該第一熱膨脹係數，以及該第二玻璃 層之該第二熱膨脹係數，以達到承載晶圓預定的整體熱膨脹係數值。
  9. 一種封裝半導體元件之製造方法，包括：耦合複數個積體電路晶粒到一承載晶圓之上，其中該承載晶圓包括一第一玻璃層耦合到一第二玻璃層；形成一封裝系統於每一個該些積體電路晶粒及該承載晶圓之上；以及移除該承載晶圓。
  10. 如申請專利範圍第9項所述之封裝半導體元件之製造方法，其中形成該封裝系統包括形成複數個組裝體通孔(through assembly vias,TAVs)於該承載晶圓之上，接合每一個該些積體電路晶粒到該承載晶圓，形成一模造成型化合物(molding compound)於該些組裝體通孔(TAVs)及該些積體電路晶粒之上，以及形成一第一重新分配層(RDL)於該模造成型化合物之上。
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