TW201905991A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法

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Publication number
TW201905991A
TW201905991A TW107107757A TW107107757A TW201905991A TW 201905991 A TW201905991 A TW 201905991A TW 107107757 A TW107107757 A TW 107107757A TW 107107757 A TW107107757 A TW 107107757A TW 201905991 A TW201905991 A TW 201905991A
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Taiwan
Prior art keywords
buffer material
semiconductor device
substrate
semiconductor die
opening
Prior art date
Application number
TW107107757A
Other languages
English (en)
Other versions
TWI677912B (zh
Inventor
黃冠育
吳志偉
郭立中
李隆華
黃松輝
施應慶
李百淵
Original Assignee
台灣積體電路製造股份有限公司
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Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201905991A publication Critical patent/TW201905991A/zh
Application granted granted Critical
Publication of TWI677912B publication Critical patent/TWI677912B/zh

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Abstract

為了防止在半導體晶粒已結合至其他基底之後在半導體晶粒的隅角處出現裂縫，鄰近半導體晶粒的隅角形成開口，且使用緩衝材料來填充及過度填充開口，所述緩衝材料具有介於半導體晶粒的物理性質與鄰近緩衝材料放置的底部填充膠材料的物理性質之間的物理性質。

Description

半導體裝置及其製造方法
半導體裝置用於各種電子應用，例如（舉例而言）個人電腦、手機、數位照相機、以及其他電子設備。通常藉由以下方式來製作半導體裝置：在半導體基底之上依序沉積絕緣材料層或介電材料層、導電材料層、以及半導體材料層，且利用微影製程及蝕刻製程對各種材料層進行圖案化以在半導體基底上形成電路組件及電路元件。
半導體行業藉由不斷減小裝置尺寸以及減小各裝置之間的空間來不斷提高各種電子組件（例如，半導體晶粒、晶片、基底等）的積體密度，此使得能夠在給定體積內整合有更多組件。然而，隨著尺寸的減小，出現了如何對組件進行結合及操作的額外問題，且應解決該些額外的問題。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及配置形式的具體實例以簡化本揭露內容。當然，該些僅為實例而並非旨在進行限制。舉例而言，在以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中在第一特徵與第二特徵之間可形成額外的特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露可能在各種實例中重複使用參考編號及/或字母。此種重複使用是為了簡潔及清晰起見，但自身並不表示所論述的各種實施例及/或構型之間的關係。
此外，為易於說明，本文中可能使用例如「位於…之下（beneath）」、「位於…下方（below）」、「下部的（lower）」、「位於…上方（above）」、「上部的（upper）」等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可被另外定向（旋轉90度或處於其他定向）且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
下文參照呈基底上晶圓上晶片（chip on wafer on substrate，CoWoS）構型的半導體裝置來闡述各實施例。然而，此旨在為說明性的而並非旨在進行限制。更確切而言，本文所實施的概念可用於各種各樣的構型中。
現在參照圖1，其示出晶圓100，在晶圓100內及在晶圓100之上形成有第一半導體晶粒101及第二半導體晶粒103。在實施例中，第一半導體晶粒101及第二半導體晶粒103形成於被切割區（在圖1中由被標記為105的虛線表示）分隔開的晶圓100內，晶圓100將沿所述切割區被分隔而形成第一半導體晶粒101與第二半導體晶粒103此兩個各別半導體晶粒。在實施例中，晶圓100（以及因此，第一半導體晶粒101及第二半導體晶粒103）可包括第一基底、第一主動裝置、金屬層（在圖1中未單獨示出）、接觸接墊107、及第一外部連接109。在實施例中，第一基底可包含經摻雜或未經摻雜的塊狀矽、或者絕緣體上矽（silicon-on-insulator，SOI）基底的主動層。一般而言，絕緣體上矽基底包括例如矽、鍺、矽鍺、絕緣體上矽、絕緣體上矽鍺（silicon germanium on insulator，SGOI）、或其組合等半導體材料層。可使用的其他基底包括多層式基底、梯度基底、或混合定向基底。
第一主動裝置包括可用於產生第一半導體晶粒101及第二半導體晶粒103的設計的所期望結構及功能部分的各種各樣的主動裝置及被動裝置，例如電晶體、電容器、電阻器、電感器等。第一主動裝置可利用任何合適的方法形成於第一基底內或第一基底上。
金屬層形成於第一基底及第一主動裝置之上，且被設計成對各種第一主動裝置進行連接以形成第一半導體晶粒101及第二半導體晶粒103兩者的功能電路系統。在實施例中，金屬層是由介電材料與導電材料的交替層形成，且可藉由任何合適的製程（例如沉積、鑲嵌（damascene）、雙鑲嵌等）形成。在實施例中，可存在藉由至少一個層間介電層（interlayer dielectric layer，ILD）而與第一基底分隔開的四個金屬層，但金屬層的精確數目取決於第一半導體晶粒101及第二半導體晶粒103的設計。
形成接觸接墊107是為了對金屬層及第一主動裝置提供外部接觸。在實施例中，接觸接墊107是由導電材料（例如鋁）形成，但作為另一選擇亦可利用其他合適的材料，例如銅、鎢等。可利用例如化學氣相沉積（Chemical Vapor Deposition，CVD）或物理氣相沉積（Physical Vapor Deposition，PVD）等製程來形成接觸接墊107，但作為另一選擇，亦可利用其他合適的材料及方法。一旦已沉積接觸接墊107的材料，便可利用例如微影遮蔽及蝕刻製程將所述材料成形為接觸接墊107。
第一外部連接109可為接觸凸塊，例如受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、球柵陣列凸塊、或微凸塊等接觸凸塊，且可包含例如錫等材料或者例如銀或銅等其他合適的材料。在其中第一外部連接109為錫焊料凸塊的實施例中，可藉由以下方式來形成第一外部連接109：首先藉由例如蒸鍍（evaporation）、電鍍（electroplating）、印刷、焊料轉移（solder transfer）、植球（ball placement）等任何合適的方法將錫層形成為約100微米的厚度。一旦已在所述結構上形成錫層，便執行迴焊來將材料成形為所期望的凸塊形狀。
然而，儘管焊料凸塊已被闡述作為第一外部連接109的一個實施例，然而此說明旨在為說明性的而並非旨在進行限制。更確切而言，亦可利用任何合適的連接結構，例如導電柱（例如，銅柱）。所有此類結構完全旨在包含於實施例的範圍內。
藉由不將功能結構（例如第一主動裝置）放置至旨在用於切割區105的區域中來形成切割區105。一旦第一半導體晶粒101與第二半導體晶粒103已被彼此分隔開，便可將用於進行平面化的其他結構（例如測試接墊或虛擬金屬）放置至切割區105中，但對於第一半導體晶粒101或第二半導體晶粒103起作用而言並非必需的。切割區105可被形成為具有介於約10微米與約200微米之間（例如約80微米）的第一寬度W1 。
一旦第一外部連接109已形成或以其他方式被放置於接觸接墊107上，便可執行第一單體化製程（在圖1中由被標記為111的虛線框表示），以在切割區105之上在晶圓100內以及至少局部地在第一半導體晶粒101及第二半導體晶粒103兩者內形成第一開口113。在實施例中，第一單體化製程111可使用鋸刀片（saw blade）來執行以部分地而非完全地切穿晶圓100。然而，亦可利用執行第一單體化製程111的任何合適的方法。
另外，鋸刀片可被選擇或製作成使得鋸刀片具有成角度的刀刃，所述成角度的刀刃於用於鋸切晶圓100時將沿第一半導體晶粒101及第二半導體晶粒103兩者形成帶斜面的邊緣115，但亦可利用形成帶斜面的邊緣115的任何其他合適的方法。在實施例中，帶斜面的邊緣115自第一半導體晶粒101的頂表面朝切割區105延伸。在實施例中，帶斜面的邊緣115可被形成為相對於第一半導體晶粒101的頂表面具有介於約20°與約45°之間的第一角度θ1 。然而，亦可利用任何合適的角度。
另外，藉由在第一半導體晶粒101內形成帶斜面的邊緣115，會在第一半導體晶粒101內形成第二開口（在圖1中由被標記為117的虛線框表示），在所述第二開口中第一單體化製程111自第一半導體晶粒101移除材料。在實施例中，第二開口117（位於第一開口113內）可具有介於約20微米與約200微米之間（例如約100微米）的第二寬度W2 。另外，第二開口117亦可具有介於約20微米與約200微米之間（例如約100微米）的第一高度H1 。然而，亦可利用任何合適的尺寸。
圖2A示出將緩衝材料201放置於第一開口113內以及至少局部地放置於第一半導體晶粒101及第二半導體晶粒103之上。可以液體形式或至少局部地可流動形式使用例如分配工具將緩衝材料201分配至第一開口113內以及第一半導體晶粒101的一些部分及第二半導體晶粒103的一些部分之上。
在實施例中，緩衝材料201是將在第一半導體晶粒101的材料（例如，第一半導體晶粒101的主要材料，例如半導體基底的矽材料）與底部填充膠材料501的材料（在圖2中未示出但下文關於圖5示出並闡述）之間充當緩衝體的材料。因此，為了充當緩衝體，在一些實施例中，緩衝材料201具有量值介於第一半導體晶粒101的材料性質的量值與底部填充膠材料501的材料性質的量值之間的材料性質。
舉例而言，在一些實施例中，緩衝材料201可為以下材料，所述材料具有介於第一基底（位於第一半導體晶粒101內）的第二楊氏模數（Young’s modulus）與底部填充膠材料501的第三楊氏模數之間的第一楊氏模數。在額外的實施例中，緩衝材料201亦可具有第一熱膨脹係數（coefficient of thermal expansion，CTE），所述第一熱膨脹係數的值介於第一基底（位於第一半導體晶粒101內）的第二熱膨脹係數與底部填充膠材料501的第三熱膨脹係數之間。
在具體實施例中，第一基底（位於第一半導體晶粒101內）是楊氏模數為160十億帕（GPa）且熱膨脹係數為2.6 mm*m-1 *K-1 的矽。另外，底部填充膠材料501是楊氏模數為11十億帕且熱膨脹係數為23 mm*m-1 *K-1 的聚合物，例如環氧樹脂。在此種實施例中，緩衝材料201可為楊氏模式為15十億帕（介於矽的楊氏模數與底部填充膠材料501的楊氏模數之間）且熱膨脹係數為9 mm*m-1 *K-1 （介於矽的熱膨脹係數與底部填充膠材料501的熱膨脹係數之間）的材料，例如環氧樹脂、壓克力、或聚胺基甲酸酯（Polyurethane，PU）。然而，亦可利用任何合適的材料。
圖2B示出第一半導體晶粒101、第二半導體晶粒103、環繞第一半導體晶粒101及第二半導體晶粒103的切割區105的至少一部分、以及緩衝材料201的俯視圖，其中圖2A是圖2B沿線A-A’的剖視圖。在實施例中，緩衝材料201可被分配成環繞第一半導體晶粒101的外邊緣及第二半導體晶粒103的外邊緣，而不延伸跨越第一半導體晶粒101及第二半導體晶粒103。舉例而言，緩衝材料201可呈液體形式或可流動形式，且可使用例如分配工具圍繞第一半導體晶粒101的外邊緣及第二半導體晶粒103的外邊緣放置，但亦可利用分配緩衝材料201或以其他方式放置緩衝材料201的任何合適的方法。
在其中緩衝材料201圍繞第一半導體晶粒101的外邊緣及第二半導體晶粒103的外邊緣分配的實施例中，緩衝材料201可被形成為自切割區105的邊緣朝第一半導體晶粒101的中心具有介於約100微米與約200微米之間（例如約150微米）的第三寬度W3 。另外，緩衝材料201可在圍繞第一半導體晶粒101的外邊緣的整個路徑上維持第三寬度W3 。如此一來，位於第一半導體晶粒101之上的緩衝材料201將沿線A-A’具有為第三寬度W3 的兩倍或介於約20微米與約200微米之間（例如約50微米）的總寬度。然而，亦可利用任何合適的寬度。
另外，緩衝材料201可被分配成自第一半導體晶粒101、在切割區105之上以及在第二半導體晶粒103之上連續延伸。在此實施例中，緩衝材料201可具有由第三寬度W3 的兩倍（包括緩衝材料201在第一半導體晶粒101及第二半導體晶粒103兩者之上的寬度）以及切割區105的第一寬度W1 構成的第四寬度W4 。如此一來，緩衝材料201可具有介於約40微米與約400微米之間（例如約130微米）的第四寬度W4 。然而，亦可利用任何合適的尺寸。
現在轉向圖2A，緩衝材料201亦可在第一半導體晶粒101的頂表面之上被分配至第二高度H2 。在實施例中，第二高度H2 小於第一半導體晶粒101與第二基底401（在圖2A中未示出但下文關於圖4示出並加以論述）之間的最終相隔高度（stand-off height）Hso 。舉例而言，在實施例中，第二高度H2 可介於相隔高度Hso 的三分之一至二分之一之間。因此，若所期望的相隔高度Hso 介於約30微米與約150微米之間（例如約100微米），則第二高度H2 可介於約10微米與約70微米之間（例如約40微米）。然而，亦可利用任何合適的高度。
一旦緩衝材料201已被分配，則可對緩衝材料201進行固化以使緩衝材料201凝固。在其中緩衝材料201是環氧樹脂的實施例中，緩衝材料201可在介於約110℃與約150℃之間（例如約180℃）的溫度下固化達介於約10秒與約2小時之間（例如約30分鐘）的時間段。然而，亦可利用任何合適的固化溫度（包括室溫）及任何合適的固化時間。
圖3示出第二單體化製程（在圖3中由被標記為301的虛線框表示）。在實施例中，第二單體化製程301可使用鋸刀片來執行以在第一半導體晶粒101與第二半導體晶粒103之間切穿晶圓100。藉由切穿切割區105內的晶圓100，第一半導體晶粒101將與第二半導體晶粒103分隔開以及與自晶圓100形成以及在晶圓100上形成的其他剩餘的晶粒分隔開。
在第二單體化製程301將第一半導體晶粒101與第二半導體晶粒103分隔開的同時，第二單體化製程301亦會切穿並移除緩衝材料201的材料。如此一來，由於對緩衝材料201及第一半導體晶粒101兩者進行鋸切，因此在第二單體化製程301已發生之後，緩衝材料201將具有與第一半導體晶粒101的側壁對齊以及平行的外側壁。
另外，儘管圖3示出緩衝材料201與第一半導體晶粒101在垂直方向上對齊，然而此旨在為說明性的而並非旨在進行限制。更確切而言，亦可利用任何合適的定向。舉例而言，若利用具有成角度的刀刃的鋸刀片，則緩衝材料201與第一半導體晶粒101的至少一部分可彼此對齊但相對於垂直方向具有一定角度，如圖3所示。亦可利用任何合適的定向。
此外，如此項技術中具有通常知識者將會認識到，利用鋸刀片來將第一半導體晶粒101單體化僅為一個說明性實施例而並非旨在進行限制。作為另一選擇，亦可利用將第一半導體晶粒101單體化的替代方法，例如利用一或多種蝕刻來將第一半導體晶粒101與第二半導體晶粒103分隔開或者甚至利用雷射燒蝕（laser ablation）。作為另一選擇，可利用該些方法及任何其他合適的方法將晶圓100單體化。
圖4示出一旦第一半導體晶粒101已被單體化，便可將第一半導體晶粒101結合至第二基底401。在實施例中，第二基底401可包括中介層基底（其中多個裝置定位於中介層基底內），所述中介層基底具有一或多個穿孔405、一或多個第二接觸接墊403、及一或多個第三接觸接墊407。
第二基底401可具有設置於第二基底401的一側或兩側上的一或多個重佈線層（圖中未單獨示出）。所述一或多個穿孔405可包含將第二基底401的第一側上的第一重佈線層（redistribution layer，RDL）連接至第二基底401的第二側上的第二重佈線層的導電材料。重佈線層可包括具有導電線的介電層，所述導電線可電性連接至所述一或多個穿孔405。舉例而言，第一重佈線層可將第二接觸接墊403（位於第二基底401的第一側上）中的一或多者連接至第三接觸接墊407（位於第二基底401的第二側上）中的一或多者。第三接觸接墊407可用於將第二基底401（以及因此第一半導體晶粒101）連接至第三基底601（在圖4中未示出但下文關於圖6示出並進一步闡述）。
在實施例中，第二接觸接墊403及第三接觸接墊407可相似於以上關於圖1闡述的接觸接墊107。舉例而言，第二接觸接墊403及第三接觸接墊407可為導電材料（例如鋁）藉由例如化學氣相沉積等製程、然後進行圖案化而形成。然而，在其他實施例中，第二接觸接墊403及第三接觸接墊407可不同於接觸接墊107且彼此不同。
在另一實施例中，第二基底401可為上面形成有額外半導體裝置的另一半導體晶圓。舉例而言，第二基底401可包括第三半導體裝置（圖中未單獨示出），所述第三半導體裝置被設計成與第一半導體晶粒101協同工作，但尚未自第二基底401的半導體晶圓內的其他半導體裝置單體化。
為了將第一半導體晶粒101結合至第二基底401，將第一外部連接109與第二基底401的第二接觸接墊403對齊並放置成與第二基底401的第二接觸接墊403實體地連接。一旦就位，便升高第一外部連接109的溫度以起始第一外部連接109的材料的回焊。一旦回焊製程已發生且然後第一外部連接109的材料已凝固，便將第一半導體晶粒101電性地及實體地連接至第二基底401。
然而，儘管回焊製程被闡述為一個結合製程，然而此旨在為說明性的而並非旨在進行限制。更確切而言，亦可利用任何合適的結合製程，例如在利用銅柱的實施例中為銅-銅結合。所有此類結合製程完全旨在包含於實施例的範圍內。
一旦第一半導體晶粒101與第二基底401已結合在一起，便將第一半導體晶粒101與第二基底401分隔開相隔高度Hso 。在實施例中，相隔高度Hso 可介於約30微米與約150微米之間（例如約100微米）。然而，亦可利用任何合適的相隔高度。
圖5示出在第一半導體晶粒101與第二基底401之間施加底部填充膠材料501以幫助密封及保護第一外部連接109。在實施例中，底部填充膠材料501可為單一連續的材料（例如環氧樹脂、樹脂等），且可藉由以液體形式對底部填充膠材料501進行注射、進而使得底部填充膠材料501在第一半導體晶粒101與第二基底401之間流動而進行分配。一旦已放置底部填充膠材料501，便可對底部填充膠材料501進行固化以使底部填充膠材料501硬化。
除密封第一外部連接109以外，底部填充膠材料501亦可被分配成在第一半導體晶粒101的每一側上形成圓角（fillet），藉此幫助密封及保護第一半導體晶粒101的各個側。在實施例中，底部填充膠材料501可被分配成直至圓角具有小於約2毫米（例如介於約1.5毫米至約2毫米之間）的第五寬度W5 （以離開第一半導體晶粒101的方式延伸）。另外，圓角可具有可延伸或可不延伸至覆蓋第一半導體晶粒101的整個側壁的第三高度H3 。如此一來，第三高度H3 可介於約700毫米與約1000毫米之間。然而，亦可利用任何合適的尺寸。
圖6示出一旦底部填充膠材料501已被放置於第一半導體晶粒101與第二基底401之間，便可將第二基底401單體化並接著結合至第三基底601。在實施例中，可使用一或多個鋸刀片將第二基底401單體化，以將第二基底401分隔成單獨的片。然而，亦可利用任何合適的單體化方法，包括雷射燒蝕或者一或多種濕式蝕刻。
一旦被單體化，便使用例如第二外部連接件603將第二基底401以及因此將第一半導體晶粒101結合至第三基底601。在實施例中，第二外部連接件603可為例如球柵陣列凸塊、微凸塊、或受控塌陷晶片連接（C4）凸塊等接觸凸塊，且可包含例如錫等材料或者例如銀或銅等其他合適的材料。在其中第二外部連接件603為錫焊料凸塊的實施例中，可藉由以下方式來形成第二外部連接件603：首先藉由例如蒸鍍、電鍍、印刷、焊料轉移、植球等任何合適的方法將錫層形成為約100微米的厚度。一旦已在此結構上形成錫層，便執行迴焊以將此材料成形為所期望的凸塊形狀。
一旦已形成第二外部連接件603，便使用第二外部連接件603將第二基底401結合至第三基底601。在實施例中，第三基底601可為印刷電路板，例如疊層基底，所述印刷電路板被形成為由例如雙馬來醯亞胺三嗪（bismaleimide triazine，BT）、FR-4、味之素構成膜（Ajinomoto Buildup Film，ABF）等聚合物材料形成的多個薄層（或疊層）的堆疊。然而，作為另一選擇，亦可利用任何其他合適的基底（例如矽中介層、矽基底、有機基底、陶瓷基底等），且對第二基底401提供支撐及連接的所有此類重佈線基底完全旨在包含於實施例的範圍內。
可藉由首先將第二基底401與第三基底601對齊、以使得第二外部連接件603位於對應的接觸接墊之間而將第二基底401結合至第三基底601。一旦實體地接觸，便可執行回焊以對第二外部連接件603進行回焊並將第二外部連接件603與第二基底401及第三基底601兩者結合。然而，作為另一選擇，亦可利用任何其他合適的結合。
藉由將緩衝材料201放置於第一半導體晶粒101與底部填充膠材料501之間，緩衝材料201可在第一半導體晶粒101的材料與底部填充膠材料501的材料之間充當緩衝體。如此一來，可減少或消除在底部填充膠材料501中可能產生的由熱膨脹係數的差異引起的負面效應，例如裂縫。在利用基底上晶圓上晶片構型的實施例中，如此減少使得良率及可靠性總體上得到提高且可靠性窗口（reliability window）擴大。
圖7示出另一實施例，其中第一開口113並非具有傾斜的側壁而是具有與第一半導體晶粒101的頂表面及第二半導體晶粒103的頂表面垂直的側壁、並且具有平的且與第一半導體晶粒101的頂表面平行的底表面。在此實施例中，並非對第一單體化製程111使用成角度的鋸刀片（如以上關於圖1所述），而是使用具有直邊的鋸刀片來形成第一開口113。在對第一開口113使用直的側壁的其他實施例中，第一開口113可使用雷射燒蝕或甚至一或多個系列的蝕刻（例如乾式蝕刻）來形成，以移除晶圓100的材料並將第一開口113形成為具有直的側壁。將第一開口113形成為具有直的側壁的任何合適的方法完全旨在包含於實施例的範圍內。
在此實施例中，第一開口113可被形成為具有介於約10微米與約90微米之間（例如約20微米）的第四高度H4 。另外，第一開口113亦可自切割區105延伸至第一半導體晶粒101中達介於約10微米與約90微米之間（例如約20微米）的第六寬度W6 。然而，亦可利用任何合適的尺寸。
圖8示出將緩衝材料201放置於第一開口113內以及至少局部地上覆於第一半導體晶粒101及第二半導體晶粒103之上。在實施例中，緩衝材料201可如以上關於圖2A所述進行放置。舉例而言，可以液體形式或可流動形式圍繞第一半導體晶粒101的外邊緣以及第二半導體晶粒103的外邊緣分配緩衝材料201（如以上關於圖2B所述）。然而，亦可以任何合適的方式來分配緩衝材料201。
在此實施例中，由於第一開口113被形成為具有直的側壁以及直的底表面，因此緩衝材料201亦將具有直的且與第一半導體晶粒101的頂表面平行的底表面。另外，緩衝材料201亦將具有以直角與底表面相交的側壁，藉此將緩衝材料201形成為階梯形狀。然而，亦可利用任何合適的形狀。
圖9示出在放置緩衝材料201之後執行第二單體化製程301。在實施例中，第二單體化製程301可如以上關於圖3所述來執行。舉例而言，可利用鋸刀片製程、雷射燒蝕製程、一或多種濕式蝕刻等來分隔晶圓100並將第一半導體晶粒101與第二半導體晶粒103分隔開。然而，亦可利用任何合適的製程來將晶圓100單體化。
另外，由於緩衝材料201具有與第一半導體晶粒101的頂表面平行的底表面，因此藉由第二單體化製程301形成的緩衝材料201的側壁（與第二半導體晶粒103面對的側壁）將不僅與第一半導體晶粒101的側壁對齊，且在一些實施例中亦將與緩衝材料201的底表面垂直。對緩衝材料201的底表面的形狀的如此微調會容許更大的製程可變性且對製程整合提供額外的選項。
圖10示出將第一半導體晶粒101結合至第二基底401、將底部填充膠材料501放置於第一半導體晶粒101與第二基底401之間、以及將第二基底401結合至第三基底601。在實施例中，該些製程步驟可如以上關於圖4至圖6所述來執行。然而，亦可執行任何合適的製程步驟。
圖11示出其中緩衝材料201並非在上部隅角處為正方形而是具有彎曲形狀的另一實施例。在此實施例中，緩衝材料201的隅角可如以上關於圖3所述在第二單體化製程301期間變彎曲。然而，在此實施例中，並非使用具有直邊的鋸刀片，而是可利用具有成角度的邊的鋸刀片。如此一來，鋸刀片將以鋸刀片的形狀來移除緩衝材料201的材料，藉此將緩衝材料201的上部隅角修圓。
在實施例中，緩衝材料201的隅角可偏離直角彎曲，使得緩衝材料201的隅角具有第一曲率。舉例而言，緩衝材料201的隅角可具有介於約90度與約10度之間（例如約30度）的第一曲率。然而，亦可利用任何合適的形狀。
圖12示出在緩衝材料201中形成修圓的隅角的另一實施例，在此實施例中並非利用第二單體化製程301來形成修圓的隅角，而是利用單獨的修圓製程（在圖12中由被標記為1201的虛線框表示）來形成修圓的隅角。在實施例中，修圓製程1201可為在第二單體化製程301之後執行的第三單體化製程，所述第三單體化製程使用成形（shaped）鋸刀片來移除緩衝材料201的材料並形成修圓的隅角。在另一實施例中，修圓的隅角可利用雷射刻槽製程來形成，在所述雷射刻槽製程中將雷射朝緩衝材料201的期望被移除的部分引導以形成緩衝材料201的修圓的隅角。亦可利用將隅角修圓的任何合適的方法來對緩衝材料201進行整形。
圖13A至圖13B示出其中可將緩衝材料201的形狀微調成不再具有平的頂表面（如以上關於圖2A所示）而是具有更修圓的頂表面的再一實施例。在此實施例中且如圖13A所示，可對緩衝材料201的材料進行選擇以在緩衝材料201已被分配之後微調緩衝材料201的形狀。舉例而言，在一個實施例中，緩衝材料201的材料可被選擇成具有更高的疏水性，而在其他實施例中，緩衝材料201的材料可被選擇成具有更低的疏水性，其中疏水性會修改緩衝材料201的形狀。藉由選擇適當的材料來微調疏水性，緩衝材料201可被微調成具有更平的或更修圓的頂表面。
在具體實施例中，緩衝材料201被選擇成對氮化矽（SiN）具有疏水性或親水性的聚合物，例如壓克力。若給定此種所選擇材料及其性質，則在分配緩衝材料201時，緩衝材料201會失去平面性而成為彎曲的形狀。如此一來，緩衝材料201可在緩衝材料201的邊緣處具有介於約10微米與約70微米之間（例如約40微米）的第五高度H5 ，且亦可在切割區105的邊緣之上的點處具有介於約10微米與約100微米之間（例如約50微米）的第六高度H6 。另外，緩衝材料201可在緩衝材料201的中點處具有介於約10微米與約150微米之間（例如約60微米）的第七高度H7 。然而，亦可利用任何合適的尺寸。
圖13B示出在緩衝材料201的材料已被選擇成將緩衝材料201的形狀微調成具有更修圓的頂表面之後，可將晶圓100單體化，可將第一半導體晶粒101結合至第二基底401，可將底部填充膠材料501放置於第一半導體晶粒101與第二基底401之間，且可將第二基底401結合至第三基底601。在實施例中，該些製程步驟可如以上關於圖4至圖6所述來執行。然而，亦可執行任何合適的製程步驟。
圖14示出其中緩衝材料201並非沿第一半導體晶粒101的整個外邊緣及第二半導體晶粒103的整個外邊緣分配而是僅在第一半導體晶粒101的隅角處及第二半導體晶粒103的隅角處分配的再一實施例。在此實施例中，緩衝材料201可被分配成使得第一半導體晶粒101之上的緩衝材料201具有介於約100微米與約500微米之間（例如約200微米）的第七寬度W7 。另外，緩衝材料201可被分配成使得緩衝材料201具有介於約100微米與約500微米之間（例如約200微米）的第一長度L1 。然而，亦可利用任何合適的尺寸。
藉由沿第一半導體晶粒101的隅角及第二半導體晶粒103的隅角利用緩衝材料201，緩衝材料201可提供所期望的緩衝以有助於防止沿隅角出現裂縫，且亦會利用更少量的緩衝材料201。材料如此減少使得成本總體上降低且有助於提高產量。
圖15示出本文所述的製程步驟中的至少一些製程步驟的簡化流程圖。在實施例中，第一步驟1501包括執行第一單體化製程，且第二步驟1503包括在藉由第一單體化製程形成的開口內分配緩衝材料。一旦緩衝材料已被分配及固化，便在第三步驟1505中執行第二單體化製程，且在第四步驟1507中將單體化的半導體晶粒結合至基底。一旦結合，便在第五步驟1509中在單體化的半導體晶粒與基底之間分配底部填充膠材料，且在第六步驟1511中將單體化的組合結合至另一基底。
在實施例中，一種製造裝置的方法包括：沿半導體晶粒的外邊緣形成開口；使用緩衝材料來過度填充所述開口的至少一部分；以及鄰近所述緩衝材料放置底部填充膠材料。在實施例中，所述方法更包括：在所述過度填充所述開口之後且在所述放置所述底部填充膠材料之前，將所述半導體晶粒自半導體晶圓單體化。在實施例中，所述將所述半導體晶粒單體化是藉由使用鋸切穿所述緩衝材料及所述半導體晶圓來執行。在實施例中，所述方法更包括：在所述鄰近所述緩衝材料放置所述底部填充膠材料之前，將所述半導體晶粒結合至第一基底。在實施例中，在所述放置所述底部填充膠材料期間，所述底部填充膠材料在所述第一基底與所述緩衝材料之間流動。在實施例中，所述方法更包括：將所述第一基底結合至第二基底。在實施例中，所述使用所述緩衝材料來過度填充所述開口的至少所述一部分使得沿所述半導體晶粒的整個周邊留下所述緩衝材料。
在另一實施例中，一種製造裝置的方法包括：將第一晶圓局部地單體化，以在所述第一晶圓內形成第一開口，所述第一晶圓包括由第一材料形成的半導體基底，所述第一材料具有為第一值的第一性質，其中所述第一開口至少局部地延伸至第一半導體裝置及第二半導體裝置二者內；使用緩衝材料來填充所述第一開口的至少一部分，所述緩衝材料具有為第二值的所述第一性質，所述第二值不同於所述第一值；在所述填充所述第一開口之後將所述第一晶圓完全單體化，其中在所述將所述第一晶圓完全單體化之後，所述緩衝材料在所述第一開口內留存於所述第一半導體裝置之上；將所述第一半導體裝置結合至基底；以及在所述第一半導體裝置與所述基底之間分配底部填充膠材料，其中所述底部填充膠材料具有為第三值的所述第一性質，所述第二值介於所述第一值與所述第三值之間。在實施例中，所述將所述第一晶圓局部地單體化使得將所述第一開口形成為具有帶斜面的邊緣。在實施例中，所述將所述第一晶圓局部地單體化使得將所述第一開口形成為具有垂直的邊。在實施例中，所述第一性質是楊氏模數。在實施例中，所述第一性質是熱膨脹係數。在實施例中，所述填充所述第一開口的至少所述一部分將所述緩衝材料放置至所述第一半導體裝置的隅角區中，其中所述緩衝材料不延伸超出所述第一半導體裝置的所述隅角區。在實施例中，所述方法更包括：在所述填充所述第一開口的至少所述一部分之後，將所述緩衝材料修圓。
在再一實施例中，一種裝置包括：第一半導體裝置，所述第一半導體裝置包括第一外部連接；緩衝材料，沿所述第一半導體裝置的外邊緣定位；以及底部填充膠材料，自所述第一半導體裝置的側壁延伸，圍繞所述緩衝材料，且延伸至所述緩衝材料與所述第一外部連接之間的點。在實施例中，所述底部填充膠材料是連續的第一材料。在實施例中，所述緩衝材料至少局部地延伸至所述第一半導體裝置內。在實施例中，所述緩衝材料在所述第一半導體裝置內具有帶斜面的邊緣。在實施例中，所述第一半導體裝置內的緩衝材料具有與所述第一半導體裝置的頂表面平行的第一邊及與所述第一邊具有角度的第二邊。在實施例中，所述第一半導體裝置內的緩衝材料具有連接至所述第一半導體裝置的側壁的側壁。
在再一實施例中，一種製造裝置的方法包括：提供具有第一半導體裝置及第二半導體裝置的半導體晶圓；在所述第一半導體裝置與所述第二半導體裝置之間的切割區之上形成第一開口；將第一材料分配至所述第一開口內；以及在單體化製程中移除所述第一材料的一部分，其中所述單體化製程將所述第一半導體裝置與所述第二半導體裝置分隔開，所述單體化製程使得所述第一材料的第一部分留在所述第一半導體裝置之上，所述第一部分具有小於200微米的寬度。在實施例中，所述移除所述第一材料的所述一部分使得留下垂直的隅角。在實施例中，所述移除所述第一材料的所述一部分使得留下修圓的隅角。在實施例中，所述形成所述第一開口形成帶斜面的邊緣。
在再一實施例中，一種裝置包括：第一半導體裝置，包括頂表面及側壁，其中所述頂表面與所述側壁是由相對於所述頂表面及所述側壁未對齊的第一表面連接；緩衝材料，實體地接觸所述頂表面且覆蓋所述第一表面，其中所述緩衝材料的第二表面與所述側壁對齊；以及底部填充膠材料，實體地接觸所述頂表面及所述緩衝材料。在實施例中，所述緩衝材料具有階梯形狀。在實施例中，所述第一表面為帶斜面的表面。
在再一實施例中，一種裝置包括：半導體裝置，具有定位於半導體裝置的隅角處的開口；緩衝材料，至少局部地定位於所述開口內，其中所述緩衝材料不延伸跨越所述半導體裝置；基底，結合至所述半導體裝置；以及底部填充膠材料，定位於所述半導體裝置與所述基底之間，其中所述緩衝材料具有第一性質，所述第一性質的值介於所述半導體裝置的值與所述底部填充膠材料的值之間。在實施例中，所述緩衝材料具有與所述半導體裝置的第二側壁對齊的第一側壁。在實施例中，所述緩衝材料具有背對所述半導體裝置的修圓的表面。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本揭露的各態樣。熟習此項技術者應理解，其可容易地使用本揭露作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，此類等效構造並不背離本揭露的精神及範圍，且他們可在不背離本揭露的精神及範圍的條件下對其作出各種改變、代替、及變更。
100‧‧‧晶圓
101‧‧‧第一半導體晶粒
103‧‧‧第二半導體晶粒
105‧‧‧切割區
107‧‧‧接觸接墊
109‧‧‧第一外部連接
111‧‧‧第一單體化製程
113‧‧‧第一開口
115‧‧‧帶斜面的邊緣
117‧‧‧第二開口
201‧‧‧緩衝材料
301‧‧‧第二單體化製程
401‧‧‧第二基底
403‧‧‧第二接觸接墊
405‧‧‧穿孔
407‧‧‧第三接觸接墊
501‧‧‧底部填充膠材料
601‧‧‧第三基底
603‧‧‧外部連接件
1201‧‧‧修圓製程
1501‧‧‧第一步驟
1503‧‧‧第二步驟
1505‧‧‧第三步驟
1507‧‧‧第四步驟
1509‧‧‧第五步驟
1511‧‧‧第六步驟
A-A’‧‧‧線
H1 ‧‧‧第一高度
H2‧‧‧第二高度
H3‧‧‧第三高度
H4‧‧‧第四高度
H5‧‧‧第五高度
H6‧‧‧第六高度
H7‧‧‧第七高度
Hso‧‧‧相隔高度
L1‧‧‧第一長度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
W3‧‧‧第三寬度
W4‧‧‧第四寬度
W5‧‧‧第五寬度
W6‧‧‧第六寬度
W7‧‧‧第七寬度
θ1‧‧‧第一角度
結合附圖閱讀以下詳細說明，會最佳地理解本揭露的各態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1示出根據一些實施例的具有第一半導體裝置及第二半導體裝置的晶圓。 圖2A至圖2B示出根據一些實施例的緩衝材料的放置。 圖3示出根據一些實施例的晶圓的單體化。 圖4示出根據一些實施例將第一半導體裝置結合至第二基底。 圖5示出根據一些實施例的底部填充膠的放置。 圖6示出根據一些實施例將第二基底結合至第三基底。 圖7示出根據一些實施例的具有平的底表面的開口。 圖8示出根據一些實施例使用平的底表面來放置緩衝材料。 圖9示出根據一些實施例的晶圓的單體化。 圖10示出根據一些實施例將第一半導體晶粒結合至第二基底及第三基底。 圖11示出根據一些實施例同時進行單體化及隅角修圓的製程。 圖12示出根據一些實施例在單體化製程之後的單獨的隅角修圓製程。 圖13A至圖13B示出根據一些實施例對緩衝材料的形狀進行的微調。 圖14示出根據一些實施例將緩衝材料放置於半導體晶粒的隅角區中。 圖15示出根據一些實施例的保護半導體裝置的製程的流程圖。

Claims (20)

  1. 一種製造裝置的方法，所述方法包括： 沿半導體晶粒的外邊緣形成開口； 使用緩衝材料來過度填充所述開口的至少一部分；以及 鄰近所述緩衝材料放置底部填充膠材料。
  2. 如申請專利範圍第1項所述的方法，更包括：在所述過度填充所述開口之後且在所述放置所述底部填充膠材料之前，將所述半導體晶粒自半導體晶圓單體化。
  3. 如申請專利範圍第2項所述的方法，其中所述將所述半導體晶粒單體化是藉由使用鋸切穿所述緩衝材料及所述半導體晶圓來執行。
  4. 如申請專利範圍第1項所述的方法，更包括：在所述鄰近所述緩衝材料放置所述底部填充膠材料之前，將所述半導體晶粒結合至第一基底。
  5. 如申請專利範圍第4項所述的方法，其中在所述放置所述底部填充膠材料期間，所述底部填充膠材料在所述第一基底與所述緩衝材料之間流動。
  6. 如申請專利範圍第5項所述的方法，更包括：將所述第一基底結合至第二基底。
  7. 如申請專利範圍第1項所述的方法，其中所述使用所述緩衝材料來過度填充所述開口的至少所述一部分使得沿所述半導體晶粒的整個周邊留下所述緩衝材料。
  8. 一種製造裝置的方法，所述方法包括： 將第一晶圓局部地單體化，以在所述第一晶圓內形成第一開口，所述第一晶圓包括由第一材料形成的半導體基底，所述第一材料具有為第一值的第一性質，其中所述第一開口至少局部地延伸至第一半導體裝置及第二半導體裝置二者內； 使用緩衝材料來填充所述第一開口的至少一部分，所述緩衝材料具有為第二值的所述第一性質，所述第二值不同於所述第一值； 在所述填充所述第一開口之後將所述第一晶圓完全單體化，其中在所述將所述第一晶圓完全單體化之後，所述緩衝材料在所述第一開口內留存於所述第一半導體裝置之上； 將所述第一半導體裝置結合至基底；以及 在所述第一半導體裝置與所述基底之間分配底部填充膠材料，其中所述底部填充膠材料具有為第三值的所述第一性質，所述第二值介於所述第一值與所述第三值之間。
  9. 如申請專利範圍第8項所述的方法，其中所述將所述第一晶圓局部地單體化使得將所述第一開口形成為具有帶斜面的邊緣。
  10. 如申請專利範圍第8項所述的方法，其中所述將所述第一晶圓局部地單體化使得將所述第一開口形成為具有垂直的邊。
  11. 如申請專利範圍第8項所述的方法，其中所述第一性質是楊氏模數。
  12. 如申請專利範圍第8項所述的方法，其中所述第一性質是熱膨脹係數。
  13. 如申請專利範圍第8項所述的方法，其中所述填充所述第一開口的至少所述一部分將所述緩衝材料放置至所述第一半導體裝置的隅角區中，其中所述緩衝材料不延伸超出所述第一半導體裝置的所述隅角區。
  14. 如申請專利範圍第8項所述的方法，更包括：在所述填充所述第一開口的至少所述一部分之後，將所述緩衝材料修圓。
  15. 一種裝置，包括： 第一半導體裝置，所述第一半導體裝置包括第一外部連接； 緩衝材料，沿所述第一半導體裝置的外邊緣定位；以及 底部填充膠材料，自所述第一半導體裝置的側壁延伸，圍繞所述緩衝材料，且延伸至所述緩衝材料與所述第一外部連接之間的點。
  16. 如申請專利範圍第15項所述的裝置，其中所述底部填充膠材料是連續的第一材料。
  17. 如申請專利範圍第15項所述的裝置，其中所述緩衝材料至少局部地延伸至所述第一半導體裝置內。
  18. 如申請專利範圍第17項所述的裝置，其中所述緩衝材料在所述第一半導體裝置內具有帶斜面的邊緣。
  19. 如申請專利範圍第17項所述的裝置，其中所述第一半導體裝置內的所述緩衝材料具有與所述第一半導體裝置的頂表面平行的第一邊及與所述第一邊具有角度的第二邊。
  20. 如申請專利範圍第17項所述的裝置，其中所述第一半導體裝置內的所述緩衝材料具有連接至所述第一半導體裝置的所述側壁的側壁。
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