CN109216215A - 半导体器件和制造方法 - Google Patents

半导体器件和制造方法 Download PDF

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Publication number
CN109216215A
CN109216215A CN201810263929.1A CN201810263929A CN109216215A CN 109216215 A CN109216215 A CN 109216215A CN 201810263929 A CN201810263929 A CN 201810263929A CN 109216215 A CN109216215 A CN 109216215A
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Prior art keywords
padded coaming
substrate
semiconductor devices
semiconductor element
semiconductor
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CN201810263929.1A
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CN109216215B (zh
Inventor
黄冠育
吴志伟
郭立中
李隆华
黄松辉
施应庆
李百渊
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

为了防止在半导体管芯接合至其它衬底之后在半导体管芯的拐角处出现裂缝，邻近半导体管芯的拐角形成开口，并且用缓冲材料填充和过填充开口，其中，缓冲材料的物理特性介于半导体管芯和邻近缓冲材料放置的底部填充材料的物理特性之间。本发明实施例涉及一种半导体器件和制造方法。

Description

半导体器件和制造方法
技术领域
本发明实施例涉及一种半导体器件和制造方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其它电子设备的各种电子应用中。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻和蚀刻工艺图案化各个材料层以在各个材料层上形成电路组件和元件来制造半导体器件。
半导体工业通过不断减小器件尺寸以及减小器件之间的间隔持续地改进各个电子组件(例如，半导体管芯、芯片、衬底等)的集成密度，这允许更多的组件集成至给定的区域。然而，随着尺寸的减小，组件在如何接合和操作方面出现额外的问题，并且这些额外的问题应该被解决。
发明内容
根据本发明的一些实施例，提供了一种制造半导体器件的方法，所述方法包括：沿着半导体管芯的外边缘形成开口；用缓冲材料过填充所述开口的至少部分；以及邻近所述缓冲材料放置底部填充材料。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，所述方法包括：部分地分割第一晶圆以在所述第一晶圆内形成第一开口，所述第一晶圆包括第一材料的半导体衬底，所述第一材料的第一特性具有第一值，其中，所述第一开口至少部分地延伸至第一半导体器件和第二半导体器件内；用缓冲材料填充所述第一开口的至少部分，所述缓冲材料的所述第一特性具有与所述第一值不同的第二值；在填充所述第一开口之后，完全地分割所述第一晶圆，其中，在完全地分割所述第一晶圆之后，所述缓冲材料保留在所述第一半导体器件上方的所述第一开口内；将所述第一半导体器件接合至衬底；以及将底部填充材料分配在所述第一半导体器件和所述衬底之间，其中，所述底部填充材料的所述第一特性具有第三值，所述第二值介于所述第一值和所述第三值之间。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：第一半导体器件，所述第一半导体器件包括第一外部连接件；缓冲材料，沿着所述第一半导体器件的外边缘；以及底部填充材料，从所述第一半导体器件的侧壁、所述缓冲材料周围延伸至所述缓冲材料和所述第一外部连接件之间的点。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的具有第一半导体器件和第二半导体器件的晶圆。
图2A至图2B示出了根据一些实施例的缓冲材料的放置。
图3示出了根据一些实施例的晶圆100的分割。
图4示出了根据一些实施例的第一半导体器件与第二衬底的接合。
图5示出了根据一些实施例的底部填充物的放置。
图6示出了根据一些实施例的第二衬底与第三衬底的接合。
图7示出了根据一些实施例的具有平坦底面的开口。
图8示出了根据一些实施例的具有平坦底面的缓冲材料的放置。
图9示出了根据一些实施例的晶圆的分割。
图10示出了根据一些实施例的第一半导体管芯与第二衬底和第三衬底的接合。
图11示出了根据一些实施例的同时分割和拐角圆化工艺。
图12示出了根据一些实施例的分割工艺之后的单独的拐角圆化工艺。
图13A至图13B示出了根据一些实施例的缓冲材料的形状的调整。
图14示出了根据一些实施例的半导体管芯的拐角区域中的缓冲材料的放置。
图15示出了根据一些实施例的保护半导体器件的工艺的流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
下面将参照衬底上晶圆上芯片(CoWoS)配置中的半导体器件来描述实施例。然而，这旨在说明而不旨在限制。而且，本文体现的思想可以用于各种配置。
现在参照图1，图1示出了具有形成在晶圆100内和上方的第一半导体管芯101和第二半导体管芯103的晶圆100。在实施例中，由划线区域(在图1中由标记为105的虚线表示)分隔开的第一半导体管芯101和第二半导体管芯103形成在晶圆100内，将沿着划线区域分离晶圆100以形成单独的第一半导体管芯101和第二半导体管芯103。在实施例中，晶圆100(并且因此，第一半导体管芯101和第二半导体管芯103)可以包括第一衬底、第一有源器件、金属化层(图1中未单独示出)、接触焊盘107和第一外部连接件109。在实施例中，第一衬底可以包括掺杂或未掺杂的块状硅或绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括诸如硅、锗、硅锗、SOI、绝缘体上硅锗(SGOI)或它们的组合的半导体材料层。可以使用包括多层衬底、梯度衬底或混合取向衬底的其它衬底。
第一有源器件包括各种有源器件和无源器件，诸如晶体管、电容器、电阻器、电感器等，其可以用于生成用于第一半导体管芯101和第二半导体管芯103的设计的期望的结构和功能部分。可以使用任何合适的方法在第一衬底内或者上形成第一有源器件。
金属化层形成在第一衬底和第一有源器件上方并且被设计为连接各个有源器件以形成用于第一半导体管芯101和第二半导体管芯103的功能电路。在实施例中，金属化层由介电材料和导电材料的交替层形成并且可以通过任何适合的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在实施例中，可能存在通过至少一个层间介电层(ILD)与第一衬底分隔开的四个金属化层，但是金属化层的精确数目取决于第一半导体管芯101和第二半导体管芯103的设计。
形成接触焊盘107以为金属化层和第一有源器件提供外部接触。在实施例中，接触焊盘107由诸如铝的导电材料形成，但是可以可选地利用诸如铜、钨等其它合适的材料。可以使用诸如CVD或PVD的工艺来形成接触焊盘107，但是可以可选地利用其它合适的材料和方法。一旦已经沉积用于接触焊盘107的材料，则可以使用例如光刻掩蔽和蚀刻工艺将材料成形为接触焊盘107。
第一外部连接件109可以是诸如可控塌陷芯片连接(C4)凸块、球栅阵列凸块或微凸块的接触凸块，并且可以包括诸如锡的材料或诸如银或铜的其它合适的材料。在第一外部连接件109是锡焊料凸块的实施例中，可以首先通过诸如蒸发、电镀、印刷、焊料转印、植球等的任何合适的方法形成锡层来形成厚度为约100μm的第一外部连接件109。一旦在结构上形成锡层，则实施回流以将材料成形为期望的凸块形状。
然而，虽然焊料凸块被描述为第一外部连接件109的一个实施例，但是该描述旨在说明而不旨在限制。而且，也可以利用诸如导电柱(例如，铜柱)的任何合适的连接结构。所有这种结构均完全旨在包括在实施例的范围内。
通过不在旨在用于划线区域105的区内放置功能结构(诸如第一有源器件)来形成划线区域105。可以将诸如用于平坦化的测试焊盘或伪金属的其它结构放置在划线区域105内，但是一旦第一半导体管芯101和第二半导体管芯103已经彼此分离，则诸如用于平坦化的测试焊盘或伪金属的其它结构对于第一半导体管芯101或第二半导体管芯103的功能将不是必须的。划线区域105可以形成为具有介于约10μm和约200μm之间(诸如约80μm)的第一宽度W1。
一旦第一外部连接件109已经形成或者以其他方式放置在接触焊盘107上，则可以实施第一分割工艺(在图1中由标记为111的虚线框表示)以在划线区域105上方的晶圆100内并且至少部分地在第一半导体管芯101和第二半导体管芯103内创建第一开口113。在实施例中，可以通过使用锯片来切割晶圆100的一部分的方式而不是全部割穿晶圆100的方式来实施第一分割工艺111。然而，可以利用实施第一分割工艺111的任何合适的方法。
此外，可以选择或制造锯片，从而使得锯片具有成角度的边缘，当用于锯切晶圆100时，该边缘将沿着第一半导体管芯101和第二半导体管芯103形成斜切边缘115，但是也可以利用形成斜切边缘115的任何其它合适的方法。在实施例中，斜切边缘115从第一半导体管芯101的顶面朝切割区域105延伸。在实施例中，斜切边缘115可以形成为与第一半导体管芯101的顶面具有介于约20°和约45°之间的第一角度θ1。然而，可以利用任何合适的角度。
此外，通过在第一半导体管芯101内形成斜切边缘115，在第一半导体管芯101内形成第二开口(在图1中由标记为117的虚线框表示)，其中第一分割工艺111从第一半导体管芯101去除材料。在实施例中，第二开口117(位于第一开口113内)可以具有介于约20μm和约200μm之间(诸如约100μm)的第二宽度W2。此外，第二开口117也可以具有介于约20μm和约200μm之间(诸如约100μm)的第一高度H1。然而，可以利用任何合适的尺寸。
图2A示出了位于第一开口113内以及至少部分地位于第一半导体管芯101和第二半导体管芯103上方的缓冲材料201的放置。可以使用例如分配工具以液体或至少部分可流动的形式将缓冲材料201分配至第一开口113内以及第一半导体管芯101和第二半导体管芯103的部分上方。
在实施例中，缓冲材料201是用作第一半导体管芯101的材料(例如，第一半导体管芯101的主要材料，诸如半导体衬底的硅材料)和底部填充材料501(未在图2A中示出，但在下面参照图5示出和描述)之间的缓冲的材料。因此，为了用作缓冲，在一些实施例中，缓冲材料201的材料特性的强弱介于第一半导体管芯101和底部填充材料501的材料特性的强弱之间。
例如，在一些实施例中，缓冲材料201可以是具有介于第一衬底(位于第一半导体管芯101内)的第二杨氏模量与底部填充材料501的第三杨氏模量之间的第一杨氏模量的材料。在额外的实施例中，缓冲材料201也可以具有第一热膨胀系数(CTE)，其具有介于第一衬底(位于第一半导体管芯101内)的第二CTE与底部填充材料501的第三CTE之间的值。
在具体实施例中，第一衬底(位于第一半导体管芯101内)是硅，其具有160GPa的杨氏模量和2.6μm*m-1*K-1的CTE。此外，底部填充材料501是诸如环氧树脂的聚合物，其具有11GPa的杨氏模量和23μm*m-1*K-1的CTE。在这种实施例中，缓冲材料201可以是诸如环氧树脂、丙烯酸树脂或PU的材料，其具有15GPa的杨氏模量(介于硅和底部填充材料501的杨氏模量之间)和9μm*m-1*K-1的CTE(介于硅和底部填充材料501的CTE之间)。然而，可以利用任何合适的材料。
图2B示出了第一半导体管芯101、第二半导体管芯103、围绕第一半导体管芯101和第二半导体管芯103的划线区域105的至少一部分以及缓冲材料201的俯视图，其中，图2A是沿着线A-A’的图2B的截面图。在实施例中，可以将缓冲材料201分配为围绕第一半导体管芯101和第二半导体管芯103的外边缘而不会横跨第一半导体管芯101和第二半导体管芯103延伸。例如，缓冲材料201可以是液体或可流动形式并且使用例如分配工具放置在第一半导体管芯101和第二半导体管芯103的外边缘周围，但是可以利用任何合适的分配或以其他方式放置缓冲材料201的方法。
在将缓冲材料201分配在第一半导体管芯101和第二半导体管芯103的外边缘周围的实施例中，缓冲材料201可以形成为从划线区域105的边缘朝向第一半导体管芯101的中心具有介于约100μm和约200μm之间(诸如约150μm)的第三宽度W3。此外，缓冲材料201可以在第一半导体管芯101的外边缘周围一直保持第三宽度W3。因此，第一半导体管芯101上方的缓冲材料201沿着线A-A’的总宽度为两倍的第三宽度W3，或介于约20μm和约200μm之间，诸如约50μm。然而，可以利用任何合适的宽度。
此外，将缓冲材料201分配为从第一半导体管芯101，在划线区域105上方以及第二半导体管芯103上方连续地延伸。在该实施例中，缓冲材料201可以具有第四宽度W4，第四宽度W4为两倍的第三宽度W3(包括第一半导体管芯101和第二半导体管芯103上方的缓冲材料201的宽度)与划线区域105的第一宽度W1之和。因此，缓冲材料201可以具有介于约40μm和约400μm之间(诸如约130μm)之间的第四宽度W4。然而，可以利用任何合适的尺寸。
现在回到图2A，也可以在第一半导体管芯101的顶面上方将缓冲材料201分配至第二高度H2。在实施例中，第二高度H2小于第一半导体管芯101和第二衬底401(未在图2A中示出，但在下面参照图4示出和讨论)之间的最终的焊点高度Hso。例如，在实施例中，第二高度H2可以介于焊点高度Hso的三分之一与二分之一之间。因此，如果期望的焊点高度Hso介于约30μm和约150μm之间，诸如约100μm，则第二高度H2可以介于约10μm和约70μm之间，诸如约40μm。然而，可以利用任何合适的高度。
一旦已经分配缓冲材料201，则可以固化缓冲材料201以凝固缓冲材料201。在缓冲材料201是环氧树脂的实施例中，可以在介于约110℃和约150℃之间(诸如约180℃)的温度下固化缓冲材料201介于约10s和约2小时之间(诸如约30分钟)的时间段。然而，也可以利用任何合适的温度(包括室温)和任何合适的固化时间。
图3示出了第二分割工艺(在图3中由标记为301的虚线框表示)。在实施例中，可以使用锯片来割穿第一半导体管芯101和第二半导体管芯103之间的晶圆100来实施第二分割工艺301。通过割穿划线区域105内的晶圆100，第一半导体管芯101将与第二半导体管芯103以及由晶圆100形成和位于晶圆100上的其它剩余管芯分离。
虽然第二分割工艺301将第一半导体管芯101与第二半导体管芯103分离，但第二分割工艺301也将切穿并且去除缓冲材料201的材料。因此，因为缓冲材料201和第一半导体管芯101被锯切，因此在已经发生第二分割工艺301之后，缓冲材料201将具有与第一半导体管芯101的侧壁对准并且平坦的外部侧壁。
此外，虽然图3示出了垂直方向对准的缓冲材料201和第一半导体管芯101，但这旨在说明而不旨在限制。而且，可以利用任何合适的取向。例如，如果利用具有成角度的边缘的锯片，则缓冲材料201和至少部分的第一半导体管芯101可以彼此对准，但与图3中示出的垂直方向成一定角度。可以利用任何合适的取向。
而且，本领域中普通技术人员将意识到，利用锯片来分割第一半导体管芯101仅仅是一个说明性实施例，并且不旨在限制。可以可选地利用用于分割第一半导体管芯101的可选方法，诸如利用一个或多个蚀刻来分离第一半导体管芯101和第二半导体管芯103，或甚至激光烧蚀。这些方法和任何其它合适的方法可以可选地用于分割晶圆100。
图4示出了一旦已经分割第一半导体管芯101，则可以将第一半导体管芯101接合至第二衬底401。在实施例中，第二衬底401可以包括中介衬底(其中，多个器件位于中介衬底内)，中介衬底具有一个或多个通孔405、一个或多个第二接触焊盘403以及一个或多个第三接触焊盘407。
第二衬底401可以具有设置在第二衬底401的一侧或两侧上的一个或多个再分布层(未单独示出)。一个或多个通孔405可以包括将第二衬底401的第一侧处的第一RDL连接至第二衬底401的第二侧处的第二RDL的导电材料。RDL可以包括具有导线的介电层，该导线可以电连接至一个或多个通孔405。例如，第一RDL可以将一个或多个第二接触焊盘403(位于第二衬底401的第一侧上)连接至一个或多个第三接触焊盘407(位于第二衬底401的第二侧上)。第三接触焊盘407可以用于将第二衬底401(以及因此第一半导体管芯101)连接至第三衬底601(未在图4中示出，但在下面参照图6进一步示出和描述)。
在实施例中，第二接触焊盘403和第三接触焊盘407可以与以上参照图1描述的接触焊盘107类似。例如，第二接触焊盘403和第三接触焊盘407可以是诸如通过CVD和随后的图案化的工艺形成的铝的导电材料。然而，在其它实施例中，第二接触焊盘403和第三接触焊盘407可以与接触焊盘107彼此不同。
在另一实施例中，第二衬底401可以是其上形成有额外的半导体器件的另一半导体晶圆。例如，第二衬底401可以包括设计为与第一半导体管芯101协作但尚未与第二衬底401的半导体晶圆内的其它半导体器件分割的第三半导体器件(未单独示出)。
为了将第一半导体管芯101接合至第二衬底401，第一外部连接件109与第二衬底401的第二接触焊盘403对准并且放置为与第二衬底401的第二接触焊盘403物理连接。一旦位于适当的位置，则升高第一外部连接件109的温度以引发第一外部连接件109的材料的回流。一旦发生回流工艺并且之后第一外部连接件109的材料已经凝固，则第一半导体管芯101电连接和物理连接至第二衬底401。
然而，虽然回流工艺被描述为一个接合工艺，但这旨在说明而不旨在限制。而且，也可以利用任何合适的接合工艺，诸如利用铜柱的实施例中的铜与铜接合。所有这种接合工艺均旨在完全地包括在实施例的范围内。
一旦第一半导体管芯101和第二衬底401已经接合在一起，则第一半导体管芯101与第二衬底401分隔开焊点高度Hso。在实施例中，焊点高度Hso可以介于约30μm和约150μm之间，诸如约100μm。然而，可以利用任何合适的焊点高度。
图5示出了在第一半导体管芯101和第二衬底401之间施加底部填充材料501，以帮助密封和保护第一外部连接件109。在实施例中，底部填充材料501可以是诸如环氧树脂、树脂等的单一连续的材料，并且可以通过以液体形式注入底部填充材料501，从而使得其在第一半导体管芯101和第二衬底401之间流动来分配底部填充材料501。一旦已经放置底部填充材料501，则可以固化底部填充材料501以使底部填充材料501硬化。
除了密封第一外部连接件109之外，也可以将底部填充材料501也分配为在第一半导体管芯101的每侧上形成圆角，从而有助于密封和保护第一半导体管芯101的侧面。在实施例中，可以分配底部填充材料501直至圆角具有小于约2mm(诸如介于约1.5mm至约2mm之间)的第五宽度W5(远离第一半导体管芯101延伸)。此外，圆角可以具有第三高度H3，该圆角可以延伸或可以不延伸为覆盖第一半导体管芯101的全部侧壁。因此，第三高度H3可以介于约700mm和约1000mm之间。然而，可以利用任何合适的尺寸。
图6示出了一旦已经将底部填充材料501放置在第一半导体管芯101和第二衬底401之间，则可以分割第二衬底401并且之后将第二衬底401接合至第三衬底601。在实施例中，可以使用一个或多个锯片将第二衬底401分为单独件来分割第二衬底401。然而，也可以利用包括激光烧蚀或一个或多个湿蚀刻的任何合适的分割方法。
一旦分割，则使用例如第二外部连接件603将第二衬底401以及因此第一半导体管芯101接合至第三衬底601。在实施例中，第二外部连接件603可以是诸如球栅阵列凸块、微凸块或可控塌陷芯片连接(C4)凸块的接触凸块，并且可以包括诸如锡的材料或诸如银或铜的其它合适的材料。在第二外部连接件603是锡焊料凸块的实施例中，可以首先通过诸如蒸发、电镀、印刷、焊料转印、植球等的任何合适的方法形成锡层来形成厚度为约100μm的第二外部连接件603。一旦在结构上形成锡层，则实施回流以将材料成形为期望的凸块形状。
一旦已经形成第二外部连接件603，则使用第二外部连接件603将第二衬底401接合至第三衬底601。在实施例中，第三衬底601可以是印刷电路板，诸如形成为聚合物材料(诸如双马来酰亚胺三嗪(BT)、FR-4、ABF等)的多个薄层(或薄片)的堆叠件的层压衬底。然而，可以可选地利用诸如硅中介层、硅衬底、有机衬底、陶瓷衬底等的任何其它合适的衬底，并且提供支撑以及连接至第二衬底401的所有这些再分布衬底均完全旨在包括在实施例的范围内。
首先可以通过将第二衬底401与第三衬底601对准(其中，第二外部连接件603位于对应的接触焊盘之间)将第二衬底401接合至第三衬底601。一旦物理接触，则可以实施回流以回流第二外部连接件603并且将第二外部连接件603与第二衬底401和第三衬底601接合。然而，可以可选地利用任何其它合适的接合。
通过在第一半导体管芯101和底部填充材料501之间放置缓冲材料201，缓冲材料201可以用作第一半导体管芯101的材料和底部填充材料501之间的缓冲。因此，可以减少或消除可能在底部填充材料501中产生的热膨胀系数差异带来的负面影响(例如裂缝)。这种减少导致利用衬底上晶圆上芯片配置的实施例中的良率和可靠性的整体改进以及可靠性窗口的扩大。
图7示出了另一实施例，其中，第一开口113具有与第一半导体管芯101和第二半导体管芯103的顶面垂直的侧壁(而不是具有倾斜的侧壁)并且具有平坦的并且与第一半导体管芯101的顶面平行的底面。在该实施例中，使用具有直边的锯片形成第一开口113，而不是使用第一分割工艺111的成角度的锯片(如以上参照图1描述的)。在第一开口113利用直侧壁的其它实施例中，使用激光烧蚀或甚至一个或多个系列蚀刻(诸如干蚀刻)形成第一开口113，以去除晶圆100的材料并且形成具有直侧壁的第一开口113。形成具有直侧壁的第一开口113的任何合适的方法均完全地旨在包括在实施例的范围内。
在该实施例中，第一开口113可以形成为具有介于约10μm和约90μm之间(诸如约20μm)的第四高度H4。此外，第一开口113也可以从划线区域105延伸至第一半导体管芯101内介于约10μm和约90μm之间(诸如约20μm)的第六宽度W6。然而，可以利用任何合适的尺寸。
图8示出了位于第一开口113内并且至少部分地位于第一半导体管芯101和第二半导体管芯103上面的缓冲材料201的放置。在实施例中，可以如以上参照图2A描述的放置缓冲材料201。例如，缓冲材料201可以以液体或可流动形式分配在第一半导体管芯101和第二半导体管芯103的外边缘周围(以上参照图2B描述的)。然而，可以以任何合适的方式分配缓冲材料201。
在该实施例中，因为第一开口113形成为具有笔直的侧壁以及笔直的底面，因此缓冲材料201将具有笔直的并且与第一半导体管芯101的顶面平行的底面。因此，缓冲材料201也将具有与底面以直角相交的侧壁，从而使缓冲材料201形成为阶梯形状。然而，可以利用任何合适的形状。
图9示出了在放置缓冲材料201之后实施第二分割工艺301。在实施例中，可以如以上参照图3描述的实施第二分割工艺301。例如，可以利用锯片工艺、激光烧蚀工艺、一个或多个湿蚀刻等来分离晶圆100并且将第一半导体管芯101与第二半导体管芯103分离。然而，可以利用任何合适的工艺来分割晶圆100。
此外，因为缓冲材料201具有与第一半导体管芯101的顶面平行的底面，因此，由第二分割工艺301形成的缓冲材料201的侧壁(面向第二半导体管芯103的侧壁)不仅将与第一半导体管芯101的侧壁对准，而且还将在一些实施例中，与缓冲材料201的底面垂直。缓冲材料201的底面的形状的这种调整允许更大的工艺可变性并且提供用于工艺集成的附加选项。
图10示出了第一半导体管芯101与第二衬底401的接合、第一半导体管芯101和第二衬底401之间的底部填充材料501的放置以及第二衬底401与第三衬底601的接合。在实施例中，可以如以上参照图4至图6描述的实施这些工艺步骤。然而，可以实施任何合适的工艺步骤。
图11示出了另一实施例，其中，缓冲材料201具有弯曲的形状，而不是在上拐角处为方形。在该实施例中，缓冲材料201的拐角在如以上参照图3描述的第二分割工艺301期间可以是弯曲的。然而，在该实施例中，可以利用具有成角度的侧边的锯片，而不是使用具有直边的锯片。因此，锯片将以锯片的形状去除缓冲材料201的材料，从而圆化缓冲材料201的上拐角。
在实施例中，缓冲材料201的拐角可以从直角弯曲，从而使得缓冲材料201的拐角具有第一曲率。例如，缓冲材料201的拐角可以具有介于约10度和约90度之间的第一曲率，诸如约30度。然而，可以利用任何合适的形状。
图12示出了形成缓冲材料201中的圆化的拐角的另一实施例，其中，使用单独的圆化工艺(在图12中由标记为1201的虚线框表示)形成圆化的拐角，而不是使用第二分割工艺301以形成圆化的拐角。在实施例中，圆化工艺1201可以是在第二分割工艺301之后使用具有某种形状的锯片实施的第三分割工艺，以去除缓冲材料201的材料并且形成圆化的拐角。在另一实施例中，可以使用激光开槽工艺来形成圆化的拐角，从而将激光导向至缓冲材料201的期望被去除的那些部分以形成缓冲材料201的圆化的拐角。可以利用用于圆化拐角的任何合适的方法以重塑缓冲材料201。
图13A至图13B示出了又另一实施例，其中，缓冲材料201的形状调整为远离平坦的顶面(如以上参照图2A示出的)并且具有更圆的顶面。在该实施例中并且如图13A中示出的，可以选择缓冲材料201的材料以在缓冲材料201被分配之后调整缓冲材料201的形状。例如，在一个实施例中，可以选择缓冲材料201的材料以具有较高的疏水性，而在其它实施例中，可以选择缓冲材料201的材料以具有较低的疏水性，其中，疏水性修改缓冲材料201的形状。通过选择适当的材料来调整疏水性，缓冲材料201可以被调整为具有更平坦或者更圆的顶面。
在特定实施例中，缓冲材料201选择为具有SiN的亲水性或疏水性的诸如丙烯酸树脂的聚合物。鉴于该选择的材料及其特性，当分配缓冲材料201时，缓冲材料201被拉伸为不再平面化并成为弯曲的形状。因此，缓冲材料201可以在缓冲材料201的边缘处具有介于约10μm和约70μm之间(诸如约40μm)的第五高度H5，并且还可以在划线区域105的边缘上方的点处具有介于约10μm和约100μm之间(诸如约50μm)的第六高度H6。此外，缓冲材料201可以在缓冲材料201的中点处具有介于约10μm和约150μm之间(诸如约60μm)的第七高度H7。然而，可以利用任何合适的尺寸。
图13B示出了在已经选择缓冲材料201的材料来调整缓冲材料201的形状以具有更圆的顶面之后，可以分割晶圆100，可以将第一半导体管芯101接合至第二衬底401，可以将底部填充材料501放置在第一半导体管芯101和第二衬底401之间，并且可以将第二衬底401接合至第三衬底601。在实施例中，可以如以上参照图4至图6描述的实施这些工艺步骤。然而，可以实施任何合适的工艺。
图14示出了又另一实施例，其中，缓冲材料201仅分配在第一半导体管芯101的拐角处以及第二半导体管芯103的拐角处，而不是沿着第一半导体管芯101和第二半导体管芯103的整个外边缘分配。在该实施例中，缓冲材料201可以分配为使得第一半导体管芯101上方的缓冲材料201具有介于约100μm和约500μm之间(诸如约200μm)的第七宽度W7。此外，缓冲材料201可以分配为使得缓冲材料201具有介于约100μm和约500μm之间(诸如约200μm)的第一长度L1。然而，可以利用任何合适的尺寸。
通过利用沿着第一半导体管芯101和第二半导体管芯103的拐角的缓冲材料201，缓冲材料201可以提供期望的缓冲，以帮助防止沿着拐角处出现裂缝，并且利用较少量的缓冲材料201。材料的这种减少导致整体成本降低并且有助于提高产量。
图15示出了示出本文描述的至少一些工艺步骤的简化流程图。在实施例中，第一步骤1501包括实施第一分割工艺并且第二步骤1503包括在由第一分割工艺形成的开口内分配缓冲材料。一旦已经分配并且固化缓冲材料，则在第三步骤1505中实施第二分割工艺，并且在第四步骤1507中，将分割的半导体管芯接合至衬底。一旦接合，则在第五步骤1509中将底部填充材料分配在分割的半导体管芯和衬底之间并且在第六步骤1511中将分割的组合接合至另一衬底。
在实施例中，制造器件的方法包括沿着半导体管芯的外边缘形成开口；用缓冲材料过填充开口的至少部分；以及邻近缓冲材料放置底部填充材料。在实施例中，该方法还包括在过填充开口之后并且在放置底部填充材料之前，从半导体晶圆分割半导体管芯。在实施例中，通过用锯切割穿缓冲材料和半导体晶圆来实施分割半导体管芯。在实施例中，该方法还包括在邻近缓冲材料放置底部填充材料之前，将半导体管芯接合至第一衬底。在实施例中，在放置底部填充材料期间，底部填充材料在第一衬底和缓冲材料之间流动。在实施例中，该方法还包括将第一衬底接合至第二衬底。在实施例中，用缓冲材料过填充开口的至少部分沿着半导体管芯的整个周边留下缓冲材料。
在另一实施例中，制造器件的方法包括：部分地分割第一晶圆以在第一晶圆内形成第一开口。第一晶圆包括第一材料的半导体衬底，第一材料的第一特性具有第一值，其中，第一开口至少部分地延伸至第一半导体器件和第二半导体器件内；用缓冲材料填充第一开口的至少部分，缓冲材料的第一特性具有与第一值不同的第二值；在填充第一开口之后完全地分割第一晶圆，其中，在完全地分割第一晶圆之后，缓冲材料保留在第一半导体器件上方的第一开口内；将第一半导体器件接合至衬底；并且将底部填充材料分配在第一半导体器件和衬底之间，其中，底部填充材料的第一特性具有第三值，第二值介于第一值和第三值之间。在实施例中，部分地分割第一晶圆形成具有斜切边缘的第一开口。在实施例中，部分地分割第一晶圆形成具有垂直侧边的第一开口。在实施例中，第一特性是杨氏模量。在实施例中，第一特性是热膨胀系数。在实施例中，填充第一开口的至少部分将缓冲材料放置在第一半导体器件的拐角区域内，其中，缓冲材料没有延伸超出第一半导体器件的拐角区域。在实施例中，该方法还包括在填充第一开口的至少部分之后，圆化缓冲材料。
在又另一实施例中，器件包括第一半导体器件，第一半导体器件包括第一外部连接件；沿着第一半导体器件的外边缘的缓冲材料；以及从第一半导体器件的侧壁延伸，围绕缓冲材料并且到达至缓冲材料和第一外部连接件之间的点的底部填充材料。在实施例中，底部填充材料是连续的第一材料。在实施例中，缓冲材料至少部分地延伸至第一半导体器件内。在实施例中，缓冲材料在第一半导体器件内具有斜切边缘。在实施例中，第一半导体器件内的缓冲材料具有与第一半导体器件的顶面平行的第一侧边和与第一侧边成角度的第二侧边。在实施例中，第一半导体器件内的缓冲材料的侧壁连接至第一半导体器件的侧壁。
在又另一实施例中，制造器件的方法包括提供具有第一半导体器件和第二半导体器件的半导体晶圆；在第一半导体器件和第二半导体器件之间的划线区域上方形成第一开口；将第一材料分配至第一开口内；以及在分割工艺中去除第一材料的部分，其中，分割工艺将第一半导体器件与第二半导体器件分离，分割工艺留下第一半导体器件上方的第一材料的第一部分，第一部分具有小于200μm的宽度。在实施例中，去除第一材料的部分留下垂直拐角。在实施例中，去除第一材料的部分留下圆化的拐角。在实施例中，形成第一开口形成斜切边缘。
在又另一实施例中，器件包括第一半导体器件，第一半导体器件包括顶面和侧壁，其中，顶面和侧壁由与该顶面和侧壁未对准的第一表面连接；与顶面物理接触并且覆盖第一表面的缓冲材料，其中，缓冲材料的第二表面与侧壁对准；以及与顶面和缓冲材料物理接触的底部填充材料。在实施例中，缓冲材料具有阶梯形状。在实施例中，第一表面是斜切表面。
在又另一实施例中，器件包括半导体器件，该半导体器件在半导体器件的拐角处具有开口；至少部分地位于开口内的缓冲材料，其中，缓冲材料没有横跨半导体器件延伸；将衬底接合至半导体器件；以及位于半导体器件和衬底之间的底部填充材料，其中，缓冲材料的第一特性的值介于半导体器件的值和底部填充材料的值之间。在实施例中，缓冲材料具有与半导体器件的第二侧壁对准的第一侧壁。在实施例中，缓冲材料具有背离半导体器件的圆化的表面。
根据本发明的一些实施例，提供了一种制造半导体器件的方法，所述方法包括：沿着半导体管芯的外边缘形成开口；用缓冲材料过填充所述开口的至少部分；以及邻近所述缓冲材料放置底部填充材料。
在上述方法中，还包括：在过填充所述开口之后并且在放置所述底部填充材料之前，从半导体晶圆分割所述半导体管芯。
在上述方法中，通过用锯切割穿所述缓冲材料和所述半导体晶圆来实施分割所述半导体管芯。
在上述方法中，还包括：在邻近所述缓冲材料放置所述底部填充材料之前，将所述半导体管芯接合至第一衬底。
在上述方法中，在放置所述底部填充材料期间，所述底部填充材料在所述第一衬底和所述缓冲材料之间流动。
在上述方法中，还包括：将所述第一衬底接合至第二衬底。
在上述方法中，用所述缓冲材料过填充所述开口的至少部分留下沿着所述半导体管芯的整个周边的所述缓冲材料。
根据本发明的另一些实施例，还提供了一种制造半导体器件的方法，所述方法包括：部分地分割第一晶圆以在所述第一晶圆内形成第一开口，所述第一晶圆包括第一材料的半导体衬底，所述第一材料的第一特性具有第一值，其中，所述第一开口至少部分地延伸至第一半导体器件和第二半导体器件内；用缓冲材料填充所述第一开口的至少部分，所述缓冲材料的所述第一特性具有与所述第一值不同的第二值；在填充所述第一开口之后，完全地分割所述第一晶圆，其中，在完全地分割所述第一晶圆之后，所述缓冲材料保留在所述第一半导体器件上方的所述第一开口内；将所述第一半导体器件接合至衬底；以及将底部填充材料分配在所述第一半导体器件和所述衬底之间，其中，所述底部填充材料的所述第一特性具有第三值，所述第二值介于所述第一值和所述第三值之间。
在上述方法中，部分地分割所述第一晶圆形成具有斜切边缘的所述第一开口。
在上述方法中，部分地分割所述第一晶圆形成具有垂直侧边的所述第一开口。
在上述方法中，所述第一特性是杨氏模量。
在上述方法中，所述第一特性是热膨胀系数。
在上述方法中，填充所述第一开口的至少部分将所述缓冲材料放置在所述第一半导体器件的拐角区域内，其中，所述缓冲材料没有延伸超出所述第一半导体器件的拐角区域。
在上述方法中，还包括在填充所述第一开口的至少部分之后，圆化所述缓冲材料。
根据本发明的又一些实施例，还提供了一种半导体器件，包括：第一半导体器件，所述第一半导体器件包括第一外部连接件；缓冲材料，沿着所述第一半导体器件的外边缘；以及底部填充材料，从所述第一半导体器件的侧壁、所述缓冲材料周围延伸至所述缓冲材料和所述第一外部连接件之间的点。
在上述半导体器件中，所述底部填充材料是连续的第一材料。
在上述半导体器件中，所述缓冲材料至少部分地延伸至所述第一半导体器件内。
在上述半导体器件中，所述缓冲材料在所述第一半导体器件内具有斜切边缘。
在上述半导体器件中，所述第一半导体器件内的所述缓冲材料具有与所述第一半导体器件的顶面平行的第一侧边和与所述第一侧边成角度的第二侧边。
在上述半导体器件中，所述第一半导体器件内的所述缓冲材料的侧壁连接至所述第一半导体器件的侧壁。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
沿着半导体管芯的外边缘形成开口；
用缓冲材料过填充所述开口的至少部分；以及
邻近所述缓冲材料放置底部填充材料。
2.根据权利要求1所述的方法，还包括：在过填充所述开口之后并且在放置所述底部填充材料之前，从半导体晶圆分割所述半导体管芯。
3.根据权利要求2所述的方法，其中，通过用锯切割穿所述缓冲材料和所述半导体晶圆来实施分割所述半导体管芯。
4.根据权利要求1所述的方法，还包括：在邻近所述缓冲材料放置所述底部填充材料之前，将所述半导体管芯接合至第一衬底。
5.根据权利要求4所述的方法，其中，在放置所述底部填充材料期间，所述底部填充材料在所述第一衬底和所述缓冲材料之间流动。
6.根据权利要求5所述的方法，还包括：将所述第一衬底接合至第二衬底。
7.根据权利要求1所述的方法，其中，用所述缓冲材料过填充所述开口的至少部分留下沿着所述半导体管芯的整个周边的所述缓冲材料。
8.一种制造半导体器件的方法，所述方法包括：
部分地分割第一晶圆以在所述第一晶圆内形成第一开口，所述第一晶圆包括第一材料的半导体衬底，所述第一材料的第一特性具有第一值，其中，所述第一开口至少部分地延伸至第一半导体器件和第二半导体器件内；
用缓冲材料填充所述第一开口的至少部分，所述缓冲材料的所述第一特性具有与所述第一值不同的第二值；
在填充所述第一开口之后，完全地分割所述第一晶圆，其中，在完全地分割所述第一晶圆之后，所述缓冲材料保留在所述第一半导体器件上方的所述第一开口内；
将所述第一半导体器件接合至衬底；以及
将底部填充材料分配在所述第一半导体器件和所述衬底之间，其中，所述底部填充材料的所述第一特性具有第三值，所述第二值介于所述第一值和所述第三值之间。
9.根据权利要求8所述的方法，其中，部分地分割所述第一晶圆形成具有斜切边缘的所述第一开口。
10.一种半导体器件，包括：
第一半导体器件，所述第一半导体器件包括第一外部连接件；
缓冲材料，沿着所述第一半导体器件的外边缘；以及
底部填充材料，从所述第一半导体器件的侧壁、所述缓冲材料周围延伸至所述缓冲材料和所述第一外部连接件之间的点。
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