TWI820316B - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TWI820316B TWI820316B TW109109272A TW109109272A TWI820316B TW I820316 B TWI820316 B TW I820316B TW 109109272 A TW109109272 A TW 109109272A TW 109109272 A TW109109272 A TW 109109272A TW I820316 B TWI820316 B TW I820316B
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- Prior art keywords
- intermediate layer
- semiconductor package
- molding member
- semiconductor wafer
- semiconductor
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Abstract
一種半導體封裝包括:封裝基板;下部半導體晶片,位於所述封裝基板上;中間層,位於所述下部半導體晶片上,所述中間層包括彼此間隔開的多個片段;上部半導體晶片,位於所述中間層上;以及模制構件,覆蓋所述下部半導體晶片及所述中間層。
Description
本發明實施例有關一種半導體封裝,且更具體來說,有關一種包括中間層的半導體封裝。[ 相關申請的交叉參考 ]
在2019年4月15日在韓國智慧財產權局提出申請且名稱為“半導體封裝(Semiconductor Package)”的韓國專利申請第10-2019-0043784號全文併入本申請供參考。
近來,電子產品市場中對便攜裝置的需求已迅速增加。因此,存在對電子產品中的電子元件的小型化及重量減小的持續需求。
需要包括這種電子元件的半導體封裝來在減小這種電子元件的體積的同時處理大量資料。因此,還存在對安裝在這種半導體封裝上的高度集成的及單一封裝的半導體晶片的需求。因此,已使用中間層來將半導體晶片高效地排列在半導體封裝的有限結構中。
根據實施例的一方面,提供一種半導體封裝,所述半導體封裝包括:封裝基板;下部半導體晶片,設置在所述封裝基板上;中間層,設置在所述下部半導體晶片上且包括彼此間隔開的多個片段;上部半導體晶片,設置在所述中間層上;以及模制構件,覆蓋所述下部半導體晶片及所述中間層。
根據實施例的一方面,提供一種半導體封裝,所述半導體封裝包括:封裝基板;下部半導體晶片,設置在所述封裝基板上;中間層,設置在所述下部半導體晶片上且通過形成在所述中間層的上表面中的凹槽而劃分成多個區;上部半導體晶片,設置在所述中間層上;接合線,將所述封裝基板連接到所述中間層;以及模制構件,覆蓋所述下部半導體晶片、所述中間層及所述接合線,其中所述模制構件的熱膨脹係數大於所述中間層的熱膨脹係數。
根據實施例的一方面,提供一種半導體封裝,所述半導體封裝包括:封裝基板;下部半導體晶片,設置在所述封裝基板上;中間層,設置在所述下部半導體晶片上且通過形成在所述中間層的側表面中的凹槽而劃分成多個區;上部半導體晶片,設置在所述中間層上;接合線,將所述封裝基板連接到所述中間層;以及模制構件,覆蓋所述下部半導體晶片、所述中間層及所述接合線,其中所述模制構件的熱膨脹係數大於所述中間層的熱膨脹係數。
在下文中,將參照所附圖式詳細闡述示例性實施例。
圖1A到圖1D是示出根據示例性實施例的半導體封裝的圖。具體來說,圖1A是半導體封裝10的剖視圖,圖1B是半導體封裝10的平面圖,圖1C是半導體封裝10中的中間層300的透視圖,且圖1D是半導體封裝10中的上部半導體晶片400的仰視圖。
為便於解釋,圖1B中省略了模制構件MB及上部半導體晶片400來示出下部半導體晶片200上的中間層300的俯視圖。此外,為方便起見只在圖1B及圖1C中在中間層300的單個片段上示出再分佈層結構320,且再分佈層結構320可形成在中間層300的每一片段上(例如,圖1A)。此外,圖1A的橫截面反映穿過中間層300的兩個相鄰片段中的元件321及325的橫截面,且為方便起見,從圖1A省略了對元件321及325進行連接的元件323。
參照圖1A到圖1D,半導體封裝10可包括:封裝基板100;下部半導體晶片200,位於封裝基板100上;中間層300,位於下部半導體晶片200上;以及上部半導體晶片400,位於中間層300上。中間層300可包括多個片段(即,彼此間隔開的多個部分(例如,圖1C)),如將在下面更詳細地闡述。
詳細來說,封裝基板100可為支撐基板。舉例來說,封裝基板100可包括主體部分110、下部保護層及上部保護層。封裝基板100可基於印刷電路板(printed circuit board,PCB)、晶圓基板、陶瓷基板、玻璃基板等形成。舉例來說,在半導體封裝10中,封裝基板100可為PCB。
在封裝基板100中可形成有佈線140。佈線140可通過例如支柱結構、焊料凸塊、焊料球及焊料層中的至少一者電連接到下部半導體晶片200,支柱結構、焊料凸塊、焊料球及焊料層連接到形成在封裝基板100的上表面中的上電極焊盤120。
此外,在形成在封裝基板100的下表面中的下電極焊盤130上可設置有外部連接端子150。封裝基板100可通過外部連接端子150電連接到電子產品的模組基板或系統板。
舉例來說,佈線140的多個層或單個層可形成在主體部分110中,且外部連接端子150可通過佈線140電連接到下部半導體晶片200。下部保護層及上部保護層可保護主體部分110且可包含例如阻焊劑。
當封裝基板100是PCB時,主體部分110可包含熱固性聚合物。舉例來說,主體部分110可通過將聚合物材料(例如熱固性樹脂、環氧樹脂(例如,阻燃劑4(flame retardant 4,FR-4)、雙馬來醯亞胺三嗪(bismaleimide triazine,BT)、味之素構成膜(Ajinomoto build up film,ABF))或酚醛樹脂)壓縮到預定厚度以變薄、對聚合物材料的兩側施加銅箔以及通過圖案化製程形成作為用於電信號傳輸的路徑的佈線140來實施。除了上電極焊盤120及下電極焊盤130之外,阻焊劑可塗布在主體部分110的全部下表面及上表面之上以形成下部保護層及上部保護層。由於構成封裝基板100的材料的特性(例如,由於封裝基板100的主體部分110中使用的熱固性聚合物),與比較半導體基板的熱膨脹係數相比,封裝基板100的熱膨脹係數可能相對大。
一般來說,PCB可被分類成單層PCB及雙層PCB,單層PCB僅在一側上形成有佈線140,雙層PCB在兩側上形成有佈線140。舉例來說,通過使用絕緣體(例如,預浸體),銅箔的層的數目可為三個或更多個,且具有多層結構的PCB可通過根據要形成的銅箔的層的數目形成三條或更多條佈線140來實施。然而,封裝基板100並非僅限於上述印刷電路板的結構及材料。
下部半導體晶片200可實施為單個邏輯晶片(例如,微處理器、圖形處理器、信號處理器、網路處理器、晶片組、音訊轉碼器、視頻轉碼器、應用處理器、片上系統等)。然而,下部半導體晶片200並非僅限於此。
另外,下部半導體晶片200可包括半導體基板210及形成在半導體基板210的下表面中的晶片焊盤220。晶片焊盤220可通過佈線結構連接到下部半導體晶片200的邏輯裝置。
構成下部半導體晶片200的半導體基板210可具有主動表面及與主動表面相對的非主動表面。半導體基板210的主動表面可為面對封裝基板100的上表面的表面。在半導體基板210的主動表面上可形成有多個主動裝置及/或被動裝置。此外,晶片焊盤220可形成在半導體基板210的主動表面上。
晶片焊盤220可通過連接端子230直接連接到設置在封裝基板100的上表面中的上電極焊盤120。可使用晶片焊盤220及上電極焊盤120作為用於下部半導體晶片200與封裝基板100之間的信號傳輸的端子。晶片焊盤220及上電極焊盤120的數目及晶片焊盤220及上電極焊盤120的排列方式是例示性地示出的且並非僅限於此。
連接端子230可設置在晶片焊盤220上。連接端子230可將下部半導體晶片200電連接到封裝基板100。通過連接端子230,可從外部提供用於下部半導體晶片200的操作的控制信號、電源供應信號及接地信號中的至少一者,可從外部提供要存儲在下部半導體晶片200中的資料信號,或者可向外部提供存儲在下部半導體晶片200中的資料。舉例來說,連接端子230可為倒裝晶片連接,例如,連接端子230可包括支柱結構、焊料凸塊、焊料球及焊料層中的至少一者。
舉例來說,半導體基板210可包括矽晶圓,所述矽晶圓包含矽(Si)(例如,晶體矽、多晶矽或非晶矽)。在另一實例中,半導體基板210可包含半導體元素(例如,鍺)或化合物半導體(例如碳化矽(SiC)、砷化鎵(GaAs)、砷化銦(InAs)及磷化銦(InP))。在根據實施例的半導體封裝10中,半導體基板210可為矽晶圓。所述矽晶圓可具有與封裝基板100的熱膨脹係數相比可相對小的、約7.6 ppm/K的熱膨脹係數。
半導體基板210可具有絕緣體上矽(silicon on insulator,SOI)結構。舉例來說,半導體基板210可包括掩埋氧化物(buried oxide,BOX)層。半導體基板210可包括導電區(例如,摻雜有雜質的井或摻雜有雜質的結構)。另外,半導體基板210可具有各種裝置隔離結構(例如,淺溝槽隔離(shallow trench isolation,STI)結構等)。
中間層300可位於下部半導體晶片200與上部半導體晶片400之間,例如,中間層300可位於下部半導體晶片200的半導體基板210的非主動表面上。中間層300可包括基礎基板310及形成在基礎基板310中的再分佈層結構320。舉例來說,如圖1A所示,再分佈層結構320可形成在基礎基板310的上表面中以具有與基礎基板310的上表面等高的上表面。
基礎基板310可包括矽晶圓,所述矽晶圓包含矽(Si)(例如,晶體矽、多晶矽或非晶矽)。也就是說,基礎基板310及半導體基板210二者均可包括矽晶圓,且因此,基礎基板310的熱膨脹係數相對小於封裝基板100的熱膨脹係數。
參照圖1A及圖1B,再分佈層結構320可包括電連接到上部半導體晶片400的上表面焊盤321、電連接到接合線BW的接合焊盤325以及將上表面焊盤321電連接到接合焊盤325的再分佈層323。舉例來說,如圖1B所示,再分佈層結構320可包括多個上表面焊盤321、多個接合焊盤325以及將每一上表面焊盤321電連接到相應的接合焊盤325的多個再分佈層323。此處,上表面焊盤321可被形成為從模制構件MB暴露出,例如,可移除模制構件MB的一部分以暴露出上表面焊盤321的上表面。儘管在圖1B及圖1C中再分佈層結構320被示出為僅形成在中間層300的單個片段上,然而此是為解釋起見,且再分佈層結構320也可形成在中間層300的其它片段中,例如,圖1A所示兩個相鄰的片段或中間層300的所有片段。
舉例來說,中間層300還可包括電路區。舉例來說,在中間層300的電路區中可形成能夠控制上部半導體晶片400的電容負載的緩衝電路。在一些實施例中,電路區可包括半導體積體電路,所述半導體積體電路包括例如以下中的至少一者:電晶體、二極體、電容器及電阻器。在另一實例中,可省略電路區。
在一些實施例中,中間層300可設置在下部半導體晶片200與上部半導體晶片400之間的區域中以便分別與下部半導體晶片200及上部半導體晶片400重疊(圖1A)。舉例來說,在平面圖中,中間層300的一部分可與下部半導體晶片200重疊,且中間層300的整個部分可與上部半導體晶片400重疊(圖1A)。舉例來說,在平面圖中,中間層300的最外邊緣可延伸超過下部半導體晶片200的邊緣(圖1B),且上部半導體晶片400的邊緣可延伸超過中間層300的最外邊緣(圖1A)。
如圖1B及圖1C所示,根據實施例,中間層300可包括多個片段300a。舉例來說,如圖1B所示,中間層300可包括例如以矩陣圖案沿X方向及Y方向彼此間隔開的多個分立部分。舉例來說,在平面圖中,中間層300可包括2N個片段(N是自然數),且2N個片段(即,部分)可以兩側對稱結構設置在下部半導體晶片200上,且在下部半導體晶片200之間具有空間。因此,下部半導體晶片200的上表面的對應於形成在相鄰的2N個片段(例如,部分)之間的空的空間的一部分(例如,彼此間隔開的部分)可不與中間層300重疊,即,下部半導體晶片200可與中間層300的部分300a之間的空的空間重疊(圖1B)。
詳細來說,中間層300的片段300a(即,部分300a(片段300a與部分300a可在下文中互換使用))可在第一方向上(即,在X方向上)彼此間隔開第一距離DX,且在第二方向上(即,在Y方向上)彼此間隔開第二距離DY。片段300a(即,部分300a)中的每一者可被配置成具有相同或不同的形狀以及相同或不同的尺寸(例如,XY平面中的面積及Z方向上的厚度)。第一距離DX與第二距離DY也可被配置成具有相同或不同的長度。
在根據實施例的半導體封裝10中,由於中間層300可包括所述多個片段300a(即,部分300a),因此所述多個片段300a(即,部分300a)之間的空間可填充有模制構件MB。舉例來說,參照圖1A到圖1C,中間層300可包括在下部半導體晶片200上例如以矩陣圖案在X方向及Y方向上沿行及列排列的片段300a,其中模制構件MB的部分例如完全填充相鄰的片段300a之間在X方向及Y方向上的空間。由此,中間層300的其之間具有模制構件MB的部分的片段300a提供由具有不同的膨脹係數的不同的材料構成的中間層。如稍後將更詳細地闡述,中間層300的熱膨脹係數可不同於(例如,低於)模制構件MB的熱膨脹係數。
上部半導體晶片400可位於中間層300上,且包括例如揮發性記憶體晶片及/或非揮發性記憶體晶片。在另一實例中,上部半導體晶片400可包括高頻寬存儲晶片。揮發性記憶體晶片可包括例如動態隨機存取記憶體(dynamic random-access memory,DRAM)、靜態隨機存取記憶體(static RAM,SRAM)、晶閘管隨機存取記憶體(thyristor RAM,TRAM)、零電容隨機存取記憶體(zero capacitor RAM,ZRAM)等。非揮發性記憶體晶片可包括例如快閃記憶體、磁性隨機存取記憶體(magnetic RAM,MRAM)、自旋轉移力矩隨機存取記憶體(spin -transfer torque MRAM,STT-MRAM)、鐵電隨機存取記憶體(ferroelectric RAM,FRAM)、相變隨機存取記憶體(phase change RAM,PRAM)、電阻式隨機存取記憶體(resistive RAM,RRAM)等。
在一些實施例中,上部半導體晶片400可包括由能夠彼此合併資料的多個存儲晶片形成的堆疊。在這種情形中,構成上部半導體晶片400的每一存儲晶片薄片均可包括具有彼此相對的主動表面與非主動表面的半導體基板、形成在主動表面上的記憶體裝置以及矽通孔(through silicon via,TSV)。在封裝系統中,其中多個存儲晶片集成到一個封裝中,根據半導體封裝10的用途而定,構成上部半導體晶片400的存儲晶片薄片的數目可不同。也就是說,構成上部半導體晶片400的存儲晶片薄片的數目並非僅限於特定數目。
上部半導體晶片400可包括半導體基板堆疊410及形成在半導體基板堆疊410的最下部表面中的晶片焊盤420。晶片焊盤420可通過佈線結構連接到上部半導體晶片400的記憶體裝置。
晶片焊盤420可通過連接端子430直接連接到設置在中間層300的上表面中的上表面焊盤321。可使用晶片焊盤420及上表面焊盤321作為用於上部半導體晶片400與中間層300之間的信號傳輸的端子。晶片焊盤420及上表面焊盤321的數目及其排列方式是例示性地示出的且並非僅限於此。
連接端子430可設置在晶片焊盤420上。由於連接端子430的高度,上部半導體晶片400可與模制構件MB間隔開。連接端子430可將上部半導體晶片400電連接到中間層300。通過連接端子430,可從外部提供用於上部半導體晶片400的操作的控制信號、電源供應信號及接地信號中的至少一者,可從外部提供要存儲在上部半導體晶片400中的資料信號,或者可向外部提供存儲在上部半導體晶片400中的資料。
另外,端子區400R(圖1D)的數目等於中間層300的片段(即,部分)的數目,在端子區400R中,晶片焊盤420以群組排列在上部半導體晶片400的下表面(即,面對中間層300的表面)上。端子區400R可被配置成與其中設置有中間層300的片段的區域對應(例如,重疊),例如每一端子區400R與中間層300的對應部分具有相同的大小及形狀以彼此完全重疊。也就是說,在上部半導體晶片400的製造製程中,可慮及中間層300的再分佈層結構320來設計晶片焊盤420。
黏合構件DAF可被設置成黏附到下部半導體晶片200及中間層300。黏合構件DAF可包括裸片貼附膜。裸片貼附膜可被分類成無機黏合劑及聚合物黏合劑。聚合物一般來說可被分類成熱固性樹脂及熱塑性樹脂,且混合型聚合物可通過將這兩種組分混合製成。
接合線BW可例如通過接合焊盤325將封裝基板100電連接到中間層300。接合線BW可包含例如金(Au)、銀(Ag)、銅(Cu)及鋁(Al)中的至少一者。在一些實施例中,接合線BW可通過熱壓縮連接方法(thermo compression connection method)或超音波連接方法(ultrasonic connection method)中的任何一種來連接,且也可通過將這些方法組合在一起的熱超聲連接方法(thermo sonic connection method)來連接。
模制構件MB可保護下部半導體晶片200及中間層300免受外部影響(例如,污染及衝擊)。為實行這種保護,模制構件MB的厚度可被形成為至少覆蓋下部半導體晶片200及中間層300。
舉例來說,如圖1A所示,模制構件MB可例如連續地從封裝基板100的主體部分110的上表面沿例如下部半導體晶片200及中間層300的整個側表面延伸到比中間層300的上表面高的高度(相對於封裝基板100的底部)。舉例來說,如圖1A進一步示出,模制構件MB可沿中間層300的片段300a中的每一者的整個側表面延伸以例如完全填充中間層300的片段300a中的相鄰片段300a之間的空間。舉例來說,如圖1A進一步示出,模制構件MB可至少部分地覆蓋中間層300的上表面,例如,模制構件MB可至少部分地暴露出中間層300的上表面上的上表面焊盤321的上表面。模制構件MB的寬度(例如,模制構件MB的最外側表面之間沿X方向的距離)可與半導體封裝10的例如沿X方向的寬度實質上相同,因為模制構件MB可覆蓋封裝基板100的全部。
舉例來說,模制構件MB可包含環氧模塑膠。環氧模塑膠可具有約10 ppm/K到約30 ppm/K的熱膨脹係數。然而,模制構件MB並非僅限於環氧模塑膠,且可包括各種材料,例如環氧系材料、熱固性材料、熱塑性材料、紫外線(Ultraviolet,UV)處理材料等。
舉例來說,在通過注入製程將適當量的模制材料注入到封裝基板100上之後,模制構件MB可通過固化製程形成半導體封裝10的外部形狀。視需要,通過在使用壓制機的壓制製程中向模制材料施加壓力,可形成半導體封裝10的外部形狀。此處,可慮及物理性質(例如,模制材料的黏度等)來設定製程條件(例如,注入模制材料與壓制模制材料之間的延遲時間、要注入的模制材料的量、壓制溫度及壓力等)。根據模制材料而定,模制構件MB的熱膨脹係數可發生變化。
在封裝基板100與下部半導體晶片200之間可形成底部填充件UF。在連接端子230與下部半導體晶片200之間的電連接過程中,可在封裝基板100與下部半導體晶片200之間形成間隙。這種間隙可能導致下部半導體晶片200與封裝基板100之間的連接可靠性的問題,且因此,可注入底部填充件UF來加強連接。在一些情形中,可使用模制底部填充件(molded underfill,MUF)製程來代替底部填充件UF。
一般的半導體封裝可包括封裝基板、半導體晶片、中間層、模制構件等。在這種一般的半導體封裝中,構成封裝基板、半導體晶片、中間層及模制構件的材料可彼此不同,且每一組成元件可具有彼此不同的熱膨脹係數。因此,當在製造半導體封裝的製程期間發生溫度改變時,每一組成元件均可彼此不同地收縮或膨脹,從而引起半導體封裝中的變形(例如,翹曲)。半導體封裝的這種變形被稱為翹曲。
舉例來說,在一般的半導體封裝中,具有相對大的熱膨脹係數的封裝基板可能在室溫下收縮,從而在半導體晶片及半導體晶片上的中間層上施加拉伸應力。此外,在高溫下,具有相對大的熱膨脹係數的封裝基板可膨脹,從而在半導體晶片及半導體晶片上的中間層上施加壓縮應力。由此,由於拉伸應力或壓縮應力引起的應力集中,可能發生半導體封裝的翹曲,從而降低半導體封裝的生產率及可靠性。
相反,根據實施例,半導體封裝10包括中間層300,中間層300具有彼此間隔開的所述多個片段300a(即,部分300a),且在所述多個片段300a之間填充有模制構件MB。由此,可減輕半導體封裝10的翹曲。也就是說,由於具有大的熱膨脹係數的元件(即,模制構件MB的部分)及具有小的熱膨脹係數的元件(即,中間層300的片段300a)可適當地(例如,交替地)排列在同一平面上,因此可減輕半導體封裝10的翹曲。
詳細來說,當具有相對大的熱膨脹係數的封裝基板100在室溫下收縮時,也具有大的熱膨脹係數並填充中間層300的片段300a之間的空間的模制構件MB也收縮。因此,中間層300中的交替片段300a以及模制構件MB的部分的整體結構可收縮,即,由於模制構件MB收縮導致相鄰的片段300a之間的空間較小,從而消除下部半導體晶片200及中間層300上的拉伸應力。由此,可減輕半導體封裝10的翹曲。
相似地,當具有相對大的熱膨脹係數的封裝基板100在高溫下膨脹時,也具有大的熱膨脹係數並填充中間層300的片段300a之間的空間的模制構件MB也膨脹。因此,中間層300中的交替片段300a以及模制構件MB的部分的整體結構可膨脹,即,由於模制構件MB的膨脹導致相鄰的片段300a之間的空間較大,從而消除下部半導體晶片200及中間層300上的壓縮應力。由此,可減輕半導體封裝10的翹曲。
因此,根據實施例的半導體封裝10可使由翹曲引起的應力集中最小化。因此,可提高半導體封裝10的生產率及可靠性。
圖2A到圖9B是示出根據示例性實施例的半導體封裝的圖。構成以下半導體封裝20到半導體封裝90的大部分元件及構成所述元件的材料與參照圖1A到圖1D闡述的該些組件及材料實質上相同或相似。因此,為便於解釋,將僅詳細闡述相對於上述半導體封裝10(參見圖1A)的不同之處。
參照圖2A及圖2B,圖2A是半導體封裝20的剖視圖,且圖2B是半導體封裝20的平面圖。為便於解釋,在圖2B中省略了模制構件MB及上部半導體晶片400。
如圖2A及圖2B一起所示,半導體封裝20可包括封裝基板100、下部半導體晶片200、包括彼此間隔開的多個片段的中間層302、上部半導體晶片400以及第一接合線BW1及第二接合線BW2。第一接合線BW1可將封裝基板100電連接到中間層302,且第二接合線BW2可將中間層302的片段電連接到彼此。
詳細來說,在中間層302的每一片段上可設置有第二接合焊盤327,且第二接合線BW2可被形成為將中間層302的相鄰的片段的第二接合焊盤327連接到彼此。第二接合線BW2可通過將中間層302的所述多個片段電連接到彼此來實現用於與上部半導體晶片400進行信號傳輸的各種佈線設計。第二接合焊盤327及第二接合線BW2的數目及第二接合焊盤327及第二接合線BW2的排列方式是例示性地示出的且並非僅限於此。
參照圖3A及圖3B,圖3A是半導體封裝30的剖視圖,且圖3B是半導體封裝30的平面圖。為便於解釋,在圖3B中省略了模制構件MB及上部半導體晶片400。
如圖3A及圖3B一起所示,半導體封裝30可包括封裝基板100、下部半導體晶片200、由兩個片段構成的中間層303及上部半導體晶片400。在半導體封裝30中,中間層303可被劃分成例如僅兩個片段。也就是說,中間層303仍可包括2N個片段(N是1),且在平面圖中,所述兩個片段可以對稱結構排列。
此外,中間層303可被配置成使得所述兩個片段排列成在第二方向(Y方向)上彼此隔開第二距離DY。所述兩個片段可被配置成具有相同的面積或不同的面積。
此外,在中間層303上可形成有第二再分佈層329以實現用於與上部半導體晶片400進行信號傳輸的各種佈線設計。第二再分佈層329的數目及第二再分佈層329的排列方式是例示性地示出的且並非僅限於此。
參照圖4A及圖4B,圖4A是半導體封裝40的剖視圖,且圖4B是半導體封裝40的平面圖。為便於解釋,在圖4B中省略了第一模制構件MB1及上部半導體晶片400。
如圖4A及圖4B一起所示,半導體封裝40可包括封裝基板100、下部半導體晶片200、包括多個片段的中間層304、上部半導體晶片400以及第一模制構件MB1及第二模制構件MB2。第一模制構件MB1可例如僅形成在下部半導體晶片200及中間層304的外部部分上。第二模制構件MB2可形成在中間層304的所述多個片段之間的空間中(圖4A及圖4B中的陰影區)。
詳細來說,在半導體封裝40中,模制構件可包括具有彼此不同的熱膨脹係數的至少兩個部分。在一些實施例中,半導體封裝40可包括具有彼此不同的熱膨脹係數的第一模制構件MB1與第二模制構件MB2。舉例來說,第一模制構件MB1的熱膨脹係數可小於第二模制構件MB2的熱膨脹係數。也就是說,慮及第一模制構件MB1及第二模制構件MB2的熱膨脹係數,可有效地控制向半導體封裝40施加的拉伸應力及壓縮應力以使翹曲最小化。
參照圖5A及圖5B,圖5A是半導體封裝50的剖視圖,且圖5B是半導體封裝50的平面圖。為便於解釋,在圖5B中省略了第一模制構件MB1及上部半導體晶片400。
如圖5A及圖5B所示,半導體封裝50可包括封裝基板100、下部半導體晶片200、包括多個片段的中間層305、上部半導體晶片400、第一模制構件MB1以及填充中間層305的片段之間的空間的第三模制構件MB3及第四模制構件MB4。
詳細來說,半導體封裝50可包括形成在中間層305的所述多個片段之間的空間中的第三模制構件MB3及第四模制構件MB4以及形成在下部半導體晶片200及中間層305的外部部分上的第一模制構件MB1。
第三模制構件MB3可包含導電材料。舉例來說,第三模制構件MB3可包含金屬(例如,銅(Cu)、鋁(Al)、鈦(Ti)、鉭(Ta)、鎢(W)、鎳(Ni)及其組合)、含有金屬的金屬膏或含有金屬的金屬帶。第三模制構件MB3可用於使下部半導體晶片200中產生的熱量消散。
第四模制構件MB4可包含絕緣材料。也就是說,第四模制構件MB4可防止第三模制構件MB3與中間層305之間的短路。
此外,在半導體封裝50中,模制構件可包括具有彼此不同的熱膨脹係數的至少三個部分。在一些實施例中,半導體封裝50可包括具有彼此不同的熱膨脹係數的第一模制構件MB1、第三模制構件MB3及第四模制構件MB4。也就是說,慮及第一模制構件MB1、第三模制構件MB3及第四模制構件MB4的熱膨脹係數,可有效地控制向半導體封裝50施加的拉伸應力及壓縮應力以使翹曲最小化。
參照圖6A到圖6C,圖6A是半導體封裝60的剖視圖,圖6B是半導體封裝60的平面圖,且圖6C是中間層306的透視圖。為便於解釋,在圖6B中省略了模制構件MB及上部半導體晶片400。
如圖6A到圖6C一起所示,半導體封裝60可包括封裝基板100、下部半導體晶片200、通過形成在中間層306的側表面上的凹槽306G而劃分成多個區的中間層306以及上部半導體晶片400。也就是說,中間層306的所述多個區可部分地連接到彼此,同時通過凹槽306G僅部分地隔開。
詳細來說,半導體封裝60可包括中間層306,中間層306通過形成在中間層306的側表面上的凹槽306G而被劃分成多個區。凹槽306G的數目可為2N(N是自然數),且凹槽306G可排列成在平面圖中彼此面對。另外,凹槽306G的一端可與中間層306的邊緣交會。舉例來說,如圖6C所示,凹槽306G中的每一者可例如沿Z方向延伸穿過中間層306的整個厚度。舉例來說,如圖6C中進一步示出,凹槽306G中的每一者可例如沿Y方向僅部分地延伸,因此一個凹槽306G的例如沿Y方向的長度可小於兩個面對的凹槽306G的例如沿Y方向之間的距離。如圖6B所示,下部半導體晶片200的上表面的與凹槽306G重疊的部分可從中間層306開口,例如,下部半導體晶片200可通過凹槽306G暴露出。
在半導體封裝60中,中間層306可在側表面上包括凹槽306G,且凹槽306G可填充有模制構件MB。中間層306的熱膨脹係數可不同於模制構件MB的熱膨脹係數。
此外,在中間層306上可形成有第二再分佈層329以實現用於與上部半導體晶片400進行信號傳輸的各種佈線設計。第二再分佈層329的數目及第二再分佈層329的排列形式是例示性地示出的且並非僅限於此。
參照圖7A到圖7C,圖7A是半導體封裝70的剖視圖,圖7B是半導體封裝70的平面圖,且圖7C是中間層307的透視圖。為便於解釋,在圖7B中省略了模制構件MB及上部半導體晶片400。
如圖7A到圖7C所示,半導體封裝70可包括封裝基板100、下部半導體晶片200、通過形成在中間層307的上表面上的凹槽307G而劃分成多個區的中間層307以及上部半導體晶片400。也就是說,凹槽307G可沿Z方向僅部分地延伸到中間層307中。
詳細來說,半導體封裝70可包括中間層307,中間層307通過形成在中間層307的上表面上的凹槽307G而被劃分成所述多個區。凹槽307G可平行於中間層307的邊緣延伸,且凹槽307G的深度可大於中間層307的例如沿Z方向的厚度的一半。另外,凹槽307G的兩端可與中間層307的邊緣間隔開。
舉例來說,凹槽307G可為線性的,且沿凹槽307G的整個長度(例如沿Y方向)為連續的(圖7C)。在另一實例中,凹槽307G可包括多個凹槽,且凹槽307G中的至少兩個凹槽307G可被形成為彼此交叉。也就是說,可形成所述多個凹槽307G,每一凹槽307G在第一方向(X方向)及第二方向(Y方向)上延伸。
在半導體封裝70中,中間層307在上表面上可包括凹槽307G,且凹槽307G可填充有模制構件MB。中間層307的熱膨脹係數可不同於模制構件MB的熱膨脹係數。
模制構件MB可包括第一模制構件及第二模制構件。也就是說,模制構件可包括填充凹槽307G的第二模制構件及形成在下部半導體晶片200及中間層307的外部部分上的第一模制構件,例如,如前面參照圖4A及圖4B所論述。第一模制構件的熱膨脹係數與第二模制構件的熱膨脹係數可彼此不同。
參照圖8A到圖8C,圖8A是半導體封裝80的剖視圖,圖8B是半導體封裝80的平面圖,且圖8C是中間層308的透視圖。為便於解釋,在圖8B中省略了模制構件MB及上部半導體晶片400。
如圖8A到圖8C所示,半導體封裝80可包括封裝基板100、下部半導體晶片200、通過形成在中間層308的上表面上的凹槽308G而劃分成多個區的中間層308以及上部半導體晶片400。也就是說,凹槽308G可沿Z方向僅部分地延伸到中間層308中。
詳細來說,半導體封裝80可包括中間層308,中間層308通過形成在中間層308的上表面上的凹槽308G而被劃分成所述多個區。凹槽308G可平行於中間層308的邊緣延伸,且凹槽308G的深度可大於中間層308的例如沿Z方向的厚度的一半。另外,凹槽308G的一端可與中間層308的邊緣交會,例如,凹槽308G沿Y方向的長度可等於中間層308沿Y方向的長度。
舉例來說,凹槽308G可為線性的且例如沿Y方向連續。在另一實例中,凹槽308G可包括多個凹槽,且凹槽308G中的至少兩個凹槽308G可被形成為彼此交叉。也就是說,可形成所述多個凹槽308G,每一凹槽308G在第一方向(X方向)及第二方向(Y方向)上延伸。
在半導體封裝80中,中間層308在上表面上可包括凹槽308G,且凹槽308G可填充有模制構件MB。中間層308的熱膨脹係數可不同於模制構件MB的熱膨脹係數。
模制構件MB可包括填充凹槽308G的第二模制構件及形成在下部半導體晶片200及中間層308的外部部分上的第一模制構件。第一模制構件的熱膨脹係數與第二模制構件的熱膨脹係數可彼此不同。
參照圖9A到圖9B,圖9A是半導體封裝90的剖視圖,且圖9B是半導體封裝90的平面圖。為便於解釋,在圖9B中省略了模制構件MB及上部半導體晶片400。
如圖9A及圖9B所示,半導體封裝90可包括封裝基板100、下部半導體晶片200、包括多個片段的中間層300及上部半導體晶片400。此外,半導體封裝90可包括下部半導體晶片209,下部半導體晶片209通過第三接合線BW3電連接到封裝基板100。
在半導體封裝90中,第二黏合構件DAF2可黏附到下部半導體晶片209及封裝基板100。第二黏合構件DAF2可與第一黏合構件DAF1實質上相同。也就是說,第二黏合構件DAF2可包括裸片貼附膜。
在半導體封裝90中,第一接合構件DAF1的厚度可被形成為大於或等於用於使第三接合線BW3成環的厚度以防止第三接合線BW3的機械變形。也就是說,第一接合構件DAF1的上表面的水平高度可高於第三接合線BW3的最上表面的水平高度。
圖10是示出根據實施例的示例性實施例的製造半導體封裝的方法的流程圖。
參照圖10,製造半導體封裝的方法S10可包括:第一步驟S110,製備封裝基板;第二步驟S120,在封裝基板上安裝下部半導體晶片;第三步驟S130,將包括多個片段的中間層貼附在下部半導體晶片上;第四步驟S140,形成用於將封裝基板連接到中間層的接合線以及接著形成模制構件;第五步驟S150,將上部半導體晶片安裝到中間層;以及第六步驟S160,在封裝基板的下部部分上形成外部連接端子。
半導體封裝的製造方法S10可包括上述示例性製程步驟S110到S160。如果一些實施例可以其他方式實施,則可與上述製程步驟的順序不同地實行特定的製程步驟。舉例來說,相繼闡述的兩個製程可實質上同時實行,或者可以與上述順序相反的順序實行。
將參照圖11A到圖11E詳細闡述第一步驟S110到第六步驟S160的技術特徵。圖11A到圖11E是根據示例性實施例的製造半導體封裝的方法中的各個階段的剖視圖。
參照圖11A,可製備封裝基板100。封裝基板100可包括主體部分110作為支撐基板。封裝基板100可為PCB。佈線140可形成在封裝基板100上,且佈線140可電連接到封裝基板100的上表面上的上電極焊盤120及封裝基板100的下表面上的下電極焊盤130。
參照圖11B,可在封裝基板100上安裝下部半導體晶片200。
構成下部半導體晶片200的半導體基板210可具有主動表面及非主動表面。半導體基板210的主動表面可被設置成面對封裝基板100的上表面。可在半導體基板210的主動表面上形成晶片焊盤220。
晶片焊盤220可通過連接端子230直接連接到設置在封裝基板100的上表面上的上電極焊盤120。可使用晶片焊盤220及上電極焊盤120作為用於下部半導體晶片200與封裝基板100之間的信號傳輸的端子。
參照圖11C,可在下部半導體晶片200上貼附包括多個片段的中間層300。可使用黏合構件DAF將中間層300貼附到下部半導體晶片200的上表面。舉例來說,中間層300的每一片段(即,部分)可通過單獨的黏合構件DAF被貼附到下部半導體晶片200的不同部分以使得中間層300的所述多個片段可在下部半導體晶片200上彼此間隔開預定距離以在下部半導體晶片200上界定行及列。
在平面圖中,中間層300的一部分可與下部半導體晶片200重疊,例如,中間層300的多個片段中的每一片段可與下部半導體晶片200的一部分重疊。另外,中間層300的最外邊緣可沿水平方向突出超過下部半導體晶片200的邊緣,例如,中間層300的多個片段中的至少一些片段可延伸超過下部半導體晶片200的邊緣以懸在下部半導體晶片200的邊緣上。
參照圖11D,在形成用於對封裝基板100與中間層300進行連接的接合線BW之後,可將模制構件MB形成為覆蓋下部半導體晶片200、中間層300及接合線BW。模制構件MB的一部分可例如完全填充中間層300的所述多個片段中的相鄰的片段之間的空間。
詳細來說,接合線BW可將封裝基板100電連接到中間層300。在形成接合線BW之後,可將適當量的模制材料注入到封裝基板100上,且可通過模制材料的固化製程形成模制構件MB。
可實行微影製程及蝕刻製程以形成開口MBH,開口MBH用於使中間層300的再分佈層結構320的上表面焊盤開口。微影製程及蝕刻製程可根據任何方便的製程來實行。
參照圖11E,可在中間層300上安裝上部半導體晶片400。上部半導體晶片400可包括半導體基板堆疊410及形成在半導體基板堆疊410的最下表面上的晶片焊盤420。
晶片焊盤420可通過連接端子430直接連接到設置在中間層300的上表面中的再分佈層結構320。可使用晶片焊盤420及再分佈層結構320作為用於上部半導體晶片400與中間層300之間的信號傳輸的端子。
再次參照圖1A,可通過在封裝基板100的下部部分上形成外部連接端子150來完成根據實施例的半導體封裝10。
圖12是示出根據示例性實施例的包括半導體封裝的半導體模組的示意圖。
參照圖12,半導體模組1000可包括模組基板1010、安裝在模組基板1010上的控制晶片1020以及安裝在模組基板1010上的多個半導體封裝1030。在模組基板1010的一側上可設置有可插入到主機板的插座(socket)中的多個輸入/輸出端子1050。所述多個半導體封裝1030可包括參照圖1A到圖9B闡述的根據實施例的半導體封裝10到半導體封裝90中的任何一者。
圖13是示出根據示例性實施例的半導體封裝的系統的示意圖。
參照圖13,系統1100可包括控制器1110、輸入/輸出裝置1120、記憶體1130、介面1140及匯流排1150。
系統1100可為移動系統或發送或接收資訊的系統。在一些實施例中,移動系統可包括例如可攜式電腦、網路平板電腦、行動電話、數位音樂播放機或存儲卡。
控制器1110可用於控制系統1100中的執行程式,且可包括例如微處理器、數位訊號處理器、微控制器等。
可使用輸入/輸出裝置1120來輸入或輸出系統1100的資料。系統1100可使用輸入/輸出裝置1120連接到外部裝置(例如個人電腦或網路),且可與外部裝置相互交換資料。輸入/輸出裝置1120可包括例如觸摸墊、鍵盤或顯示器。
記憶體1130可存儲用於控制器1110的操作的資料,或者可存儲由控制器1110處理的資料。記憶體1130可包括參照圖1A到圖9B闡述的根據實施例的半導體封裝10到半導體封裝90中的任何一者。
介面1140可為系統1100與外部裝置之間的資料傳輸路徑。控制器1110、輸入/輸出裝置1120、記憶體1130及介面1140可通過匯流排1150彼此通信。
通過總結及回顧,實施例提供一種半導體封裝,在所述半導體封裝中通過使用中間層,有利於在半導體封裝的有限結構中有效地排列半導體晶片的同時進行翹曲控制。也就是說,根據實施例,半導體封裝包括具有多個片段的中間層及填充所述多個片段之間的空間的模制構件以減輕翹曲。
在本文中已揭露了示例性實施例,且儘管採用了特定用語,然而使用這些用語僅是為了從一般性及說明性的意義加以解釋而非用於限制目的。在一些情況中,在提出本申請時對所屬領域中的一般技術人員而言將顯而易見,除非另外具體地指明,否則結合具體實施例闡述的特徵、特性及/或元件可單獨使用或與結合其他實施例闡述的特徵、特性及/或元件組合使用。因此,所屬領域中的技術人員應理解,在不背離申請專利範圍中所述本發明的精神及範圍的條件下可作出形式及細節上的各種改變。
10、20、30、40、50、60、70、80、90:半導體封裝
100:封裝基板
110:主體部分
120:上電極焊盤
130:下電極焊盤
140:佈線
150:外部連接端子
200、209:下部半導體晶片
210:半導體基板
220:晶片焊盤
230:連接端子
300、302、303、304、305、306、307、308:中間層
300a:片段/部分
306G、307G、308G:凹槽
310:基礎基板
320:再分佈層結構
321:元件/上表面焊盤
323、329:組件/再分佈層
325、327:組件/接合焊盤
400:上部半導體晶片
400R:端子區
410:半導體基板堆疊
420:晶片焊盤
430:連接端子
1000:半導體模組
1010:模組基板
1020:控制晶片
1030:半導體封裝
1050:輸入/輸出端子
1100:系統
1110:控制器
1120:輸入/輸出裝置
1130:記憶體
1140:介面
1150:匯流排
BW、BW1、BW2、BW3:接合線
DAF、DAF1、DAF2:黏合構件
DX、DY:距離
MB、MB1、MB2、MB3、MB4:模制構件
MBH:開口
S10:方法
S110、S120、S130、S140、S150、S160:步驟
UF:底部填充件
X、Y、Z:方向
通過參照所附圖式詳細闡述示例性實施例,對於所屬領域中的技術人員來說,特徵將變得顯而易見,在所附圖式中:
圖1A到圖1D示出根據示例性實施例的半導體封裝的圖。
圖2A到圖9B示出根據示例性實施例的半導體封裝的圖。
圖10示出根據示例性實施例的製造半導體封裝的方法的流程圖。
圖11A到圖11E示出根據示例性實施例的製造半導體封裝的方法中的各個階段的剖視圖。
圖12示出根據示例性實施例的包括半導體封裝的半導體模組的示意圖。
圖13示出根據示例性實施例的半導體封裝的系統的示意圖。
10:半導體封裝
100:封裝基板
110:主體部分
120:上電極焊盤
130:下電極焊盤
140:佈線
150:外部連接端子
200:下部半導體晶片
210:半導體基板
220:晶片焊盤
230:連接端子
300:中間層
310:基礎基板
320:再分佈層結構
321:元件/上表面焊盤
325:組件/接合焊盤
400:上部半導體晶片
410:半導體基板堆疊
420:晶片焊盤
430:連接端子
BW:接合線
DAF:黏合構件
MB:模制構件
UF:底部填充件
X、Y、Z:方向
Claims (25)
- 一種半導體封裝,包括:封裝基板;下部半導體晶片,位於所述封裝基板上;中間層,位於所述下部半導體晶片上,所述中間層包括彼此間隔開的多個片段;上部半導體晶片,位於所述中間層上;以及模制構件,覆蓋所述下部半導體晶片及所述中間層。
- 如申請專利範圍第1項所述的半導體封裝,其中所述中間層包括2N個片段,在平面圖中,所述2N個片段以兩側對稱結構排列,其中N是正整數。
- 如申請專利範圍第1項所述的半導體封裝,其中所述下部半導體晶片的上表面的一部分不與所述中間層重疊。
- 如申請專利範圍第1項所述的半導體封裝,其中,在平面圖中,所述中間層的最外邊緣延伸超過所述下部半導體晶片的邊緣。
- 如申請專利範圍第1項所述的半導體封裝,其中所述下部半導體晶片及所述中間層中的每一者包括矽晶圓作為基板。
- 如申請專利範圍第1項所述的半導體封裝,其中所述模制構件填充所述中間層的所述多個片段中的相鄰的片段之間的空間,所述模制構件的熱膨脹係數大於所述中間層的熱膨脹係數。
- 如申請專利範圍第6項所述的半導體封裝,其中所述封裝基板的熱膨脹係數大於所述中間層的所述熱膨脹係數。
- 如申請專利範圍第1項所述的半導體封裝,其中:所述中間層的上表面的一部分包括被所述模制構件暴露出的焊盤區,所述中間層與所述上部半導體晶片通過所述焊盤區中的連接構件連接到彼此,且所述上部半導體晶片與所述模制構件間隔開。
- 如申請專利範圍第8項所述的半導體封裝,其中:所述上部半導體晶片中的其中排列有所述連接構件的端子區的數目等於所述中間層的所述多個片段的數目,且所述端子區中的每一個端子區與所述中間層的所述多個片段中的對應的一個片段重疊。
- 如申請專利範圍第1項所述的半導體封裝,其中所述下部半導體晶片包括單個邏輯晶片,且所述上部半導體晶片包括由多個存儲晶片形成的堆疊。
- 如申請專利範圍第1項所述的半導體封裝,其中所述模制構件包括:第一模制構件,填充所述中間層的所述多個片段之間的空間;以及 第二模制構件,覆蓋所述下部半導體晶片、所述中間層及所述第一模制構件,其中所述第一模制構件的熱膨脹係數大於所述第二模制構件的熱膨脹係數。
- 如申請專利範圍第11項所述的半導體封裝,其中所述第一模制構件包括金屬材料,且絕緣膜設置在所述中間層與所述第一模制構件之間。
- 如申請專利範圍第1項所述的半導體封裝,還包括:第一接合線,將所述封裝基板連接到所述中間層;以及第二接合線,將所述中間層的所述片段連接到彼此。
- 如申請專利範圍第1項所述的半導體封裝,其中所述下部半導體晶片以倒裝晶片方式位於所述封裝基板上,且接合線將所述下部半導體晶片連接到所述封裝基板。
- 如申請專利範圍第1項所述的半導體封裝,其中所述中間層使用黏合構件貼合到所述下部半導體晶片。
- 一種半導體封裝,包括:封裝基板;下部半導體晶片,位於所述封裝基板上;中間層,位於所述下部半導體晶片上,所述中間層包括多個區,所述多個區通過所述中間層的上表面中的凹槽而彼此隔開;上部半導體晶片,位於所述中間層上;接合線,將所述封裝基板連接到所述中間層;以及 模制構件,覆蓋所述下部半導體晶片、所述中間層及所述接合線,其中所述模制構件的熱膨脹係數大於所述中間層的熱膨脹係數。
- 如申請專利範圍第16項所述的半導體封裝,其中,在平面圖中,所述中間層的邊緣延伸超過所述下部半導體晶片的邊緣。
- 如申請專利範圍第16項所述的半導體封裝,其中所述模制構件包括:第一模制構件,填充所述凹槽;以及第二模制構件,覆蓋所述下部半導體晶片、所述中間層、所述第一模制構件及所述接合線,其中所述第一模制構件的熱膨脹係數大於所述第二模制構件的熱膨脹係數。
- 如申請專利範圍第16項所述的半導體封裝,其中所述凹槽的端部與所述中間層的邊緣間隔開。
- 如申請專利範圍第16項所述的半導體封裝,其中所述凹槽的端部與所述中間層的邊緣交會。
- 一種半導體封裝,包括:封裝基板;下部半導體晶片,位於所述封裝基板上;中間層,位於所述下部半導體晶片上,所述中間層包括多個區,所述多個區通過從所述中間層的側表面延伸的凹槽而彼此隔開; 上部半導體晶片,位於所述中間層上;接合線,將所述封裝基板連接到所述中間層;以及模制構件,覆蓋所述下部半導體晶片、所述中間層及所述接合線,所述模制構件的熱膨脹係數大於所述中間層的熱膨脹係數。
- 如申請專利範圍第21項所述的半導體封裝,其中所述凹槽包括2N個片段,在平面圖中,所述2N個片段彼此面對地排列,其中N是正整數。
- 如申請專利範圍第21項所述的半導體封裝,其中與所述凹槽重疊的所述下部半導體晶片的上表面的一部分被所述中間層暴露出。
- 如申請專利範圍第21項所述的半導體封裝,其中所述凹槽的端部與所述中間層的邊緣交會。
- 如申請專利範圍第21項所述的半導體封裝,其中,在平面圖中,所述中間層的邊緣延伸超過所述下部半導體晶片的邊緣。
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CN113345846B (zh) * | 2021-06-03 | 2022-03-22 | 长鑫存储技术有限公司 | 封装结构及用于制造封装结构的方法 |
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CN111834355A (zh) | 2020-10-27 |
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