TWI548053B - 具有嵌入式表面配裝裝置的半導體封裝與其形成方法 - Google Patents

具有嵌入式表面配裝裝置的半導體封裝與其形成方法 Download PDF

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TWI548053B
TWI548053B TW103145300A TW103145300A TWI548053B TW I548053 B TWI548053 B TW I548053B TW 103145300 A TW103145300 A TW 103145300A TW 103145300 A TW103145300 A TW 103145300A TW I548053 B TWI548053 B TW I548053B
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package
interconnect structure
fitting device
die
surface fitting
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TW103145300A
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TW201532234A (zh
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陳憲偉
陳英儒
邱銘彥
葉德強
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台灣積體電路製造股份有限公司
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Description

具有嵌入式表面配裝裝置的半導體封 裝與其形成方法
本發明是有關於一種半導體封裝，且特別是有關於一種配裝有表面配裝裝置的半導體封裝與其形成方法。
半導體裝置被使用在各種電子應用中，例如為個人電腦、手機、數位相機與其他電子設備。一般來說，半導體裝置是透過以下方式來形成，依序地在半導體基板上沉積絕緣層或介電層、導電層與半導體層等材料，並且使用微影技術來圖案化這些材料層以形成電路組件與元件。
由於各種電子組件(例如電晶體、二極體、電阻、電容等)的積體密度的改良，半導體工業已經經歷了快速的成長。在大多數的情況下，此積體密度的改良是來自於縮小半導體製程節點(例如縮小製程節點至子20奈米(sub-20nm)節點)。隨著近來對於微小化、高速高頻寬、 以及低功耗和低延遲的需求已成長，對於更小更創新的半導體晶粒封裝技術的需求也在成長。
本發明的實施例提出了半導體封裝與其形成方法。
本發明的實施例提出一種半導體封裝，包括了包含有一或多個晶粒的第一封裝，以及透過第一組連接件接合至第一封裝第一側的封裝基板。此半導體封裝還包括配裝在第一封裝第一側的表面配裝裝置，此表面配裝裝置實質上是由一或多個被動元件所組成。
本發明的實施例提出一種半導體封裝，包括：第一封裝，包括具有第一側與第二側的第一晶粒，其中第二側是相對於第一側；互連結構，位於第一晶粒的第一側上，其中互連結構包括N個金屬層與M個鈍化層；表面配裝裝置，配裝於互連結構的第一部份中N個金屬層的其中之一，其中第一部分具有少於M個鈍化層；以及一組凸塊下金屬(under bump metallizations，UBMs)，耦接至第一封裝的互連結構的第N個金屬層，其中第N個金屬層是最遠離第一晶粒第一側的金屬層。半導體封裝還包括耦接至凸塊下金屬的第一組導電連接件，以及接合至第一組導電連接件的封裝基板。
本發明的實施例提出一種形成方法，包括形成第一封裝，此程序包括形成互連結構於第一晶粒的第一側 上，挖鑿互連結構的一部分，以及將表面配裝裝置配裝於互連結構中被挖鑿的部分。此方法還包括利用第一組導電連接件將第一封裝的互連結構接合至封裝基板。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
102‧‧‧基板
104‧‧‧接合墊
200‧‧‧第一封裝
202A、202B‧‧‧晶粒
204、205‧‧‧接合墊
206‧‧‧電性連接件
208‧‧‧膜塑料
210‧‧‧接觸區域
212‧‧‧互連結構
220‧‧‧凸塊下金屬
230‧‧‧導電連接件
250‧‧‧表面配裝裝置
260‧‧‧導電連接件
270‧‧‧金屬線
300‧‧‧第二封裝
302‧‧‧基板
304、306‧‧‧接合墊
308‧‧‧導電連接件
310‧‧‧堆疊晶粒
312‧‧‧引線接合
314‧‧‧膜塑料
400‧‧‧半導體封裝
P1~PN+1‧‧‧鈍化層
M1~MX‧‧‧金屬層
D1、D2、D3、D4‧‧‧距離
500‧‧‧第一封裝
600‧‧‧半導體封裝
280‧‧‧金屬線
700‧‧‧第一封裝
800‧‧‧半導體封裝
290‧‧‧密封材料
當結合附圖閱讀時，根據下面詳細的描述可以更好地理解本揭露的態樣。應該強調的是，根據工業中的標準作法，各種特徵並沒有按比例繪示。實際上，為了清楚的討論，各種特徵可以被任意增大或縮小。
圖1是根據一些實施例繪示了半導體封裝的示意圖。
圖2是根據一些實施例繪示了半導體封裝的示意圖。
圖3是根據一些實施例繪示了半導體封裝的示意圖。
以下的揭露提供了許多不同的實施例或是例子，用以實作本發明的不同的特徵。為了簡化本揭露，組件與佈置的具體例子會在以下說明。當然，這些僅是例子，並不用以限制本揭露。例如，若在後續說明中提到了第一特徵形成在第二特徵上面，這可包括第一特徵與第二特徵是直接接觸的實施例；這也可以包括第一特徵與第二特徵之間還形成其他特徵的實施例，這使得第一特徵與第二特徵沒有直接接觸。此外，本揭露可能會在各種例子中 重複圖示符號及/或文字。此重複是為了簡明與清晰的目的，但本身並不決定所討論的各種實施例及/或設置之間的關係。
再者，在空間上相對的用語，例如底下、下面、較低、上面、較高等，是用來容易地解釋在圖示中一個元件或特徵與另一個元件或特徵之間的關係。這些空間上相對的用語除了涵蓋在圖示中所繪的方向，也涵蓋了裝置在使用或操作上不同的方向。這些裝置也可被旋轉(例如旋轉90度或旋轉至其他方向)，而在此所使用的空間上相對的描述同樣也可以有相對應的解釋。
以下會針對具體的內容來解釋實施例，也就是製造與使用包括了表面配裝裝置的半導體封裝。然而，其他的實施例也可以應用在其他電性連接的組件上，其包括但不限定於推疊式封裝的組裝、推疊式晶粒的組裝、堆疊式晶圓的組裝、晶粒至基板的組裝、封裝組裝、製程基板、中介層、基板等，或者是配裝輸入組件、電路板、晶粒或其他組件，或者用以連接封裝或配裝任一類型的積體電路或電子組件的組合。
圖1是根據一些實施例繪示了半導體封裝400的示意圖。半導體封裝400包括了基板102、在基板102上的第一封裝200、以及在第一封裝200上的第二封裝300。
基板102可由半導體材料所製成，例如為矽、鍺、鑽石等。或者，也可以使用化合材料，例如為矽化鍺，碳化矽，砷化鎵，砷化銦，磷化銦，矽鍺碳、鎵砷 磷、鎵銦磷、或其組合等。此外，基板102可以為矽上絕緣體(silicon-on-insulator，SOI)基板。一般來說，SOI基板包括一層半導體材料，例如為磊晶矽、鍺、矽化鍺、SOI、矽鍺上絕緣體(silicon germanium on insulator，SGOI)或其組合。在另一實施例中，基板102是基於絕緣芯，例如玻璃纖維增強的樹脂芯。一個範例的芯材料為玻璃纖維樹脂，例如為FR4。其他的芯材料包括雙馬來醯亞胺-三嗪(bismaleimide-triazine，BT)樹脂，或者是其他的印刷電路板材料或膜。基板102也可使用增強膜，例如為Ajinomoto公司的增強膜(Ajinomoto build-up film，ABF)或其他層板。基板102可被稱為封裝基板102。
基板102可包括主動元件與被動被動元件(未繪示於圖1中)。本領域具有通常知識者可理解例如為電晶體、電容、電阻、或其組合等的各種裝置可被用來產生半導體封裝400設計的結構性與功能性需求。這些裝置可用任意適合的方法來形成。
基板102也可包括金屬化層(未繪示)。金屬化層可形成在主動元件與被動元件上，並且被設計來連接各種裝置以形成功能性電路。金屬化層可藉由交替介電材料(例如低K的介電材料)與導電材料(例如為銅)來形成，其中有通孔來連接導電材料層，並且可透過任意適合的製程(例如沉積、鑲嵌(damascene)、雙鑲嵌等)來形成。在一些實施例中，基板102實質上並沒有主動元件與被動元件。
基板102包括了接合墊104。接合墊104可形成於基板102的第一側。在一些實施例中，接合墊104是透過在基板102或基板102上的鈍化層(未繪示)中形成凹陷(未繪示)來形成。這些凹陷可被形成以讓接合墊104可鑲嵌在基板102或鈍化層之中。在其他實施例中，這些凹陷可被省略，接合墊104可形成於基板102的第一側上。接合墊104是電性地及/或實體地將依序接合的第一封裝200及/或第二封裝300耦接至基板102的主動元件與被動元件(若有的話)以及/或基板102第二側上的連接件(未繪示)。在一些實施例中，接合墊104包括了沉積在基板102上的薄晶種層(未繪示)，例如透過物理氣相沉積(physical vapor deposition，PVD)、化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)等或其組合來沉積。上述的晶種層可由銅、鈦、鎳、金等或其組合來製成。接合墊104的導電材料可沉積在薄晶種層上。此導電材料可透過電化學電鍍製程、CVD、ALD、PVD等或其組合來形成。在一實施例中，接合墊104的導電材料為銅、鎢、鋁、銀、金等或其組合。
在一實施例中，接合墊包括三層導電材料，例如為一層鈦、一層銅與一層鎳。然而，本領域具有通常知識者可理解的是，對於接合墊104的形成有許多材料與層的合適配置，例如為鉻/鉻銅合金/銅/金的配置、鈦/鎢鈦/銅的配置、或銅/鎳/金的配置。接合墊104可以使用任意適 合的材料或是材料層，這些都充分地包含在本申請的範圍中。
第一封裝200包括了密封在膜塑料208中的一或多個晶粒202(202A與202B)。晶粒202在第一側是耦接至一組接合墊205並且在第二側具有一組接觸區域210，其中第二側是相對於第一側。一組電性連接件206是從接合墊204延伸通過膜塑料208，而膜塑料208是相鄰於晶粒202。電性連接件206從晶粒202的第一側延伸至晶粒202的第二側。互連結構212是形成於晶粒202的第二側與電性連接件206之上。互連結構212包括交替的鈍化層(P1、PN與PN+1)和金屬化層(M1與MX)，其中這些金屬化層是透過延伸通過鈍化層的通孔來連接。表面配裝裝置250是直接地耦接至金屬化層MX。
在一實施例中，第一封裝200是透過在載體基板(未繪示)上形成接合墊204與205來形成。形成接合墊204、205的材料與製程和上述的接合墊104類似，在此並不再贅述，但接合墊204、205與接合墊104不需要相同。
電性連接件206可為柱狀凸塊(stud bump)，其可透過以下方式來形成，將引線接合至接合墊204並且切斷接合引線，留下一部份的接合引線來連接至對應的接合球上。例如，在圖1中，電性連接件206包括較低部分與較高部分，其中較低部分可為引線接合中形成的接合球，並且較高部分可為剩下的接合線。電性連接件206的較高部分從較高部分的上、中、下部位都具有均勻的寬度與均 勻的形狀。電性連接件206是由引線接合器可接合的非焊金屬材料所形成。在一些實施例中，電性連接件206是由銅線、金線等或其組合所製造，並且可具有包括多層的複合結構。
在其他的實施例中，電性連接件206是透過電鍍所形成。在這些實施例中，電性連接件206是由銅、鋁、鎳、金、銀、鈀等或其組合所製造，並且可具有包括多層的複合結構。在這些實施例中，犧牲層(未繪示)會形成於載體基板之上。多個開口會形成於犧牲層中以暴露出底下的接合墊204。接下來執行電鍍步驟以電鍍出電性連接件206。在形成電性連接件206以後，接下來會移除犧牲層。
在形成接合墊205以後，晶粒202的第一側可耦接至接合墊205。晶粒202(202A與202B)可為單一個晶粒或者是多於兩個的晶粒。晶粒202可包括邏輯晶粒，例如為中央處理器(central processing unit，CPU)、圖形處理單元(graphics processing unit，GPU)等或其組合。在一些實施例中，晶粒202包括了同時具有邏輯晶粒與記憶體晶粒的晶粒堆疊(未繪示)。晶粒202可包括輸入輸出(input/output，I/O)晶粒，例如為寬I/O晶粒，其提供了在第一封裝200與依序連接的第二封裝300之間的連接。
在晶粒202第二側上的接觸區域210可相似於上述的接合墊104，在此便不再贅述，但接觸區域210與接合墊104並不需要相同。
接下來，可密封晶粒202與電性連接件206。在一些實施例中，晶粒202與電性連接件206是由膜塑料208所密封。膜塑料208可例如使用模壓成型而被膜塑在晶粒202與電性連接件206之上。在一些實施例中，膜塑料208是由模塑化合物、聚合物、環氧樹脂、矽氧化物填料等或其組合所製造。可實施一個固化步驟來固化膜塑料208，此固化可為熱固化、紫外線(Ultra-Violet，UV)固化等。
在一些實施例中，晶粒202、接觸區域210與電性連接件206是被埋在膜塑料208當中，並且在固化膜塑料208以後會實施例如為研磨(grinding)的平坦化步驟來移除膜塑料208中多餘的部分，其中多餘的部分會超過接觸區域210與電性連接件206的上表面。在一些實施例中，接觸區域210的表面與電性連接件206的表面會被暴露出來，並且會齊平於膜塑料208的表面。電性連接件206可被稱為膜塑通孔(through molding vias，TMVs)並且以下會被稱為TMVs 206。
互連結構212可形成於晶粒202的接觸區域210與TMVs 206之上並與之電性耦接。互連結構包括了多個鈍化層，也就是P1、PN、與PN+1，其中鈍化層P1為緊鄰於接觸區域210和TMVs 206的鈍化層，並且鈍化層PN+1(有時被稱為上鈍化層PN+1)為緊鄰於凸塊下金屬(under bump metallizations，UBMs)220的鈍化層。互連結構212還包括多個金屬層，也就是M1與MX，其中金屬 層M1是緊鄰於鈍化層P1的金屬層，並且金屬層MX(有時被稱為上金屬層MX)是緊鄰於UBMs 220的金屬層。在本揭露中，術語"金屬層"指的是同一層中金屬線的統稱。
鈍化層(P1、PN與PN+1)可以是氮化矽、碳化矽、氧化矽、例如為摻碳氧化物的低k介電質、例如為多孔摻碳氧化矽的極低k介電質、例如為環氧樹脂、聚酰亞胺、苯並環丁烯(BCB)、聚苯並噁唑(PBO)等或其組合的聚合物，但也可以使用其他相對軟，通常為有機的介電材料，並且可透過CVD、PVD、ALD、旋塗介電製程等或其組合來沉積。在一實施例中，每一個鈍化層(P1、PN與PN+1)是被形成以具有約2微米至約15微米的厚度。
金屬層M1、MX可使用單及/或雙鑲嵌製程、通孔優先製程或金屬優先製程來形成。金屬層(M1與MX)與通孔可由導電材料來製造，例如為銅、鋁、鈦等或其組合，並且可有阻隔層或是沒有阻隔層。在一實施例中，金屬層M1至MX中的每一者都具有範圍從約1微米至12微米的厚度。
鑲嵌製程是用以形成嵌入至另一層的圖案化層，使得這兩層的上表面為共平面。只產生溝槽或通孔的鑲嵌製程被稱為單鑲嵌製程。同時產生溝槽與通孔的鑲嵌製程被稱為雙鑲嵌製程。
在一範例實施例中，金屬層M1至MX是使用雙鑲嵌製程來形成。在此例子中，M1層的形成可從在鈍化層P1上形成蝕刻停止層(未繪示)並在蝕刻停止層上形成鈍化 層PN開始。一旦沉積了鈍化層PN，部分的鈍化層PN會被蝕刻以形成凹陷特徵，例如為溝槽與通孔，其中可填滿導電材料以連接互連結構212的不同區域並且容納金屬線與通孔。上述的製成可重複實施在其餘的金屬層(直到MX)上。
金屬層M1~MX的數目以及鈍化層P1~PN+1的數目只是用以作為說明性目的，並不用以限制本揭露。也可以有其他數目的層，這些層是多於或少於所繪示的兩個金屬層。也可以有不同於圖1所繪示的，其他數目的鈍化層和鈍化層。
UBMs 220可形成在金屬層MX之上並與之電性耦接。一組開口(未繪示)可形成在鈍化層PN+1以暴露出金屬層MX中金屬線的表面。UBMs 220可延伸通過鈍化層PN+1的開口，並且也沿著鈍化層PN+1的表面延伸。UBMs 220可包括三層導電材料，例如為一層鈦、一層銅與一層鎳。然而，本領域具有通常知識者可理解的是，對於UBMs 220的形成有許多材料與層的合適配置，例如為鉻/鉻銅合金/銅/金的配置、鈦/鎢鈦/銅的配置、或銅/鎳/金的配置。UBMs 220可以使用任意適合的材料或是材料層，這些都充分地包含在本申請的範圍中。
表面配裝裝置250是透過導電連接件260直接地配裝在上金屬層MX的一或多個金屬線270。上鈍化層PN+1中覆蓋金屬線270的部分可透過適當的製程來移除，例如為蝕刻製程、雷射等或其組合。在移除部分的上鈍化層PN+1後所形成的凹陷具有距離D1的深度。在一實施例 中，此距離D1是約10微米至約30微米。
在一實施例中，表面配裝裝置250具有兩個接觸點，其是透過導電連接件260與金屬線270電性耦接至互連結構212。在一些實施例中，導電連接件260是被形成以具有從表面配裝裝置250表面垂直地量測至導電連接件260表面的高度，此高度是約10微米至約30微米。
表面配裝裝置250可包括一或多個被動元件，例如為電容、電阻、電感等或其組合。在一實施例中，表面配裝裝置250實質上是由一或多個被動元件所組成，並且不包括例如為電晶體的主動元件。如圖1所示，表面配裝裝置250可包括兩個導電連接件260，其是由導電材料所形成，例如為焊錫等或其組合。在一些實施例中，表面配裝裝置250具有約0.4釐米至約1.5釐米的長度，約0.1釐米至約0.8釐米的寬度，以及約0.1釐米至約0.2釐米的厚度。
導電連接件260可由應用在金屬線270的金屬焊膏(metal-paste)印刷製程所形成。根據金屬線270的位置，可用膜板(stencil)來印刷金屬線270上的金屬焊膏。回流製程會被應用在半導體封裝，使得金屬焊膏會凝聚在互連結構212的金屬線270上的導電連接件260中。
或者，導電連接件260也可以透過以下步驟來形成，在互連結構212上沉積光阻(未繪示)，圖案化此光阻以在互連結構212的金屬線270上形成多個開口，以例如為焊錫等適合的材料來填滿這些開口，回流焊錫材料，並且移除光阻以暴露出導電連接件260。
在一些實施例中，導電連接件260是形成在表面配裝裝置250之上，而不是形成在互連結構212之上。
在形成導電連接件260以後，表面配裝裝置250可例如透過拾取與放置工具而被放置在互連結構212的凹陷中。在一實施例中，表面配裝裝置250是透過回流製程而接合至互連結構212。在回流製程中，互連結構212的金屬線270會接觸導電連接件260，藉此實體地或電性地將表面配裝裝置250耦合至互連結構212。
隨著將表面配裝裝置250配裝在金屬線270上，表面配裝裝置250上最靠近鈍化層PN的表面與鈍化層PN相隔了距離D2，在一實施例中此距離D2是約10微米至30微米。金屬線270和導電連接件260的側壁與上鈍化層PN+1的側壁相隔了距離D3，在一實施例中此距離D3是大於10微米。
將表面配裝裝置250配裝於金屬線270以後，第一封裝200是透過導電連接件230、UBMs 220與接合墊104接合至基板102。在第一封裝200接合至基板102之前，第一封裝200可被單片化(若必要的話)且載體基板(未繪示)可被移除。
導電連接件230可以是焊錫球、金屬柱、可控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、無電鎳鈀浸金(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊等。導電連接件230可 包括導電材料，例如為焊錫、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在導電連接件230為焊錫凸塊的實施例中，導電連接件230是透過以下方式來形成，一開始先透過一般使用的方法形成一層焊錫，此方法例如為揮發、電鍍、印刷、焊錫轉移法、錫球置入法(ball placement)等。一旦焊錫層形成在結構上以後，可實施回流來將這些材料塑造成所需的凸塊形狀。在其他的實施例中，導電連接件230為金屬柱(例如為銅柱)，其是透過濺射、印刷、電鍍、化學鍍法、CVD等所形成。這些金屬柱可不具有焊錫並且具有實質上為垂直的側壁。在一些實施例中，金屬蓋層(未繪示)可被形成在金屬柱連接件230上。此金屬蓋層可包括鎳、錫、錫鉛合金、金、銀、鈀、銦、鎳鈀金合金、鎳金合金等或其組合所形成，並且可透過電鍍製程來形成。
在第一封裝200與基板102之間的接合可為焊錫接合或直接金屬對金屬(例如為銅對銅或錫對錫)接合。在一實施例中，第一封裝200是透過回流製程而接合至基板102。在回流製程中，導電連接件230接觸了接合墊104與UBMs 220，藉此實體地或電性地將第一封裝200耦接至基板102。
第二封裝300可在第一封裝200接合至基板102的之後或之前被形成且接合至第一封裝200。第二封裝300包括了基板302與一或多個耦接至基板302的堆疊晶粒310。
基板302可包括在基板302第一側上的接合墊304，耦接至堆疊晶粒310與基板302第二側上的接合墊306，其中基板302第二側是相對於第一側，藉此耦接至導電連接件308。基板302可相似於上述的基板102，在此便不再贅述，但基板302與基板102並不需要相同。在一些實施例中基板302可包括形成在上面的電子組件與元件，或者基板302可不包括電子組件與元件。
在所繪示的實施例中，堆疊晶粒310是透過引線接合312耦接至基板302，但也可以使用其他連接，例如為導電凸塊。在一實施例中，堆疊晶粒310為堆疊記憶體晶粒。例如，上述的堆疊記憶體晶粒310可包括低功耗(low-power，LP)雙資料率(double data rate，DDR)記憶體模組，例如為LPDDR1、LPDDR2、LPDDR3或相似的記憶體模組。堆疊記憶體晶粒310可透過引線接合312、接合墊304、306與導電連接件308耦接至第一封裝200。
在一些實施例中，堆疊晶粒310與引線接合312可被膜塑料314所密封。膜塑料314可例如使用模壓成型而被膜塑在堆疊晶粒310與引線接合312之上。在一些實施例中，膜塑料314是由模塑化合物、聚合物、環氧樹脂、矽氧化物填料等或其組合所製造。可實施一個固化步驟來固化膜塑料314，此固化可為熱固化、紫外線固化等。
在一些實施例中，堆疊晶粒310與引線接合312被埋在膜塑料314中，並且在固化膜塑料314以後可實施例如為研磨的平坦化步驟來移除膜塑料314的多餘部分 並且提供第二封裝300實質上為平坦的表面。
在形成第二封裝300以後，第二封裝300會透過導電連接件308與接合墊306、204被接合至第一封裝200。
導電連接件308可相似於上述的導電連接件230，在此便不再贅述，但導電連接件308與導電連接件230並不需要相同。
在第二封裝300與第一封裝200之間的接合可為焊錫接合或直接金屬對金屬(例如為銅對銅或錫對錫)接合。在一實施例中，第二封裝300是透過回焊製程接合至第一封裝200。在回流製程中，導電連接件308接觸了接合墊306、204，藉此實體地或電性地將第二封裝300耦接至第一封裝200。
底部填充材料(未繪示)可被注入或形成在第一封裝200與第二封裝300之間的空間，且圍繞導電連接件308。此外，底部填充材料(未繪示)可被注入或形成在第一封裝200與基板102之間的空間，且圍繞表面配裝裝置250和導電連接件230。此底部填充材料可例如為液體環氧樹脂，可變形凝膠，矽橡膠或類似物，其是分散在結構之間並且之後可被固化變硬。位於其他東西之間的底部填充材料是用來保護表面配裝裝置250與導電連接件230、308並減少面配裝裝置250與導電連接件230、308的傷害。
應注意的是，圖1中半導體晶粒(例如為半導體晶粒202)、表面配裝裝置(例如為表面配裝裝置250)與導電 連接件(例如為導電連接件230、308)的數目都僅是範例。本揭露可以有許多變型，修改和替換。例如，本領域具有通常知識者可理解半導體封裝400可容納任意數目的半導體晶粒、表面配裝裝置與導電連接件。
相較於把表面配裝裝置配裝在封裝基板上相鄰於封裝的位置或半導體封裝上的其他位置，透過將表面配裝裝置嵌入在封裝與封裝基板之間，可降低半導體封裝的形狀因子(form factor)。此外，當不需要長的金屬導體，例如為將互連及/或晶粒耦接至表面配裝裝置的重分佈線或互連，表面配裝裝置的訊號整合也會改善。
圖2是根據一些實施例繪示了半導體封裝600的示意圖。除了半導體封裝600包括了第一封裝500，其中表面配裝裝置250是直接配裝在第一金屬層M1中的金屬線，半導體封裝600是相似於上述的半導體封裝400。在此並不重覆本實施例中相似於上述實施例的細節。
在此實施例中，表面配裝裝置250是透過導電連接件260直接地配裝在第一金屬層M1的一或多個金屬線280。在鈍化層中覆蓋金屬線280的部分，除了P1以外(例如為PN與PN+1)都可透過適當的製程來移除，例如為蝕刻製程、雷射等或其組合。在移除鈍化層中覆蓋金屬線280但除了P1以外的部分(例如為PN與PN+1)以後所形成的凹陷具有距離D4的深度。在一實施例中，此距離D4是約15微米至約40微米。
表面配裝裝置250可例如透過拾取與放置工具 而被放置在互連結構212上。在一實施例中，表面配裝裝置250是透過回焊製程而接合至互連結構212。在回流製程中，互連結構212的金屬線280會接觸導電連接件260，藉此實體地或電性地將表面配裝裝置250耦接至互連結構212。
值得注意的是，在互連結構212中具有兩層以上金屬層的例子中，表面配裝裝置250可直接地配裝在M1與MX之間的任何一層金屬層。
透過移除鈍化層中除了第一鈍化層以外的所有其他層並且將表面配裝裝置配裝在第一金屬層上，可擴大表面配裝裝置的製程適用範圍(process window)。這可允許在封裝與封裝基板之間裝進更大的表面配裝裝置。
圖3是根據一些實施例繪示了半導體封裝800的示意圖。除了半導體封裝800包括了第一封裝700，其中表面配裝裝置250是被密封材料290所密封，半導體封裝800是相似於上述的半導體封裝600。在此並不重覆本實施例中相似於上述實施例的細節。
在此實施例中，表面配裝裝置250是透過密封材料290所密封。此密封材料290可以例如透過膜壓成型而膜塑在表面配裝裝置250之上。在一些實施例中，密封材料290是由模塑化合物、聚合物、環氧樹脂、矽氧化物填料等或其組合所製造。可實施一個固化步驟來固化膜塑料314，此固化可為熱固化、紫外線固化等。在一些實施例中，密封材料290延伸通過上鈍化層PN+1的表面。在其他 實施例中，密封材料290具有一表面，實質上地與上鈍化層PN+1的表面共平面。
透過以密封材料來密封表面配裝裝置，可保護表面配裝裝置免於濕氣，並且密封材料可提供熱與物理壓力的減免。此密封可提升具有表面配裝裝置的半導體封裝的良率。
某一實施例為半導體封裝，包括了包含有一或多個晶粒的第一封裝，以及透過第一組連接件接合至第一封裝第一側的封裝基板。此半導體封裝還包括配裝在第一封裝第一側的表面配裝裝置，此表面配裝裝置實質上是由一或多個被動元件所組成。
另一個實施例為半導體封裝，包括：第一封裝，包括具有第一側與第二側的第一晶粒，其中第二側是相對於第一側；互連結構，位於第一晶粒的第一側上，其中互連結構包括N個金屬層與M個鈍化層；表面配裝裝置，配裝於互連結構的第一部份中N個金屬層的其中之一，其中第一部分具有少於M個鈍化層；以及一組凸塊下金屬(under bump metallizations，UBMs)，耦接至第一封裝的互連結構的第N個金屬層，其中第N個金屬層是最遠離第一晶粒第一側的金屬層。半導體封裝還包括耦接至凸塊下金屬的第一組導電連接件，以及接合至第一組導電連接件的封裝基板。
另一個實施例為一方法，包括形成第一封裝，此程序包括形成互連結構於第一晶粒的第一側上，挖鑿互連結構的一部分，以及將表面配裝裝置配裝於互連結構中被挖 鑿的部分。此方法還包括利用第一組導電連接件將第一封裝的互連結構接合至封裝基板。
以上蓋述了多個實施例的特徵，使得本領域通常知識者可更佳地理解本揭露的各種態樣。本領域通常知識者應可理解的是他們可輕易地使用本揭露作為基礎來設計或修改其他的製程或結構，藉此實踐出與這些實施例相同的目的及/或達到相同優點。本領域通常知識者也應可理解的是，這些等效的結構並不脫離本揭露的精神與範圍，並且他們可以做各種改變、置換與變更，而不脫離本揭露的精神與範圍。
102‧‧‧基板
104‧‧‧接合墊
200‧‧‧第一封裝
202A、202B‧‧‧晶粒
204、205‧‧‧接合墊
206‧‧‧電性連接件
208‧‧‧膜塑料
210‧‧‧接觸區域
212‧‧‧互連結構
220‧‧‧凸塊下金屬
230‧‧‧導電連接件
250‧‧‧表面配裝裝置
260‧‧‧導電連接件
270‧‧‧金屬線
300‧‧‧第二封裝
302‧‧‧基板
304、306‧‧‧接合墊
308‧‧‧導電連接件
310‧‧‧堆疊晶粒
312‧‧‧引線接合
314‧‧‧膜塑料
400‧‧‧半導體封裝
P1~PN+1‧‧‧鈍化層
M1~MX‧‧‧金屬層
D1、D2、D3‧‧‧距離

Claims (10)

  1. 一種半導體封裝，包括：一第一封裝，包括一或多個晶粒；一封裝基板，透過第一組連接件接合至該第一封裝的一第一側；一表面配裝裝置，配裝在該第一封裝的該第一側，其中該表面配裝裝置實質上是由一或多個被動元件所組成；以及一第二封裝，透過第二組導電連接件接合至該第一封裝的一第二側，其中該第二側是相對於該第一側，該第二封裝包括一或多個晶粒。
  2. 如申請專利範圍第1項所述之半導體封裝，其中該第一封裝更包括在該第一封裝的該第一側上的一互連結構，其中該表面配裝裝置是配裝在該互連結構的一凹陷中，並且該凹陷具有實質為10微米至實質為30微米的深度，該半導體封裝更包括一密封材料，位於在該凹陷中且圍繞該表面配裝裝置的一部分。
  3. 如申請專利範圍第1項所述之半導體封裝，其中該表面配裝裝置具有兩個導電連接件，並且該表面配裝裝置的該一或多個被動元件是從電容、電阻、電感或其組合所組成的組合中所選出。
  4. 如申請專利範圍第1項所述之半導體封裝，其中該第一封裝更包括：一電性連接件，從該第一封裝的該第二側延伸至該第一封裝的該第一側，其中該電性連接件是被隔開於該第一封裝的該一或多個晶粒；以及一膜塑料，圍繞該第一封裝的該一或多個晶粒以及該第一封裝的該電性連接件。
  5. 一種半導體封裝，包括：一第一封裝，包括：一第一晶粒，具有一第一側與一第二側，該第二側是相對於該第一側；一互連結構，位於該第一晶粒的該第一側上，其中該互連結構包括N個金屬層與M個鈍化層；一表面配裝裝置，配裝於該互連結構的一第一部份中該些N個金屬層的其中之一，其中該第一部分具有少於M個鈍化層；以及一組凸塊下金屬(under bump metallizations，UBMs)，耦接至該第一封裝的該互連結構的第N個金屬層，其中該第N個金屬層是最遠離該第一晶粒的該第一側的金屬層；第一組導電連接件，耦接至該組凸塊下金 屬；以及一封裝基板，接合至該第一組導電連接件。
  6. 如申請專利範圍第5項所述之半導體封裝，其中該表面配裝裝置是配裝在該互連結構的該第N個金屬層，並且該互連結構的該第一部分具有M-1個鈍化層。
  7. 如申請專利範圍第5項所述之半導體封裝，其中該表面配裝裝置是配裝在該互連結構中的第一個金屬層，該第一個金屬層是最接近該第一晶粒的該第一側的金屬層，並且該互連結構的該第一部分具有一個鈍化層。
  8. 如申請專利範圍第5項所述之半導體封裝，其中該表面配裝裝置的一側壁是相隔於第M個鈍化層的一壁側至少10微米，並且該表面配裝裝置實質上是由一或多個被動元件所組成，該半導體封裝還包括：一第二封裝，包括一第二晶粒，其中該第二封裝是透過第二組連接件接合至該第一晶粒的該第二側。
  9. 一半導體封裝的形成方法，包括：形成一第一封裝，包括： 形成一互連結構於一第一晶粒的一第一側上；挖鑿該互連結構的一部分，其中挖鑿該互連結構的該部分的程序更包括從該互連結構的該部分移除至少一鈍化層與至少一金屬層；以及將一表面配裝裝置配裝於該互連結構中被挖鑿的該部分；以及利用第一組導電連接件將該第一封裝的該互連結構接合至一封裝基板。
  10. 如申請專利範圍第9項所述的形成方法，更包括：將該表面配裝裝置密封於該互連結構上被挖鑿的該部分中。
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