TW201913899A - 積體電路封裝及其製作方法 - Google Patents

積體電路封裝及其製作方法 Download PDF

Info

Publication number
TW201913899A
TW201913899A TW106135546A TW106135546A TW201913899A TW 201913899 A TW201913899 A TW 201913899A TW 106135546 A TW106135546 A TW 106135546A TW 106135546 A TW106135546 A TW 106135546A TW 201913899 A TW201913899 A TW 201913899A
Authority
TW
Taiwan
Prior art keywords
layer
integrated circuit
alignment mark
conductive
insulating
Prior art date
Application number
TW106135546A
Other languages
English (en)
Inventor
楊慶榮
邱銘彥
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201913899A publication Critical patent/TW201913899A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一種積體電路封裝包括晶粒、多個導通孔、對位標記及絕緣包封材。所述晶粒包括多個導電接墊。所述導通孔分別接觸所述導電接墊。所述對位標記設置在所述晶粒上且與所述導通孔間隔開。所述絕緣包封材包封所述晶粒且接觸所述導通孔的側表面及所述對位標記的側表面。

Description

積體電路封裝及其製作方法
本發明是有關於一種積體電路封裝及其製作方法。
半導體裝置被用於例如個人電腦、手機、數碼相機及其他電子裝備等各種各樣的電子應用中。半導體裝置通常是透過以下方式來製作：在半導體基板之上依序沉積絕緣層或介電層、導電層以及半導體材料層；以及利用微影（lithography）對所述各種材料層進行圖案化以在上面形成電路元件及元件。許多積體電路通常是在單個半導體晶圓上製造。可對晶圓的晶粒進行晶圓級加工及封裝，且已開發出用於晶圓級封裝的各種技術。
在本發明的一實施例中，一種積體電路封裝包括半導體晶粒、多個導通孔、對位標記以及絕緣包封材。半導體晶粒包括主動表面及設置在所述主動表面上的多個導電接墊。導通孔分別接觸所述多個導電接墊。對位標記設置在所述半導體晶粒上且與所述多個導通孔間隔開。絕緣包封材包封所述半導體晶粒且接觸所述多個導通孔的側表面及所述對位標記的側表面。
在本發明的一實施例中，一種積體電路封裝包括半導體晶粒、多個導通孔、對位標記、絕緣包封材以及重佈層。半導體晶粒包括設置在所述半導體晶粒的主動表面上的多個導電接墊及覆蓋所述主動表面的保護層，其中所述保護層包括與所述多個導電接墊對應的多個第一開口。導通孔設置在所述多個第一開口中且經由所述多個第一開口接觸所述多個導電接墊。對位標記設置在所述保護層上且透過所述保護層與所述主動表面隔開，其中所述對位標記與所述多個第一開口之間保持有距離。絕緣包封材包封所述半導體晶粒的側表面且接觸所述保護層，其中所述對位標記透過所述絕緣包封材與所述多個導通孔隔開。重佈層設置在所述絕緣包封材及所述半導體晶粒上。
在本發明的一實施例中，一種製作積體電路封裝的方法包括下列步驟。提供積體電路元件，所述積體電路元件能夠移除地接合到載體，其中所述積體電路元件包括半導體晶粒、多個導通孔及對位標記，所述多個導通孔分別接觸所述半導體晶粒的多個導電接墊且與所述對位標記間隔開；在所述載體之上形成絕緣包封材以包封所述積體電路元件，其中所述絕緣包封材填充在所述多個導通孔與所述對位標記之間，且接觸所述多個導通孔的側表面及所述對位標記的側表面；以及研磨所述絕緣包封材，直到顯露出所述多個導通孔的頂表面及所述多個對位標記的頂表面，其中所述絕緣包封材的被研磨表面與所述導通孔的所述頂表面及所述對位標記的所述頂表面共平面。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實作所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本發明實施例。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下（beneath）」、「下面（below）」、「下部的（lower）」、「上方（above）”、「上部的（upper）」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向（旋轉90度或處於其他取向）且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外，為易於說明，本文中可能使用例如“第一（first）”、“第二（second）”、“第三（third）”、“第四（fourth）”等用語來闡述與圖中所示者相似或不同的一個或多個元件或特徵，且可根據呈現次序或本說明的上下文來可互換地使用所述用語。
圖1至圖11說明根據一些實施例的製作整合扇出型（integrated fan-out，InFO）封裝的製作流程。在一些實施例中，積體電路封裝100是整合扇出型（InFO）封裝。所述製作積體電路封裝100的方法可包括以下步驟。參照圖1，提供包括呈陣列排列的多個半導體晶粒110的晶圓110a。在對晶圓110a執行晶圓切割製程（wafer dicing process）之前，晶圓110a的多個半導體晶粒110是彼此連接的。在一些實施例中，晶圓110a包括半導體基板111、多個導電接墊112及保護層116。導電接墊112形成在半導體基板111的主動表面114上。保護層116形成在晶圓110a上。在一些實施例中，保護層116形成在主動表面114上且包括分別與導電接墊112對應的多個第一開口116a。在一個實施例中，第一開口116a位於導電接墊112上且保護層116局部地覆蓋導電接墊112。換句話說，保護層116的第一開口116a局部地暴露出導電接墊112。舉例來說，晶圓110a的半導體基板111可為矽基板，所述矽基板包括形成在所述矽基板中的主動元件（例如，電晶體等）及/或被動元件（例如，電阻器、電容器、電感器等）。導電接墊112可為鋁墊、銅墊或其他適合的金屬墊。保護層116可為氧化矽層、氮化矽層、氮氧化矽層或由其他適合的介電材料所形成的介電層。在一個實施例中，保護層116是單層的保護層116且可直接接觸主動表面114。在這樣的配置下，可省略半導體晶粒110上的多層的保護層，以減少積體電路封裝的生產成本。
參照圖2，在保護層116上形成圖案化光阻層PR。圖案化光阻層PR包括多個第一圖案開口OP1及第二圖案開口OP2。第一圖案開口OP1顯露出保護層116的第一開口116a及位於第一開口116a之下的導電接墊112。第二圖案開口OP2顯露出保護層116。接著，在第一圖案開口OP1中形成多個導通孔120且在第二圖案開口OP2中形成對位標記130。因此，導通孔120可分別直接接觸導電接墊112，且對位標記130可直接接觸保護層116。在一些實施例中，對位標記130與導通孔120間隔開。因此，對位標記130與導通孔120之間存在間隙G1。換句話說，對位標記130與第一開口116a保持有一距離。另外，對位標記130與導電接墊112之間存在另一間隙。在一些實施例中，導通孔120可局部地覆蓋保護層116，且對位標記130透過保護層116而與主動表面114隔開。
在一些實施例中，透過電鍍（plating）製程在導電接墊112上形成導通孔120。舉例來說，在形成圖案化光阻層PR之前，可首先將種晶層濺鍍（sputter）在保護層116及被保護層116暴露出的導電接墊112上。接著，透過微影（photolithography）在種晶層之上形成包括第一圖案開口OP1及第二圖案開口OP2的圖案化光阻層PR。接著將上面形成有圖案化光阻層PR的晶圓110a浸沒到電鍍液中，從而使得導通孔120及對位標記130電鍍形成於種晶層上，且導通孔120及對位標記130在位置上與第一圖案開口OP1及第二圖案開口OP2對應。
參照圖3，在形成導通孔120及對位標記130之後，移除圖案化光阻層PR。此後，使用導通孔120及對位標記130作為硬罩幕，例如透過刻蝕（etching）製程移除種晶層中不被導通孔120及對位標記130所覆蓋的部分，直到顯露出保護層116。在一些實施例中，導通孔120為銅通孔或其他金屬通孔。
圖13是說明根據一些實施例的積體電路元件的示意圖。參照圖3及圖13，在一些實施例中，透過相同的製程（例如，電鍍製程）來製作導通孔120與對位標記130。在此種實施例中，導通孔120的材料與對位標記130的材料相同。在一些實施例中，對位標記130可為三角形對位標記130a、矩形對位標記130b、L形對位標記130c、十字形對位標記130d或具有其他適合形狀的對位標記。換句話說，對位標記130的俯視圖可呈三角形、矩形、十字形、L形或其他適合形狀。根據本發明，對位標記130的形狀及數目並非僅限於此。在一些實施例中，積體電路元件115可包括一個以上的對位標記130，且對位標記130的形狀可彼此相同，對位標記130的形狀也可彼此不同。
接著，參照圖2與圖3，在形成導通孔120及對位標記130之後，可對半導體基板111的後表面上執行背側研磨製程（back side grinding process）。研磨半導體基板111，以形成薄化晶圓，且所述薄化晶圓包括薄化半導體基板111’、導電接墊112、保護層116、導通孔120及對位標記130。
接著，在執行背側研磨製程之後，執行晶圓切割製程以如圖3中所示將薄化晶圓切割成多個積體電路元件115。各個積體電路元件115包括半導體晶粒110’、導通孔120及對位標記130，其中導通孔120分別接觸半導體晶粒110’的導電接墊112且與對位標記130間隔開。半導體晶粒110’所包括的半導體基板111’及保護層116’的材料及性質與圖1所示的半導體基板111及保護層116的材料及性質相似。因此，為簡潔起見，本文中不再對半導體基板111’及保護層116’予以贅述。
參照圖4，提供上面形成有剝離層12及絕緣層170的載體10，其中剝離層12設置在載體10與絕緣層170之間。在一些實施例中，舉例來說，載體10可為玻璃基板，剝離層12可為形成在玻璃基板上的光熱轉換（light to heat conversion，LTHC）釋放層，且絕緣層170可為形成在剝離層12上的聚苯並惡唑（polybenzoxazole，PBO）層。應注意，在一些實施例中，可省略絕緣層170。換句話說，在一些替代性實施例中，形成絕緣層170的步驟是選擇性的（optional）。還可注意的是，根據本發明實施例，載體10、剝離層12及絕緣層170的材料並不僅限於本文中所公開的材料。
在提供上面形成有剝離層12的載體10之後，在載體10上形成多個導電柱160。在一些實施例中，透過微影、電鍍及光阻剝除製程（photoresist stripping process）而形成導電柱160於載體10之上（例如，在絕緣層170上或者如果絕緣層170被省略則在剝離層12上）。在一些替代性實施例中，可透過其他製程預先製作導電柱160，並將導電柱160安裝在載體10之上。舉例來說，導電柱160包括銅柱（copper post）或其他適合的金屬柱。
接著，在一些實施例中，可拾取如圖3所示的包括導通孔120及對位標記130的積體電路元件115中的一個並將其放置在載體10上。所述積體電路元件115可透過晶粒貼合膜（die attach film）172、黏著膠（adhesion paste）等貼合或黏合在載體10上。在一些替代性實施例中，可將一個以上的積體電路元件115拾取並放置在載體10上，且可將能夠移除地接合到載體10的積體電路元件115以陣列的方式排列。當放置在載體10上的積體電路元件115以陣列的方式排列時，可將導電柱160劃分成與積體電路元件115的數目對應的多個群組。為清晰及簡潔起見，在本發明實施例中繪示一個積體電路元件115，但積體電路元件115的數目並非僅限於此。
在一些實施例中，積體電路元件115的厚度可小於導電柱160的高度。然而，本發明實施例並非僅限於此。在一些替代性實施例中，積體電路元件115的厚度可大於或約等於導電柱160的高度。
如圖4中所示，可在形成導電柱160之後將積體電路元件115中的一個或多個拾取並放置在載體10上。然而，本發明實施例並非僅限於此。在一些替代性實施例中，可在形成導電柱160之前將積體電路元件115中的一個或多個拾取及放置在載體10上。
參照圖5，在載體10之上（例如，在絕緣層170上或者如果絕緣層170被省略則在剝離層12上）形成絕緣包封材140a，以包封包括半導體晶粒110’的積體電路元件115。絕緣包封材140a包封且接觸導通孔120的側表面及對位標記130的側表面。絕緣包封材140a填充導通孔120與對位標記130之間的間隙及導電接墊112與對位標記130之間的間隙。另外，絕緣包封材140a填充各導通孔120之間的間隙及各導電柱160之間的間隙。在一些實施例中，絕緣包封材140a為單層的絕緣包封材，其可包含透過模塑製程（molding process）形成的封裝膠體。絕緣包封材140a的材料可包括環氧樹脂（epoxy）或其他適合的樹脂。舉例來說，絕緣包封材140a可為含有化學填料的環氧樹脂。
參照圖5及圖6，在一些實施例中，對絕緣包封材140a及導電柱160進行研磨，直到顯露出導通孔120的頂表面及對位標記130的頂表面。在研磨絕緣包封材140a之後，形成如圖6中所示的絕緣包封材140。絕緣包封材140的被研磨表面與導通孔120的頂表面及對位標記130的頂表面共平面。在一些實施例中，在絕緣包封材140a的研磨製程期間，更可對導電柱160的頂部部分、導通孔120的頂部部分及對位標記130的頂部部分進行研磨。在此種實施例中，絕緣包封材140的被研磨表面與導電柱160的被研磨頂表面、導通孔120的被研磨頂表面及對位標記130的被研磨頂表面共平面。舉例來說，可透過機械研磨（mechanical grinding）或化學機械拋光（chemical mechanical polishing，CMP）來研磨絕緣包封材140。
絕緣包封材140填充在導通孔120與對位標記130之間且接觸導通孔120的側表面及對位標記130的側表面。換句話說，積體電路元件115及導電柱160大部分內嵌在絕緣包封材140中，僅積體電路元件115的頂表面及導電柱160的頂表面被顯露出。絕緣包封材140的材料及性質與如圖5中所示的絕緣包封材140a的材料及性質相似。因此，為簡潔起見，本文中不再對絕緣包封材140予以贅述。
在一些實施例中，透過研磨製程可在導通孔120的頂表面上產生多個研磨痕跡（圖中未示出），且所述研磨痕跡分佈在導通孔120的頂表面上。此外，上述研磨痕跡不僅會在導通孔120的頂表面上找到，而且會在對位標記130的頂表面、導電柱160的頂表面及絕緣包封材140被研磨表面上找到。在一些實施例中，對位標記130的粗糙的被研磨表面是可在紅外光（infrared，IR）對準製程中被識別的及可行的，原因是IR對準製程對於對位標記130的被研磨表面的粗糙度較不敏感。
參照圖7，在形成絕緣包封材140並對絕緣包封材140進行研磨之後，在絕緣包封材140及包括半導體晶粒110’的積體電路元件115上形成重佈層150。在一些實施例中，重佈層150的製作製程可包括以下步驟。舉例來說，在絕緣包封材140的被研磨表面上形成重佈線路層152，且接著在絕緣包封材140的被研磨表面以及重佈線路層152上形成介電層154。
在一些實施例中，重佈線路層152連接絕緣包封材140的被研磨表面、導通孔120的頂表面、對位標記130的頂表面及導電柱160的頂表面。重佈線路層152被製作成用於電性連接其下的一個或多個連接件。此處，前述連接件可為導通孔120及/或導電柱160。在一些實施例中，對位標記可如圖7中所示一樣透過重佈線路層152電性連接到導通孔120。在其他實施例中，對位標記130可與導通孔120電性絕緣。換句話說，對位標記130可能接觸或可能不接觸重佈線路層152。重佈線路層152可包括用於安裝導電球的多個球接墊及用於安裝被動元件的至少一個連接接墊。介電層154包括多個第二開口154a，所述多個第二開口154a位於重佈線路層152上以顯露出重佈線路層152的球接墊及連接接墊。在重佈線路層152直接連接導通孔120、對位標記130及導電柱160的配置下，重佈層150的最底部的介電層可被省略，以進一步減少生產成本。
在一些實施例中，重佈層150可進一步包括交替堆疊的多個介電層與多個重佈線路層。在一些實施例中，導通孔120的頂表面、對位標記130的頂表面及導電柱160的頂表面可接觸重佈線路層中最底部的一個。最底部介電層局部地覆蓋導通孔120的頂表面、對位標記130的頂表面及導電柱160的頂表面。
參照圖8，在形成重佈層150之後，在第二開口154a中形成多個導電球180。導電球180經由第二開口154a接觸重佈線路層152。在一些實施例中，導電球180填充第二開口154a。換句話說，導電球180經由第二開口154a直接安裝在重佈線路層152的接墊上。也就是說，在這樣的配置下，用於球安裝（ball mount）的多個球下金屬（under-ball metallurgy，UBM）圖案可被省略，以進一步減少生產成本。在一些實施例中，可透過植球製程（ball placement process）在重佈線路層152的接墊上放置導電球180，且可透過焊接製程（soldering process）在重佈線路層152的連接接墊上安裝至少一個被動元件。
參照圖8及圖9，在形成重佈層150、導電球180及/或被動元件之後，將剝離層12從由載體10所承載的絕緣層170（如果有的話）、絕緣包封材140及積體電路元件115剝離以形成圖9中所示結構。在剝離層12為LTHC釋放層的實施例中，可對剝離層12執行紫外（ultra-violet，UV）雷射照射製程（UV laser irradiation process），以促進剝離層12與載體10的脫離。
參照圖10，在一些實施例中，可進一步將絕緣層170圖案化，以形成包括多個接觸開口172的絕緣層170a。接觸開口172對應於導電柱160以顯露出導電柱160的底表面。接觸開口172的數目可對應於導電柱160的數目。在一些實施例中，可透過雷射鑽孔製程（laser drilling process）、微影製程或其他適合的製程形成絕緣層170中的接觸開口172。
參照圖11，在絕緣層170中形成接觸開口172之後，經由接觸開口172在導電柱160的底表面上形成多個導電球190。另外，可例如對導電球190進行迴焊，以與導電柱160的底表面接合。在形成導電球190之後，具有雙側端子的積體電路元件115的積體電路封裝100（例如整合扇出型（InFO）封裝）即可形成。此時，積體電路封裝100的製作流程可大致上完成。
圖11A說明根據一些實施例的積體電路封裝的剖視圖。參照圖11A，在一些替代性實施例中，載體10可不包括形成在載體10上的絕緣層170。在此種實施例中，在剝離製程期間，將剝離層12從由載體10所承載的絕緣包封材140及積體電路元件115剝離。因此，絕緣包封材140的底表面、積體電路元件115的底表面（包括晶粒貼合膜）及導電柱160的底表面被顯露出。接著，在沒有環繞導電球190的絕緣層170的情況下直接在導電柱160的底表面上形成多個導電球190。另外，可例如對導電球190進行迴焊，以與導電柱160的底表面接合。在形成導電球190之後，具有雙側端子的積體電路元件115的積體電路封裝100’（例如整合扇出型（InFO）封裝）的形成過程即可完成。
圖12是說明根據一些實施例的堆疊封裝（POP）結構的剖視圖。參照圖12，可提供另一封裝體200。在一些實施例中，所提供的封裝體200為例如記憶體裝置等。封裝體200可堆疊在如圖11所示的積體電路封裝100或圖11A所示的積體電路封裝100’之上，且透過導電球190電性連接到圖11所示的積體電路封裝100或圖11A所示的積體電路封裝100’，從而製作出堆疊封裝（POP）結構300。
其他特徵及製程也可被涵蓋。舉例來說，可包括測試結構，以説明對三維（3D）封裝或三維積體電路（3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈層中或在基板上形成的測試接墊，以允許對3D封裝或3DIC進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構也可對最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合包括對已知良好晶粒進行中間驗證的測試方法而使用，以提高良率並降低成本。
根據本發明的一些實施例，一種積體電路封裝包括半導體晶粒、多個導通孔、對位標記及絕緣包封材。半導體晶粒包括主動表面及設置在所述主動表面上的多個導電接墊。導通孔分別接觸導電接墊。對位標記設置在半導體晶粒上且與導通孔間隔開。絕緣包封材包封半導體晶粒且接觸導通孔的側表面及對位標記的側表面。
根據本發明的一些實施例，所述半導體晶粒更包括保護層，所述保護層覆蓋所述主動表面且包括位於所述導電接墊上的多個第一開口。
根據本發明的一些實施例，所述導通孔經由所述多個第一開口電性連接到所述多個導電接墊，且所述保護層被所述多個導通孔局部地覆蓋。
根據本發明的一些實施例，所述對位標記設置在所述保護層上且透過所述保護層與所述主動表面隔開。
根據本發明的一些實施例，所述保護層是單層的保護層。
根據本發明的一些實施例，所述絕緣包封材的頂表面與所述多個導通孔的頂表面及所述對位標記的頂表面共平面。
根據本發明的一些實施例，所述絕緣包封材包括封裝膠體。
根據本發明的一些實施例，所述的積體電路封裝更包括設置在所述絕緣包封材及所述半導體晶粒上的重佈層，且所述重佈層包括：重佈線路層，接觸所述絕緣包封材的頂表面、所述多個導通孔的頂表面及所述對位標記的頂表面；以及介電層，設置在所述絕緣包封材及所述重佈線路層上。
根據本發明的一些實施例，所述積體電路封裝更包括多個導電球，其中所述介電層包括設置在所述重佈線路層上的多個第二開口，且所述多個導電球設置在所述多個第二開口中且經由所述多個第二開口接觸所述重佈線路層。
根據本發明的一些實施例，一種積體電路封裝包括：半導體晶粒，包括設置在所述半導體晶粒的主動表面上的多個導電接墊及覆蓋所述主動表面的保護層，其中所述保護層包括與所述多個導電接墊對應的多個第一開口；多個導通孔，設置在所述多個第一開口中且經由所述多個第一開口接觸所述多個導電接墊；對位標記，設置在所述保護層上且透過所述保護層與所述主動表面隔開，其中所述對位標記與所述多個第一開口之間保持有距離；絕緣包封材，包封所述半導體晶粒的側表面且接觸所述保護層，其中所述對位標記透過所述絕緣包封材與所述多個導通孔隔開；以及重佈層，設置在所述絕緣包封材及所述半導體晶粒上。
根據本發明的一些實施例，所述絕緣包封材接觸所述多個導通孔及所述對位標記並填充在所述多個導通孔與所述對位標記之間。
根據本發明的一些實施例，所述絕緣包封材的頂表面與所述多個導通孔的頂表面及所述對位標記的頂表面共平面。
根據本發明的一些實施例，所述保護層是單層的保護層。
根據本發明的一些實施例，所述重佈層包括：重佈線路層，接觸所述絕緣包封材的頂表面、所述多個導通孔的頂表面及所述對位標記的頂表面；以及介電層，設置在所述絕緣包封材及所述重佈線路層上。
根據本發明的一些實施例，所述的積體電路封裝更包括多個導電球，其中所述介電層包括設置在所述重佈線路層上的多個第二開口，且所述多個導電球分別設置在所述多個第二開口中且經由所述多個第二開口接觸所述重佈線路層。
根據本發明的一些實施例，一種製作積體電路封裝的方法包括：提供積體電路元件，所述積體電路元件能夠移除地接合到載體，其中所述積體電路元件包括半導體晶粒、多個導通孔及對位標記，所述多個導通孔分別接觸所述半導體晶粒的多個導電接墊且與所述對位標記間隔開；在所述載體之上形成絕緣包封材以包封所述積體電路元件，其中所述絕緣包封材填充在所述多個導通孔與所述對位標記之間，且接觸所述多個導通孔的側表面及所述對位標記的側表面；以及研磨所述絕緣包封材，直到顯露出所述多個導通孔的頂表面及所述多個對位標記的頂表面，其中所述絕緣包封材的被研磨表面與所述導通孔的所述頂表面及所述對位標記的所述頂表面共平面。
根據本發明的一些實施例，提供所述積體電路元件的步驟包括：提供包括所述半導體晶粒的晶圓；在所述晶圓上形成保護層，其中所述保護層包括分別對應於所述導電接墊的多個第一開口；在所述保護層上形成圖案化光阻層，其中所述圖案化光阻層包括多個第一圖案開口及第二圖案開口，所述多個第一圖案開口顯露出所述多個第一開口及所述多個導電接墊，且所述第二圖案開口顯露出所述保護層；在所述多個第一圖案開口中形成所述多個導通孔且在所述第二圖案開口中形成所述對位標記；移除所述圖案化光阻層；以及切割所述晶圓以形成所述積體電路元件。
根據本發明的一些實施例，在將所述積體電路元件能夠移除地接合到所述載體之前，在所述載體上形成多個導電柱，且所述絕緣包封材包封所述多個導電柱的多個側表面。
根據本發明的一些實施例，所述的方法更包括：在所述絕緣包封材的所述被研磨表面上形成重佈線路層，其中所述重佈線路層連接所述多個導通孔的所述頂表面與所述對位標記的所述頂表面；以及在所述絕緣包封材的所述被研磨表面上及所述重佈線路層上形成介電層，其中所述介電層包括設置在所述重佈線路層上的多個第二開口。
根據本發明的一些實施例，所述的方法更包括：在所述第二開口中形成多個導電球，其中所述導電球經由所述多個第二開口接觸所述重佈線路層。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10‧‧‧載體
12‧‧‧剝離層
100、100’‧‧‧積體電路封裝
110、110’‧‧‧半導體晶粒
110a‧‧‧晶圓
111、111’‧‧‧半導體基板
112‧‧‧導電接墊
114‧‧‧主動表面
115‧‧‧積體電路元件
116‧‧‧保護層
116’‧‧‧保護層
116a‧‧‧第一開口
120‧‧‧導通孔
130‧‧‧對位標記
130a‧‧‧三角形對位標記
130b‧‧‧矩形對位標記
130c‧‧‧L形對位標記
130d‧‧‧十字形對位標記
140、140a‧‧‧絕緣包封材
150‧‧‧重佈層
152‧‧‧重佈線路層
154‧‧‧介電層
154a‧‧‧第二開口
160‧‧‧導電柱
170、170a‧‧‧絕緣層
172‧‧‧晶粒貼合膜
180、190‧‧‧導電球
200‧‧‧封裝體
300‧‧‧堆疊封裝結構
G1‧‧‧間隙
OP1‧‧‧第一圖案開口
OP2‧‧‧第二圖案開口
PR‧‧‧圖案化光阻層
圖1至圖11說明根據一些實施例的製作積體電路封裝的製作流程。 圖11A說明根據一些實施例的積體電路封裝的剖視圖。 圖12是說明根據一些實施例的堆疊封裝（package-on-package，POP）結構的剖視圖。 圖13是說明根據一些實施例的積體電路元件的示意圖。

Claims (1)

  1. 一種積體電路封裝，包括： 一半導體晶粒，包括一主動表面及設置在所述主動表面上的多個導電接墊； 多個導通孔，分別接觸所述多個導電接墊； 一對位標記，設置在所述半導體晶粒上且與所述多個導通孔間隔開；以及 一絕緣包封材，包封所述半導體晶粒且接觸所述多個導通孔的側表面及所述對位標記的側表面。
TW106135546A 2017-08-29 2017-10-17 積體電路封裝及其製作方法 TW201913899A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/690,196 2017-08-29
US15/690,196 US10636757B2 (en) 2017-08-29 2017-08-29 Integrated circuit component package and method of fabricating the same

Publications (1)

Publication Number Publication Date
TW201913899A true TW201913899A (zh) 2019-04-01

Family

ID=65435612

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106135546A TW201913899A (zh) 2017-08-29 2017-10-17 積體電路封裝及其製作方法

Country Status (3)

Country Link
US (1) US10636757B2 (zh)
CN (1) CN109427700A (zh)
TW (1) TW201913899A (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USD920266S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
USD920265S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
CN111430313A (zh) * 2020-05-11 2020-07-17 上海天马微电子有限公司 半导体封装及其制作方法
TWI753700B (zh) * 2020-12-11 2022-01-21 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (106)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
JP5259211B2 (ja) * 2008-02-14 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
US8024858B2 (en) * 2008-02-14 2011-09-27 Ibiden Co., Ltd. Method of manufacturing printed wiring board with built-in electronic component
WO2009118950A1 (ja) * 2008-03-27 2009-10-01 イビデン株式会社 多層プリント配線板の製造方法
JP2010118631A (ja) * 2008-10-14 2010-05-27 Shinko Electric Ind Co Ltd フリップチップ用基板及びその製造方法
US9576919B2 (en) * 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US8686560B2 (en) * 2010-04-07 2014-04-01 Maxim Integrated Products, Inc. Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
JP5927756B2 (ja) * 2010-12-17 2016-06-01 ソニー株式会社 半導体装置及び半導体装置の製造方法
US9391046B2 (en) * 2011-05-20 2016-07-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming 3D semiconductor package with semiconductor die stacked over semiconductor wafer
JP2012256737A (ja) * 2011-06-09 2012-12-27 Sony Corp 半導体装置及び半導体装置の製造方法
US8829676B2 (en) * 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) * 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9691706B2 (en) * 2012-01-23 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip fan out package and methods of forming the same
US9991190B2 (en) * 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
US9196532B2 (en) * 2012-06-21 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods for forming the same
US9059107B2 (en) * 2012-09-12 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and packaged devices
US8778738B1 (en) * 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9048222B2 (en) * 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9640531B1 (en) * 2014-01-28 2017-05-02 Monolithic 3D Inc. Semiconductor device, structure and methods
US8877554B2 (en) * 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
JP2014187185A (ja) * 2013-03-22 2014-10-02 Renesas Electronics Corp 半導体装置の製造方法
US9559044B2 (en) * 2013-06-25 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Package with solder regions aligned to recesses
US9466581B2 (en) * 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
US9373527B2 (en) * 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
JP6303443B2 (ja) * 2013-11-27 2018-04-04 Tdk株式会社 Ｉｃ内蔵基板の製造方法
US9184143B2 (en) * 2013-12-05 2015-11-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device with bump adjustment and manufacturing method thereof
US20150287697A1 (en) * 2014-04-02 2015-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method
US9935090B2 (en) * 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9484318B2 (en) * 2014-02-17 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9318429B2 (en) * 2014-03-31 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated structure in wafer level package
US20150311132A1 (en) * 2014-04-28 2015-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line structure and method of forming same
US9711379B2 (en) * 2014-04-30 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. 3D stacked-chip package
US9666522B2 (en) * 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
US9824990B2 (en) * 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9449947B2 (en) * 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
US9318442B1 (en) * 2014-09-29 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package with dummy vias
US9899248B2 (en) * 2014-12-03 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US10325853B2 (en) * 2014-12-03 2019-06-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor packages having through package vias
US9502272B2 (en) * 2014-12-29 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Devices and methods of packaging semiconductor devices
SG10201408768XA (en) * 2014-12-29 2016-07-28 Globalfoundries Sg Pte Ltd Device without zero mark layer
US9595482B2 (en) * 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US10115647B2 (en) * 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US9589903B2 (en) * 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US9659805B2 (en) * 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US9666502B2 (en) * 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9484227B1 (en) * 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US10170444B2 (en) * 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US9818711B2 (en) * 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
JP6478853B2 (ja) * 2015-07-14 2019-03-06 新光電気工業株式会社 電子部品装置及びその製造方法
US10134972B2 (en) * 2015-07-23 2018-11-20 Massachusetts Institute Of Technology Qubit and coupler circuit structures and coupling techniques
US9570410B1 (en) * 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US9391028B1 (en) * 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US10141288B2 (en) * 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US9847269B2 (en) * 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9685411B2 (en) * 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US10636773B2 (en) * 2015-09-23 2020-04-28 Mediatek Inc. Semiconductor package structure and method for forming the same
US10068844B2 (en) * 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US10304700B2 (en) * 2015-10-20 2019-05-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9953963B2 (en) * 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US9735131B2 (en) * 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9793245B2 (en) * 2015-11-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10165682B2 (en) * 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
US10062648B2 (en) * 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9899342B2 (en) * 2016-03-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, redistribution circuit structure, and method of fabricating the same
US9859229B2 (en) * 2016-04-28 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9935080B2 (en) * 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US10068853B2 (en) * 2016-05-05 2018-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9922895B2 (en) * 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
US9806059B1 (en) * 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10037961B2 (en) * 2016-05-17 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9870997B2 (en) * 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10157807B2 (en) * 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
US9941216B2 (en) * 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive pattern and integrated fan-out package having the same
US9985006B2 (en) * 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US9653391B1 (en) * 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9859254B1 (en) * 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US10163805B2 (en) * 2016-07-01 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9966360B2 (en) * 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9793230B1 (en) * 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10163800B2 (en) * 2016-07-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy feature in passivation layer
US9825007B1 (en) * 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US10276506B2 (en) * 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10134708B2 (en) * 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
US10672741B2 (en) * 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10658199B2 (en) * 2016-08-23 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10529697B2 (en) * 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9922896B1 (en) * 2016-09-16 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure with copper pillar having reversed profile
US9837359B1 (en) * 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9911672B1 (en) * 2016-09-30 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices
US10515899B2 (en) * 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US10157846B2 (en) * 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US20180138115A1 (en) * 2016-11-11 2018-05-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method for manufacturing the same
US10163813B2 (en) * 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US10103125B2 (en) * 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10269703B2 (en) * 2016-11-29 2019-04-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of forming the same
US10128193B2 (en) * 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10685896B2 (en) * 2017-04-13 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of fabricating the same
US10312112B2 (en) * 2017-06-20 2019-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package having multi-band antenna and method of forming the same
US10163803B1 (en) * 2017-06-20 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out packages and methods of forming the same
US10854570B2 (en) * 2017-07-27 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package and method of fabricating the same
US11107680B2 (en) * 2017-08-31 2021-08-31 Taiwan Semiconductor Manufacturing Co., Ltd. Mask assembly and method for fabricating a chip package
US10748861B2 (en) * 2018-05-16 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof

Also Published As

Publication number Publication date
CN109427700A (zh) 2019-03-05
US10636757B2 (en) 2020-04-28
US20190067226A1 (en) 2019-02-28

Similar Documents

Publication Publication Date Title
US20230378078A1 (en) Package with fan-out structures
US11069656B2 (en) Three-layer package-on-package structure and method forming same
TWI793960B (zh) 封裝結構及其製造方法
US9735131B2 (en) Multi-stack package-on-package structures
US9716080B1 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
US10163807B2 (en) Alignment pattern for package singulation
US11776905B2 (en) Package structure, package-on-package structure and manufacturing method thereof
TW201911496A (zh) 封裝結構
US11764159B2 (en) Package with fan-out structures
TW201725659A (zh) 使用熱與機械強化層的裝置及其製造方法
TW201812888A (zh) 製作半導體元件的方法
US11011501B2 (en) Package structure, package-on-package structure and method of fabricating the same
TWI716852B (zh) 積體扇出型封裝及其製造方法
US11502040B2 (en) Package structure and semiconductor pacakge
TW201742203A (zh) 整合扇出型封裝及其製造方法
US20220319925A1 (en) Integrated circuit component and package structure having the same
TW201917845A (zh) 封裝結構及其製造方法
TW201909366A (zh) 封裝結構、整合扇出型封裝及其製作方法
SG181248A1 (en) Semiconductor packages and methods of packaging semiconductor devices
TW201911524A (zh) 積體電路封裝
TW201838107A (zh) 積體電路封裝
TW201913899A (zh) 積體電路封裝及其製作方法
US10978405B1 (en) Integrated fan-out package
TW201917863A (zh) 半導體裝置封裝
TW201913840A (zh) 用於製造晶片封裝及導線方法