TW201913840A - 用於製造晶片封裝及導線方法 - Google Patents

用於製造晶片封裝及導線方法 Download PDF

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Publication number
TW201913840A
TW201913840A TW107113420A TW107113420A TW201913840A TW 201913840 A TW201913840 A TW 201913840A TW 107113420 A TW107113420 A TW 107113420A TW 107113420 A TW107113420 A TW 107113420A TW 201913840 A TW201913840 A TW 201913840A
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Taiwan
Prior art keywords
alignment
mask
photoresist layer
opening
pattern
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TW107113420A
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English (en)
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TWI682471B (zh
Inventor
陳潔
陳憲偉
劉醇鴻
陳英儒
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台灣積體電路製造股份有限公司
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Publication of TW201913840A publication Critical patent/TW201913840A/zh
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Publication of TWI682471B publication Critical patent/TWI682471B/zh

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    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
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    • G03F7/2002—Exposure; Apparatus therefor with visible light or UV light, through an original having an opaque pattern on a transparent support, e.g. film printing, projection printing; by reflection of visible or UV light from an original such as a printed image
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Abstract

第一罩幕及第二罩幕經依序提供以執行多步驟曝光及顯影製程。經由第一罩幕及第二罩幕的適當重疊設計，可形成具有可接受重疊偏移的導線。

Description

用於製造晶片封裝的罩幕總成及方法
由於各種電子組件（即，電晶體、二極體、電阻器、電容器等）的積體密度的持續改良，半導體行業已經歷快速增長。一般而言，積體密度的改良來自最小特徵大小（feature size）的逐漸減小，此發展允許將更多的較小的組件整合至給定區域中。此等較小的電子組件亦需要使用面積比先前封裝少的較小封裝。半導體組件的一些較小封裝類型包括四邊扁平封裝（quad flat package；QFP）、接腳柵格陣列（pin grid array；PGA）封裝、球柵陣列（ball grid array；BGA）封裝等。
整合式扇出封裝是針對晶片與系統之間的異質整合的有力解決方案。由整合式扇出封裝所提供之經改良的可繞線性（routability）及可靠性是未來封裝的關鍵因素。如何簡化整合式扇出封裝的製程及降低其製造成本是重要問題。
以下揭露內容提供用於實施所提供標的物的不同特徵的許多不同實施例或實例。在下文描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包括第一特徵及第二特徵直接接觸地形成的實施例，且亦可包括額外特徵可在第一特徵與第二特徵之間形成，以使得第一特徵與第二特徵不可直接接觸的實施例。另外，本揭露內容可在各種實例中重複參考數字及/或字母。此重複是出於簡單性及清晰性的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為了易於描述，諸如「在...之下」、「低於」、「下部」、「上方」、「上部」及其類似者的空間相對術語可在本文中使用以描述如諸圖中所說明的一個元件或特徵與另一元件特徵的關係。除了諸圖中所描繪的定向以外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
本發明的實施例亦可包括其他特徵及製程。舉例而言，可包括測試結構以幫助對三維（3D）封裝或三維積體電路（3DIC）裝置的驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試墊，從而允許測試三維封裝或三維積體電路裝置、使用探測器及/或探測卡及其類似處理。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高產率且降低成本。
圖1至圖5根據本揭露內容的一些實施例示意性地說明用於製造積體電路組件的製造流程。請參照圖1，提供包括以陣列排列的多個積體電路組件100的晶圓W。在對晶圓W執行晶圓鋸切（sawing）或切割（dicing）製程之前，晶圓W中的積體電路組件100是彼此實體地連接的，如圖1中所示。在一些實施例中，積體電路組件100中的每一者包括半導體基底110及配置於半導體基底110上的內連線結構120。半導體基底110可為矽基底，其包括形成於其中的主動組件（例如，電晶體或其類似物）及被動組件（例如，電阻器、電容器、電感器或其類似物）。內連線結構120可包括交替堆疊的多個層間介電層122及多個圖案化導電層124。舉例而言，層間介電層122可為氧化矽層、氮化矽層、氮氧化矽層或由其他合適介電材料所形成的介電層，且圖案化導電層124可為圖案化銅層或其他合適的圖案化金屬層。
如圖1中所示，最頂部的圖案化導電層124由層間介電層122中的最頂部的層間介電層122覆蓋，且最頂部的圖案化導電層124由最頂部的層間介電層122的多個開口O1暴露。
請參照圖2，於晶圓W上形成多個導電柱130，導電柱130可經由電鍍製程形成。在一些實施例中，可在晶圓W上濺鍍晶種層（例如，鈦/銅晶種層），且接著於晶種層上形成圖案化光阻。將其上形成有晶種層及圖案化光阻的晶圓W浸於電鍍浴中，以使得導電柱130被電鍍至由圖案化光阻所暴露的部分晶種層上。導電柱130對應於最頂部的層間介電層122的開口O1。在導電柱130被電鍍至暴露的晶種層上之後，移除圖案化光阻。此後，藉由使用導電柱130作為硬式罩幕，移除並且圖案化晶種層，直至最頂部的層間介電層122被暴露為止。在一些實施例中，導電柱130可為銅柱或其他合適的金屬柱。
如圖2中所示，導電柱130可包括柱體部分132及位於柱體部分132與最頂部的圖案化導電層124之間的晶種圖案134。在一些實施例中，導電柱130的柱體部分132的材料及最頂部的圖案化導電層124的材料實質上相同。導電柱130的晶種圖案134與柱體部分132以及最頂部的圖案化導電層124接觸。經由適當選擇晶種圖案134及最頂部的圖案化導電層124的材料，可增強導電柱130（例如，晶種圖案134）與最頂部的圖案化導電層124之間的黏著。銅柱體部分132及鈦/銅晶種圖案134具有良好的電致遷移（electro-migration）抵抗性且具有低電阻率，且最頂部的圖案化導電層124（例如，銅層）與鈦/銅晶種圖案134之間的界面可引發較低的等效串聯電感（equivalent series inductance；ESL）及/或等效串聯電阻（equivalent series resistance；ESR）。
請參照圖3，為了檢測導電柱130及/或積體電路組件100的電特性，可於導電柱130的頂表面上形成多個導電蓋體CAP。在一些實施例中，導電蓋體CAP可為焊料蓋體（solder cap）。舉例而言，上述焊料蓋體可為無鉛焊料蓋體。接著，對導電蓋體CAP執行晶片探測製程（chip probing process），以便檢測導電柱130及/或積體電路組件100的電特性。在晶片探測製程期間，將檢測探測器壓至導電蓋體CAP上，且探測標記（probing marks）可能因此而形成於導電蓋體CAP的頂表面上。然而，由於導電蓋體CAP會被移除，如圖8中所示，故形成於導電蓋體CAP的頂表面上的探測標記不會降低導電柱130及積體電路組件100的可靠性。
請參照圖4，於晶圓W上方形成保護層140，以使得導電蓋體CAP及導電柱130可由保護層140所覆蓋或包覆。導電蓋體CAP及導電柱130可受到保護層140保護。在一些實施例中，保護層140可為聚醯亞胺（PI）層、聚苯并噁唑（PBO）層或其他合適的聚合物或有機層。在保護層140形成之後，可執行晶圓W的背面研磨製程，以使得晶圓W薄化而具有預定厚度。在進行晶圓W的背面研磨製程期間，導電柱130受保護層140a的保護而免受損害。
請參照圖5，沿著切割道SL執行晶圓切割製程或晶圓單體化製程，以使得晶圓W被單體化成多個積體電路組件100a。單體化的積體電路組件100a中的每一者包括半導體基底110a、配置於半導體基底110a上的內連線結構120a、導電柱130以及保護層140a。保護層140a覆蓋內連線結構120a。導電柱130由保護層140a包覆。在晶圓切割或單體化製程期間，導電柱130受保護層140a的保護而免受損害。
圖6至圖13根據本揭露內容的一些實施例示意性地說明用於製造晶片封裝的製造流程。
請參照圖6，提供載體C，而載體C上已形成有剝離層DB及介電層DI，其中剝離層DB位於載體C與介電層DI之間。在一些實施例中，舉例而言，載體C為玻璃基底，剝離層DB為形成於玻璃基底上的光熱轉換（light-to-heat conversion；LTHC）釋放層，且介電層DI為形成於剝離層DB上的聚苯并噁唑（PBO）層。在一些替代性實施例中，剝離層DB可為黏性能夠藉由光固化過程而減小的光可固化離型膜，或為黏性能夠藉由熱固化過程而減小的熱可固化離型膜，且介電層DI可由其他光敏或非光敏介電材料製成。在提供其上形成有剝離層DB及介電層DI的載體C之後，於介電層DI上形成多個導電的絕緣體穿孔TIV。在一些實施例中，導電的絕緣體穿孔TIV藉由光阻塗佈、微影、電鍍以及光阻剝離製程形成。舉例而言，導電的絕緣體穿孔TIV包括銅柱或其他合適的金屬柱。
在一些實施例中，拾取單體化積體電路組件100a（包括有分佈於其上的導電柱130）中的至少一者，並且將所述積體電路組件100a置放於介電層DI上。積體電路組件100a經由晶粒黏合膜（die attachment film；DAF）、黏附膠體或其類似物而附著或黏附在介電層DI上。在一些替代性實施例中，可拾取兩個或更多個積體電路組件100a並且將其置放於介電層DI上，且置放於介電層DI上的積體電路組件100a可呈陣列排列。
請參照圖7，積體電路組件100a經拾取並且置放於介電層DI上。在一些實施例中，可在導電的絕緣體穿孔TIV形成之後拾取積體電路組件100a並且將其置放於介電層DI上。在一些替代性實施例中，可在導電的絕緣體穿孔TIV形成之前拾取積體電路組件100a並且將其置放於介電層DI上。
如圖7中所示，於介電層DI上形成絕緣包封體210以覆蓋至少一個積體電路組件100a及導電的絕緣體穿孔TIV。在一些實施例中，絕緣包封體210是藉由模製製程（例如，壓縮模製製程）所形成的模製化合物。積體電路組件100a的導電柱130及保護層140a由絕緣包封體210覆蓋。換言之，積體電路組件100a的導電柱130及保護層140a未顯露並且被絕緣包封體210所保護。在一些實施例中，絕緣包封體210包括環氧樹脂或其他合適的介電材料。
請參照圖7及圖8，研磨絕緣包封體210直至導電柱130的頂表面及保護層140a的頂表面被暴露為至。在一些實施例中，藉由機械研磨製程及/或化學機械研磨（chemical mechanical polishing；CMP）製程來研磨絕緣包封體210。在絕緣包封體210被研磨之後，於介電層DI上方形成絕緣包封體210'。在絕緣包封體210的研磨製程期間，保護層140a、導電蓋體CAP以及導電柱130會被研磨，直至導電柱130的頂表面被暴露為止。由於導電蓋體CAP會被研磨，因此形成於導電蓋體CAP的頂表面上的探測標記不會降低導電柱130及積體電路組件100a的可靠性。在執行絕緣包封體210的研磨製程之後，會形成被研磨的保護層140a'。在一些實施例中，在絕緣包封體210的研磨製程期間，導電的絕緣體穿孔TIV亦會被部分地研磨。
如圖8中所示，絕緣包封體210'橫向地包覆至少一個積體電路組件100a的側壁，且絕緣包封體210'由導電的絕緣體穿孔TIV所貫穿。換言之，積體電路組件100a及導電的絕緣體穿孔TIV被嵌入於絕緣包封體210'之中。應注意，導電的絕緣體穿孔TIV的頂表面、絕緣包封體210'的頂表面以及導電柱130的頂表面可與保護層140a'的頂表面實質上共面。
請參照圖9，在絕緣包封體210'及保護層140a'形成之後，於導電的絕緣體穿孔TIV的頂表面、絕緣包封體210'的頂表面、導電柱130的頂表面以及保護層140a'的頂表面上形成電連接至積體電路組件100a的導電柱130的重佈線路結構220。如圖9中所示，重佈線路結構220包括交替堆疊的多個層間介電層222及多個重佈線導電層224。在一些實施例中，導電柱130的頂表面及導電的絕緣體穿孔TIV的頂表面會與重佈線路結構220接觸。在本實施例中，如圖9中所示，舉例而言，層間介電層222包括四個層間介電層222，且重佈線導電層224包括三個重佈線導電層224。
此外，於層間介電層222中的最頂部層間介電層上形成多個墊230，且墊230電連接至重佈線導電層224中的最頂部重佈線導電層。墊230包括用於導電球安裝的多個球下金屬層（under-ball metallurgy；UBM）圖案230a及用於被動組件安裝的多個連接墊230b。墊230經由重佈線導電層224而電連接至積體電路組件100a的導電柱130及導電的絕緣體貫穿柱TIV。應注意，球下金屬層圖案230a及連接墊230b的數目在本發明中不受限制。
由於藉由至少一個積體電路組件100a、絕緣包封體210'以及導電的絕緣體穿孔TIV所提供的上述重佈線路結構220的佈局面積相當大，因此，重佈線路結構220中的重佈線導電層224及/或層間介電層222的圖案化製程（即微影製程）因工具能力（tool capacity）而無法藉由單一罩幕來執行。應注意，重佈線導電層224及層間介電層222可具有不同圖案，且因此，在本實施例中，分別包括多個罩幕的不同罩幕組態可被用於重佈線導電層224及層間介電層222的製程中。在一些替代性實施例中，重佈線路結構220可僅包括兩個層間介電層222及夾在所述兩個層間介電層222之間的一個重佈線導電層224。應注意，層間介電層222及重佈線導電層224的數目在本發明中不受限制。
重佈線路結構220內的至少一個重佈線導電層224的製造將伴隨圖15、圖16A至圖16F、圖17A至圖17C、圖18A至圖18C、圖19以及圖20A至圖20C來描述。
請參照圖10，在球下金屬層圖案230a及連接墊230b形成之後，多個導電球240被置放於球下金屬層圖案230a上，且多個被動組件250被安裝於連接墊230b上。在一些實施例中，導電球240可藉由植球製程而置放於球下金屬層圖案230a上，且被動組件250可經由焊料回焊製程而安裝於連接墊230b上。在一些實施例中，舉例而言，導電球240的高度大於被動組件250的高度。應注意，在被動組件250安裝於連接墊230b上之後，最頂部的圖案化導電層124（例如銅層）與鈦/銅晶種圖案134之間的界面可引發較小的等效串聯電感（ESL）及/或等效串聯電阻（ESR）。
請參照圖10及圖11，在導電球240及被動組件250安裝於墊230上之後，令形成於絕緣包封體210'的底表面上的層間介電層DI與剝離層DB剝離，以使得層間介電層DI與載體C分離。在一些實施例中，剝離層DB（例如，LTHC釋放層）可由紫外光雷射照射，以使得層間介電層DI自載體C剝離。
如圖12中所示，接著，層間介電層DI被圖案化，以使得多個接觸開口O2形成進而暴露導電的絕緣體穿孔TIV的底表面。接觸開口O2的數目及位置可對應於導電的絕緣體穿孔TIV的數目。在一些實施例中，層間介電層DI的接觸開口O2是藉由雷射鑽孔製程或其他合適的圖案化製程形成。在一些替代性實施例中，層間介電層DI可自絕緣包封體210'的底表面完全移除，以便暴露出導電的絕緣體穿孔TIV的底表面。
請參照圖13，在接觸開口O2形成於層間介電層DI中之後，可將多個導電球260置放於由接觸開口O2所暴露的導電的絕緣體穿孔TIV的底表面上。並且，舉例而言，導電球260可經由回焊而與導電的絕緣體穿孔TIV的底表面接合。如圖13中所示，在導電球230及導電球260形成之後，具有雙面端子設計（即導電球240及260）的積體電路100的積體扇出封裝便已初步完成。
圖14為說明根據本揭露內容的一些實施例的疊層封裝（POP）結構的截面圖。請參照圖14，接著提供另一封裝300。舉例而言，封裝300為記憶體裝置或其他合適的半導體裝置。封裝300堆疊在圖13中所說明的積體扇出封裝上且經由導電球260而電連接至其所述積體扇出封裝，以使得製造出疊層封裝（POP）結構。在一些實施例中，疊層封裝（POP）結構可進一步包括配置於封裝300與圖13中所說明的積體扇出封裝之間的底填材料。底填材料可包覆導電球260以增強疊層封裝（POP）結構的可靠性及耐久性。
圖15根據本揭露內容的一些實施例示意性地說明用於製造導線的製造流程；圖16A至圖16F根據本揭露內容的一些實施例示意性地說明用於在重佈線路結構220中製造導線（即重佈線導電層224）的製造流程；圖17A根據本揭露內容的一些實施例示意性地說明圖16A中所示的第一罩幕M1及圖16B中所示的重疊部分OL的俯視圖；圖17B根據本揭露內容的一些實施例示意性地說明圖16C中所示的第二罩幕M2及圖16D中所示的重疊部分OL的俯視圖；以及圖17C根據本揭露內容的一些實施例示意性地說明圖16E中所示的重疊部分OL的俯視圖。
請參照圖15及圖16A至圖16F，在一些實施例中，用於製造導線（繪示於圖16F中）的方法可包括圖案化光阻層PR（步驟S10）及在光阻層PR中形成導線（S20）。在一些替代性實施例中，用於製造導線的方法可進一步包括在於光阻層PR中形成導線之後移除光阻層PR（步驟S30）。應注意，步驟S30在本揭露內容中是可選的。如圖15中所示，執行用於圖案化光阻層PR的多步驟曝光及顯影製程（即步驟S10），且多步驟曝光及顯影製程包括以下步驟（即步驟S11、S12、S13以及S14）。
如圖16A中所示，在一些實施例中，於至少一個積體電路組件100a及絕緣包封體210'上形成導電層C。而在形成導電層C之前，可於至少一個積體電路組件100a及絕緣包封體210'上形成層間介電層122。層間介電層122可包括暴露導電柱130及導電的絕緣體穿孔TIV的頂表面的多個接觸開口。在導電層C形成之後，可於導電層C上形成光阻層PR。在一些實施例中，舉例而言，導電層C充當晶種層且是藉由濺鍍製程形成，而光阻層PR可藉由旋塗製程而形成於導電層C上。
如圖15、圖16A、圖16B以及圖17A中所示，提供包括第一佈局圖案P1的第一罩幕M1（步驟S11）。第一罩幕M1覆蓋光阻層PR的第一部分PR1（例如，左部分），但第一罩幕M1不覆蓋光阻層PR的第二部分PR2（例如，右部分）。第一罩幕M1包括第一重疊區OL1。在一些實施例中，第一罩幕M1的第一佈局圖案P1可包括具有多個第一光穿透區域T1的第一遮光圖案。接著，執行經由第一罩幕M1的第一曝光製程E1以及執行第一顯影製程（步驟S12）以便在光阻層PR的第一部分PR1中形成多個第一走線開口OP1。經由第一罩幕M1的第一佈局圖案P1的遮蔽，光阻層PR被部分地圖案化，且對應於第一光穿透區域T1的第一走線開口OP1可形成於光阻層PR的第一部分PR1中。如圖16B中所示，導電層C藉由形成於光阻層PR的第一部分PR1中的第一走線開口OP1而部分地暴露。
在一些實施例中，為了防止光阻層PR的第二部分PR2曝光，第一罩幕M1可藉由遮光構件SH1（繪示於圖17A中）固定，且遮光構件SH1可遮蔽光阻層PR的第二部分PR2。在一些替代性實施例中，為了防止光阻層PR的第二部分PR2曝光，可提供遮光構件SH1（繪示於圖17A中）以遮蔽光阻層PR的第二部分PR2，且第一罩幕M1可不藉由遮光構件SH1固定。在另一實施例中，經由適當控制第一曝光製程E1中所使用的光源，可避免光阻層PR的第二部分PR2的不必要曝光。舉例而言，由第一曝光製程E1中所使用的光源提供的光可用電學方式來控制（例如，僅開啟光源對應於光阻層PR的重疊部分OL及第一部分PR1的部分區域）或用光學方式來控制（例如，對應於光阻層PR的第二部分PR2的光源的部分區域可被遮光構件所遮蔽），從而局部地照射在光阻層PR的重疊部分OL及第一部分PR1上。用於防止光阻層PR的第二部分PR2曝光的其他合適方式亦可在本揭露內容中使用。
如圖15、圖16C、圖16D以及圖17B中所示，提供包括第二佈局圖案P2的第二罩幕M2（步驟S13）。第二罩幕M2覆蓋光阻層PR的重疊部分OL及第二部分PR2（例如，右部分）。光阻層PR的重疊部分OL是依序由第一罩幕M1（繪示於圖16A中）及第二罩幕M2所覆蓋的區域。換言之，光阻層PR的重疊部分OL是第一部分PR1的部分且對應於第一罩幕M1的第一重疊區OL1。除了重疊部分OL之外，光阻層PR的第一部分PR1（例如，左部分）不會被第二罩幕M2覆蓋。第二罩幕M2包括第二重疊區OL2且第二重疊區OL2覆蓋且對應於光阻層PR的重疊部分OL。在一些實施例中，第二罩幕M2的第二佈局圖案P2可包括具有多個第二光穿透區域T2的第二遮光圖案。接著，執行經由第二罩幕M2的第二曝光製程E2以及執行第二顯影製程（步驟S14）以便在光阻層PR的第二部分PR2中形成多個第二走線開口OP2。當執行第二曝光製程E2時，令第二罩幕M2的第二佈局圖案P2與形成於光阻層PR的重疊部分OL中的第一走線開口OP1實質上對準。換言之，當執行第二曝光製程E2時，第二光穿透區域T2與形成於光阻層PR的重疊部分OL中的第一走線開口OP1可實質上對準。經由第二罩幕M2的第二佈局圖案P2的遮蔽，光阻層PR可被進一步圖案化，且對應於第二光穿透區域T2的第二走線開口OP2可形成於光阻層PR的第二部分PR2中。如圖16D中所示，導電層C可藉由形成於光阻層PR中的第一走線開口OP1及第二走線開口OP2而部分地暴露。
在一些實施例中，為了防止未被第二罩幕M2覆蓋的第一部分PR1曝光，第二罩幕M2可藉由遮光構件SH2（繪示於圖17B中）固定，且遮光構件SH2可遮蔽未被第二罩幕M2所覆蓋的第一部分PR1。在一些替代性實施例中，為了防止未被第二罩幕M2覆蓋的第一部分PR1曝光，可提供遮光構件SH2（繪示於圖17B中）以遮蔽未被第二罩幕M2覆蓋的第一部分PR1，且第二罩幕M2可不藉由遮光構件SH2固定。在另一實施例中，經由適當控制第二曝光製程E2中所使用的光源，可避免未被第二罩幕M2覆蓋的第一部分PR1的不必要曝光。舉例而言，由第二曝光製程E2中所使用的光源提供的光可用電學方式來控制（例如，僅開啟光源對應於光阻層PR的重疊部分OL及第二部分PR2的部分區域）或用光學方式來控制（例如，對應於光阻層PR的第一部分PR1的光源的部分區域可被遮光構件所遮蔽），從而局部地輻照射在光阻層PR的重疊部分OL及第二部分PR2上。用於防止光阻層PR的第一部分分PR1的不必要曝光的其他合適方式亦可在本揭露內容中使用。
在執行第二曝光製程E2及第二顯影製程之後，形成於光阻層PR中的第一走線開口OP1及第二走線開口OP2在重疊部分OL處相連通。如圖17B中所示，由於對準移位（即重疊移位），重疊偏移可出現在第一走線開口OP1與第二走線開口OP2之間。
如圖15、圖16E以及圖17B中所示，在形成第一走線開口OP1及第二走線開口OP2之後，可經由例如電鍍製程而於第一走線開口OP1及第二走線開口OP2中形成多個導線。換言之，導線可形成於（例如，電鍍於）由第一走線開口OP1及第二走線開口OP2所部分地暴露的導電層C上。在一些實施例中，可於光阻層PR的第一走線開口OP1及第二走線開口OP2中形成分別包括第一導電區段W1及第二導電區段W2的導線（S20）。換言之，導線的第一導電區段W1形成於第一走線開口OP1中，且導線的第二導電區段W2形成於第二走線開口OP2中。
如圖16F及圖17C中所示，在於光阻層PR的第一走線開口OP1及第二走線開口OP2中形成導線（步驟S30）之後，光阻層PR的第一部分PR1及第二部分PR2被移除。在移除第一部分PR1及第二部分PR2之後，未被第一導電區段W1及第二導電區段W2所覆蓋的部分導電層C將經由例如蝕刻製程而被移除，直至層間介電層122被暴露為止。在一些替代性實施例中，可省略導電層C的形成及導電層C的圖案化製程。如圖17C中所示，在一些實施例中，第一導電區段W1及第二導電區段W2在重疊部分OL處連接，且由於罩幕M1及/或罩幕M2的對準移位（即重疊移位），重疊偏移可出現在第一導電區段W1與第二導電區段W2之間。應注意，罩幕M1及/或罩幕M2的對準移位可輕易地由上述重疊偏移進行判斷。
圖18A根據本揭露內容的一些替代性實施例示意性地說明圖16A中所示的第一罩幕M1及圖16B中所示的重疊部分OL的俯視圖；圖18B根據本揭露內容的一些替代性實施例示意性地說明圖16C中所示的第二罩幕M2及圖16D中所示的重疊部分OL的俯視圖；以及圖18C根據本揭露內容的一些替代性實施例示意性地說明圖16E中所示的重疊部分OL的俯視圖。
請參照圖18A至圖18C，形成於重疊部分OL中的第一走線開口OP1的寬度WD1大於形成於未被第二罩幕M2覆蓋的第一部分PR1中的第一走線開口OP1的寬度WD2。舉例而言，寬度WD1與寬度WD2的比值（即WD1/WD2）可在約1.2至約2的範圍內。在一些實施例中，形成於重疊部分OL中的第一走線開口OP1的寬度WD2可實質上等於形成於第二部分PR2中的第二走線開口OP2的寬度WD3。由於重疊移位，第一走線開口OP1的寬度可從WD1增大至WD4。應注意，罩幕M1及/或罩幕M2的對準移位可輕易地由上述重疊偏移進行判斷。
圖19根據本揭露內容的一些實施例示意性地說明用於製造導線的另一製造流程；圖20A根據本揭露內容的一些替代性實施例示意性地說明圖16A中所示的第一罩幕M1及圖16B中所示的重疊部分OL的俯視圖；圖20B根據本揭露內容的一些替代性實施例示意性地說明圖16C中所示的第二罩幕M2及圖16D中所示的重疊部分OL的俯視圖；以及圖20C根據本揭露內容的一些替代性實施例示意性地說明圖16E中所示的重疊部分OL的俯視圖。
請參照圖19，在一些實施例中，提供一種用於製造導線的方法，其包括圖案化光阻層（S40）、在光阻層中形成對準標記（S50）以及在光阻層中形成導線（S60）。在一些實施例中，可同時或依序地執行在光阻層中形成對準標記（S50）及在光阻層中形成導線（S60）的步驟。舉例而言，對準標記可於在光阻層中形成導線之前或之後形成。替代地，對準標記及導線可藉由同一製程（例如電鍍製程）形成。在一些替代性實施例中，用於製造導線的方法可進一步包括在光阻層中形成導線之後移除光阻層（步驟S70）。應注意，步驟S70在本揭露內容中是可選的。
如圖19中所示，執行用於圖案化光阻層的多步驟曝光及顯影製程（即步驟S40），且多步驟曝光及顯影製程可包括以下步驟（即步驟S41、S42、S43以及S44）。提供包括第一對準圖案及第一佈局圖案的第一罩幕（步驟S41）。執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以便在所述光阻層的第一部分中形成第一對準開口及多個第一走線開口，其中所述光阻層的所述第一部分由所述第一罩幕覆蓋（步驟S42）。提供包括第二對準圖案及第二佈局圖案的第二罩幕（步驟S43）。執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以便在所述光阻層的第二部分中形成多個第二走線開口，其中所述光阻層的第一部分及第二部分的重疊部分由所述第二罩幕覆蓋，且當執行所述第二曝光製程時，所述第二罩幕的所述第二對準圖案與形成於所述光阻層中的所述第一對準開口實質上對準（步驟S44）。
圖19中所說明的用於製造導線的方法與圖15中所說明的方法類似，不同之處在於：圖19中所說明的導線的製程進一步包括製造對準標記（即步驟S40及S50）。因此，省略關於導線的詳細描述。
請參照圖19及圖20A，提供包括第一對準圖案AP1及第一佈局圖案P1（繪示於圖17A或圖18A中）的第一罩幕M1（步驟S41）。舉例而言，在第一罩幕M1上，第一對準圖案AP1可連接至第一佈局圖案P1。第一罩幕M1覆蓋光阻層PR的第一部分PR1（例如，左部分），但第一罩幕M1不覆蓋光阻層PR的第二部分PR2（例如，右部分）。第一罩幕M1包括第一重疊區OL1且第一對準圖案AP1分佈於第一重疊區OL1中。在一些實施例中，第一罩幕M1的第一對準圖案AP1可包括具有多個第三光穿透區域T3的第一遮光圖案。接著，執行經由第一罩幕M1的第一曝光製程以及執行第一顯影製程（步驟S42）以便在光阻層PR的第一部分PR1中形成第一對準開口OP3及多個第一走線開口OP1（繪示於圖17A或圖18A中）。經由第一罩幕M1的第一對準圖案AP1及第一佈局圖案P1的遮蔽，光阻層PR可被部分地圖案化，以使得對應於第三光穿透區域T3的第一對準開口OP3及對應於第一光穿透區域T1的第一走線開口OP1可被形成於光阻層PR的第一部分PR1中。在一些實施例中，導電層C（繪示於圖16E中）被形成於光阻層PR的第一部分PR1中的第一對準開口OP3及第一走線開口OP1部分地暴露。
請參照圖19及圖20A，提供包括第二對準圖案AP2及第二佈局圖案P2的第二罩幕M2（步驟S43）。舉例而言，在第二罩幕M2上，第二對準圖案AP2可連接至第二佈局圖案P2。第二罩幕M2覆蓋光阻層PR的重疊部分OL及第二部分PR2（例如，右部分）。重疊部分OL是依序由第一罩幕M1（繪示於圖16A中）及第二罩幕M2覆蓋的區域。換言之，重疊部分OL是第一部分PR1的部分且對應於第一罩幕M1的第一重疊區OL1。除重疊部分OL之外，光阻層PR的第一部分PR1（例如，左部分）不被第二罩幕M2覆蓋。第二罩幕M2包括第二重疊區OL2且第二重疊區OL2對應於重疊部分OL。第二對準圖案AP2分佈於第二重疊區OL2中。在一些實施例中，第二罩幕M2的第二對準圖案AP2可包括具有多個第四光穿透區域T4的第四遮光圖案。接著，執行經由第二罩幕M2的第二曝光製程以及執行第二顯影製程（步驟S44）以便在光阻層PR的重疊部分OL中形成多個第二走線開口OP2。在一些實施例中，在執行第二曝光製程及第二顯影製程之後，與第一對準開口OP3對準的第二對準開口OP4可進一步形成於光阻層PR中。當執行第二曝光製程時，第二罩幕M2的第二對準圖案AP2與形成於光阻層PR的重疊部分OL中的第一對準開口OP3實質上對準或相對應。換言之，當執行第二曝光製程時，第四光穿透區域T4與形成於光阻層PR的重疊部分OL中的第一對準開口OP3實質上對準。經由第二罩幕M2的第二對準圖案AP2的遮蔽，光阻層PR會被圖案化，且對應於第四光穿透區域T4的第二對準開口OP4可形成於光阻層PR的重疊部分OL中。如圖20B中所示，導電層C（繪示於圖16E中）由形成於光阻層PR中的第一對準開口OP3及第二對準開口OP4部分地暴露。
在執行第二曝光製程及第二顯影製程之後，形成於光阻層PR中的第一對準開口OP3及第二對準開口OP4在重疊部分OL處彼此對準。如圖20B中所示，第二對準開口OP4可與第一對準開口OP3隔開。此外，由於對準移位（即重疊移位），重疊偏移可出現在第一走線開口OP1與第二走線開口OP2之間。
如圖19、圖20B及以及圖20C中所示，在形成第一對準開口OP3及第二對準開口OP4之後，可經由例如電鍍製程而於第一對準開口OP3及第二對準開口OP4中形成至少一個對準標記（例如，對準標記AM1及AM2）。換言之，對準標記AM1及AM2會形成（例如，電鍍）於被第一對準開口OP3及第二對準開口OP4所部分地暴露出的導電層C（繪示於圖16E中）上。在一些實施例中，導線及對準標記AM1及AM2可藉由同一電鍍製程形成。
如圖20C中所示，在對準標記AM1及AM2形成於光阻層PR的第一對準開口OP3及第二對準開口OP4中（步驟S50）之後，光阻層PR的第一部分PR1及第二部分PR2被移除。在移除第一部分PR1及第二部分PR2之後，未被對準標記AM1及AM2覆蓋的部分導電層C（繪示於圖16E中）將藉由例如蝕刻製程而移除，直至層間介電層122被暴露為止。在一些替代性實施例中，可省略導電層C（繪示於圖16E中）的形成及導電層C的圖案化製程。
在一些實施例中，對準標記AM1具有對準凹口且對準標記AM2延伸至所述對準凹口中。在一些替代性實施例中，對準標記AM2具有對準凹口且對準標記AM1延伸至所述對準凹口中。對準標記AM1及AM2的形狀在本揭露內容中不受限制。對準標記AM1及AM2在重疊部分OL處彼此隔開，且由於對準移位（即重疊移位），重疊偏移可出現在對準標記AM1與AM2之間。應注意，罩幕M1及/或罩幕M2的對準移位可輕易地由對準標記AM1與AM2之間的距離判斷。舉例而言，對準標記AM1與AM2之間的距離可為約5微米。
雖然描述了上述製程以製造重佈線路結構220中的重佈線導電層224為例，但上述製程亦可用以製造重佈線路結構220中的層間介電層222（繪示於圖9中）。
根據一些實施例，提供一種用於製造導線的方法，其包括圖案化光阻層及在光阻層中形成導線。圖案化光阻層包括以下步驟。提供包括第一佈局圖案的第一罩幕。執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以便在所述光阻層的第一部分中形成多個第一走線開口，其中所述光阻層的所述第一部分由所述第一罩幕覆蓋。提供包括第二佈局圖案的第二罩幕。執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以便在所述光阻層的第二部分中形成多個第二走線開口，其中所述光阻層的所述第一部分及所述第二部分的重疊部分由所述第二罩幕覆蓋，所述第一走線開口及所述第二走線開口在所述重疊部分處連通，且當執行所述第二曝光製程時，所述第二罩幕的所述第二佈局圖案與形成於所述光阻層中的所述第一走線開口實質上對準。所述導線形成於所述光阻層的所述第一走線開口及所述第二走線開口中。
根據一些替代性實施例，提供一種用於製造導線的方法，其包括圖案化光阻層、在光阻層中形成對準標記以及在光阻層中形成導線。圖案化光阻層包括以下步驟。提供包括第一對準圖案及第一佈局圖案的第一罩幕。執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以便在所述光阻層的第一部分中形成第一對準開口及多個第一走線開口，其中所述光阻層的所述第一部分由所述第一罩幕覆蓋。提供包括第二對準圖案及第二佈局圖案的第二罩幕。執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以便在所述光阻層的第二部分中形成多個第二走線開口，其中所述光阻層的所述第一部分及所述第二部分的重疊部分由所述第二罩幕覆蓋，且當執行所述第二曝光製程時，所述第二罩幕的所述第二對準圖案與形成於所述光阻層中的所述第一對準開口實質上對準。對準標記形成於第一對準開口中。導線形成於第一走線開口及第二走線開口中。
根據一些替代性實施例，提供一種用於製造晶片封裝的方法，其包括以下步驟。形成絕緣包封體以橫向地包覆至少一個積體電路組件的側壁。在所述至少一個積體電路組件及所述絕緣包封體上形成導電層。在所述導電層上形成光阻層且執行多步驟曝光及顯影製程以圖案化所述光阻層。對準標記形成於所述光阻層中。多個導線形成於所述光阻層中。執行所述多步驟曝光及顯影製程以圖案化所述光阻層，且所述多步驟曝光及顯影製程包括以下步驟。提供包括第一對準圖案及第一佈局圖案的第一罩幕。執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以便在所述光阻層的第一部分中形成第一對準開口及多個第一走線開口，其中所述光阻層的所述第一部分由所述第一罩幕覆蓋。提供包括第二對準圖案及第二佈局圖案的第二罩幕。執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以便在所述光阻層的第二部分中形成多個第二走線開口，其中所述光阻層的所述第一部分及所述第二部分的部分由所述第二罩幕覆蓋，且當執行所述第二曝光製程時，所述第二罩幕的所述第二對準圖案與形成於所述光阻層中的所述第一對準開口實質上對準。對準標記形成於第一對準開口中。導線形成於所述第一走線開口及所述第二走線開口中，其中所述導線電連接至所述至少一個積體電路組件。
前文概述若干實施例的特徵，使得熟習此項技術者可更好地理解本揭露內容的態樣。熟習此項技術者應瞭解，熟習此項技術者可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且熟習此項技術者可在不脫離本揭露內容的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
100、100a‧‧‧積體電路組件
110、110a‧‧‧半導體基底
120、120a‧‧‧內連線結構
122、222‧‧‧層間介電層
124‧‧‧圖案化導電層
130‧‧‧導電柱
132‧‧‧柱體部分
134‧‧‧晶種圖案
140、140a、140a'‧‧‧保護層
210、210'‧‧‧絕緣包封體
220‧‧‧重佈線路結構
224‧‧‧重佈線導電層
230‧‧‧墊
230a‧‧‧球下金屬層（UBM）圖案
230b‧‧‧連接墊
240、260‧‧‧導電球
250‧‧‧被動組件
300‧‧‧封裝
AM1、AM2‧‧‧對準標記
AP1‧‧‧第一對準圖案
AP2‧‧‧第二對準圖案
C‧‧‧載體/導電層
CAP‧‧‧導電蓋體
DB‧‧‧剝離層
DI‧‧‧層間介電層
E1‧‧‧第一曝光製程
E2‧‧‧第二曝光製程
M1‧‧‧第一罩幕
M2‧‧‧第二罩幕
O1‧‧‧開口
O2‧‧‧接觸開口
OL‧‧‧重疊部分
OL1‧‧‧第一重疊區
OL2‧‧‧第二重疊區
OP1‧‧‧第一走線開口
OP2‧‧‧第二走線開口
OP3‧‧‧第一對準開口
OP4‧‧‧第二對準開口
P1‧‧‧第一佈局圖案
P2‧‧‧第二佈局圖案
PR‧‧‧光阻層
PR1‧‧‧第一部分
PR2‧‧‧第二部分
SH1、SH2‧‧‧遮光構件
SL‧‧‧切割道
S10、S11、S12、S13、S14、S20、S30、S40、S41、S42、S43、S44、S50、S60、S70‧‧‧步驟
T1‧‧‧第一光穿透區域
T2‧‧‧第二光穿透區域
T3‧‧‧第三光穿透區域
T4‧‧‧第四光穿透區域
TIV‧‧‧導電的絕緣體穿孔
W‧‧‧晶圓
W1‧‧‧第一導電區段
W2‧‧‧第二導電區域
WD1、WD2、WD3、WD4‧‧‧寬度
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵之尺寸。 圖1至圖5根據本揭露內容的一些實施例示意性地說明用於製造積體電路組件的製造流程。 圖6至圖13根據本揭露內容的一些實施例示意性地說明用於製造晶片封裝的製造流程。 圖14為說明根據本揭露內容的一些實施例的疊層封裝（package-on-package；POP）結構的截面圖。 圖15根據本揭露內容的一些實施例示意性地說明用於製造導線的製造流程。 圖16A至圖16F根據本揭露內容的一些實施例示意性地說明用於在重佈線路結構220中製造導線（即重佈線導電層224）的製造流程。 圖17A根據本揭露內容的一些實施例示意性地說明圖16A中所示的第一罩幕M1及圖16B中所示的重疊部分OL的俯視圖。 圖17B根據本揭露內容的一些實施例示意性地說明圖16C中所示的第二罩幕M2及圖16D中所示的重疊部分OL的俯視圖。 圖17C根據本揭露內容的一些實施例示意性地說明圖16E中所示的重疊部分OL的俯視圖。 圖18A根據本揭露內容的一些替代性實施例示意性地說明圖16A中所示的第一罩幕M1及圖16B中所示的重疊部分OL的俯視圖。 圖18B根據本揭露內容的一些替代性實施例示意性地說明圖16C中所示的第二罩幕M2及圖16D中所示的重疊部分OL的俯視圖。 圖18C根據本揭露內容的一些替代性實施例示意性地說明圖16E中所示的重疊部分OL的俯視圖。 圖19根據本揭露內容的一些實施例示意性地說明用於製造導線的另一製造流程。 圖20A根據本揭露內容的一些替代性實施例示意性地說明圖16A中所示的第一罩幕M1及圖16B中所示的重疊部分OL的俯視圖。 圖20B根據本揭露內容的一些替代性實施例示意性地說明圖16C中所示的第二罩幕M2及圖16D中所示的重疊部分OL的俯視圖。 圖20C根據本揭露內容的一些替代性實施例示意性地說明圖16E中所示的重疊部分OL的俯視圖。

Claims (20)

  1. 一種用於製造導線的方法，包括： 圖案化光阻層，包括： 提供包括第一佈局圖案的第一罩幕； 執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以在所述光阻層的第一部分中形成多個第一走線開口，且所述光阻層的所述第一部分由所述第一罩幕覆蓋； 提供包括第二佈局圖案的第二罩幕； 執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以在所述光阻層的第二部分中形成多個第二走線開口，所述光阻層的所述第一部分及所述第二部分的重疊部分由所述第二罩幕覆蓋，所述第一走線開口及所述第二走線開口在所述重疊部分處連通，且當執行所述第二曝光製程時，所述第二罩幕的所述第二佈局圖案與形成於所述光阻層中的所述第一走線開口實質上對準；以及 在所述第一走線開口及所述第二走線開口中形成所述導線。
  2. 如申請專利範圍第1項所述的方法，其中所述第一罩幕的所述第一佈局圖案包括具有對應於所述第一走線開口的多個第一光穿透區域的第一遮光圖案，且所述第二罩幕的所述第二佈局圖案包括具有對應於所述第二走線開口的多個第二光穿透區域的第二遮光圖案。
  3. 如申請專利範圍第1項所述的方法，其中所述第一罩幕包括對應於所述重疊部分的第一重疊區，且所述第二罩幕包括對應於所述重疊部分的第二重疊區。
  4. 如申請專利範圍第1項所述的方法，其中形成於所述重疊部分中的所述第一走線開口的第一寬度大於形成於未被所述第二罩幕覆蓋的所述第一部分中的所述第一走線開口的第二寬度。
  5. 如申請專利範圍第1項所述的方法，其中所述導線包括形成於所述第一走線開口中的多個第一導電區段及形成於所述第二走線開口中的多個第二導電區段。
  6. 如申請專利範圍第5項所述的方法，其中重疊偏移出現在所述第一導電區段與所述第二導電區段之間。
  7. 一種用於製造導線的方法，包括： 圖案化光阻層，包括： 提供包括第一對準圖案及第一佈局圖案的第一罩幕； 執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以在所述光阻層的第一部分中形成第一對準開口及多個第一走線開口，且所述光阻層的所述第一部分由所述第一罩幕覆蓋； 提供包括第二對準圖案及第二佈局圖案的第二罩幕； 執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以在所述光阻層的第二部分中形成多個第二走線開口，所述光阻層的所述第一部分及所述第二部分的重疊部分由所述第二罩幕覆蓋，且當執行所述第二曝光製程時，所述第二罩幕的所述第二對準圖案與形成於所述光阻層中的所述第一對準開口實質上對準； 在所述第一對準開口中形成對準標記；以及 在所述第一走線開口及所述第二走線開口中形成所述導線。
  8. 如申請專利範圍第7項所述的方法，其中與所述第一對準開口對準的第二對準開口藉由執行所述第二曝光製程及所述第二顯影製程而另外形成於所述光阻層中，且所述對準標記形成於所述第一對準開口及所述第二對準開口中。
  9. 如申請專利範圍第7項所述的方法，其中與所述第一對準開口隔開的第二對準開口藉由執行所述第二曝光製程及所述第二顯影製程而另外形成於所述光阻層中，且所述對準標記形成於所述第一對準開口及所述第二對準開口中。
  10. 如申請專利範圍第9項所述的方法，其中所述第一對準標記具有對準凹口且所述第二對準標記延伸至所述對準凹口中。
  11. 如申請專利範圍第9項所述的方法，其中所述第二對準標記具有對準凹口且所述第一對準標記延伸至所述對準凹口中。
  12. 如申請專利範圍第7項所述的方法，其中所述第一罩幕的所述第一佈局圖案包括具有對應於所述第一走線開口的多個第一光穿透區域的第一遮光圖案，且所述第二罩幕的所述第二佈局圖案包括具有對應於所述第二走線開口的多個第二光穿透區域的第二遮光圖案。
  13. 如申請專利範圍第7項所述的方法，其中所述第一罩幕包括對應於所述重疊部分的第一重疊區，所述第二罩幕包括對應於所述重疊部分的第二重疊區，所述第一對準圖案分佈於所述第一罩幕的所述第一重疊區中，所述第二對準圖案分佈於所述第二罩幕的所述第二重疊區中，且所述第二罩幕的所述第二重疊區覆蓋形成於所述光阻層中的所述第一對準開口。
  14. 一種用於製造晶片封裝的方法，包括： 形成絕緣包封體以橫向地包覆至少一個積體電路組件的側壁； 在所述至少一個積體電路組件及所述絕緣包封體上形成導電層； 在所述導電層上形成光阻層且執行多步驟曝光及顯影製程以圖案化所述光阻層，其中執行所述多步驟曝光及顯影製程以圖案化所述光阻層包括： 提供包括第一對準圖案及第一佈局圖案的第一罩幕； 執行經由第一罩幕的第一曝光製程以及執行第一顯影製程以在所述光阻層的第一部分中形成第一對準開口及多個第一走線開口，且所述光阻層的所述第一部分由所述第一罩幕覆蓋； 提供包括第二對準圖案及第二佈局圖案的第二罩幕； 執行經由第二罩幕的第二曝光製程以及執行第二顯影製程以在所述光阻層的第二部分中形成多個第二走線開口，所述光阻層的所述第一部分及所述第二部分的部分由所述第二罩幕覆蓋，且當執行所述第二曝光製程時，所述第二罩幕的所述第二對準圖案與形成於所述光阻層中的所述第一對準開口實質上對準； 在所述第一對準開口中形成對準標記；以及 在所述第一走線開口及所述第二走線開口中形成多個導線，其中所述導線電連接至所述至少一個積體電路組件。
  15. 如申請專利範圍第14項所述的方法，其中與所述第一對準開口對準的第二對準開口藉由執行所述第二曝光製程及所述第二顯影製程而另外形成於所述光阻層中，且所述對準標記形成於所述第一對準開口及所述第二對準開口中。
  16. 如申請專利範圍第14項所述的方法，其中與所述第一對準開口隔開的第二對準開口藉由執行所述第二曝光製程及所述第二顯影製程而另外形成於所述光阻層中，且所述對準標記形成於所述第一對準開口及所述第二對準開口中。
  17. 如申請專利範圍第16項所述的方法，其中所述第一對準標記具有對準凹口且所述第二對準標記延伸至所述對準凹口中。
  18. 如申請專利範圍第16項所述的方法，其中所述第二對準標記具有對準凹口且所述第一對準標記延伸至所述對準凹口中。
  19. 如申請專利範圍第14項所述的方法，其中所述第一罩幕的所述第一佈局圖案包括具有對應於所述第一走線開口的多個第一光穿透區域的第一遮光圖案，且所述第二罩幕的所述第二佈局圖案包括具有對應於所述第二走線開口的多個第二光穿透區域的第二遮光圖案。
  20. 如申請專利範圍第14項所述的方法，其中所述第一罩幕包括對應於重疊部分的第一重疊區，所述第二罩幕包括對應於所述重疊部分的第二重疊區，所述第一對準圖案分佈於所述第一罩幕的所述第一重疊區中，所述第二對準圖案分佈於所述第二罩幕的所述第二重疊區中，且所述第二罩幕的所述第二重疊區覆蓋形成於所述光阻層中的所述第一對準開口。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10748861B2 (en) * 2018-05-16 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10748831B2 (en) * 2018-05-30 2020-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packages having thermal through vias (TTV)
KR102499039B1 (ko) * 2018-11-08 2023-02-13 삼성전자주식회사 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법
CN111128754A (zh) * 2019-12-04 2020-05-08 通富微电子股份有限公司 一种扇出型封装方法及扇出型封装器件
KR20220099333A (ko) * 2021-01-06 2022-07-13 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63275115A (ja) 1987-05-06 1988-11-11 Nec Corp 半導体装置のパタ−ン形成方法
JPH0645581A (ja) 1992-07-22 1994-02-18 Toshiba Corp 半導体装置の製造方法
US7067931B1 (en) 2000-12-14 2006-06-27 Koninklijke Philips Electronics N.V. Self-compensating mark design for stepper alignment
US9097989B2 (en) 2009-01-27 2015-08-04 International Business Machines Corporation Target and method for mask-to-wafer CD, pattern placement and overlay measurement and control
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9535316B2 (en) 2013-05-14 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Photomask with three states for forming multiple layer patterns with a single exposure
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9666522B2 (en) * 2014-05-29 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Alignment mark design for packages
JP6246076B2 (ja) 2014-06-05 2017-12-13 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US10049986B2 (en) 2015-10-30 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of making the same
US9741669B2 (en) 2016-01-26 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Forming large chips through stitching
US9899342B2 (en) * 2016-03-15 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, redistribution circuit structure, and method of fabricating the same
US9991207B2 (en) * 2016-03-24 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Test key strcutures, integrated circuit packages and methods of forming the same
US10163805B2 (en) * 2016-07-01 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163802B2 (en) * 2016-11-29 2018-12-25 Taiwan Semicondcutor Manufacturing Company, Ltd. Fan-out package having a main die and a dummy die, and method of forming
CN107093584B (zh) 2017-05-05 2019-11-19 上海中航光电子有限公司 阵列基板、显示面板、显示装置以及阵列基板的制作方法
US10276428B2 (en) * 2017-08-28 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of fabricating semiconductor package
US10319707B2 (en) * 2017-09-27 2019-06-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component, package structure and manufacturing method thereof

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