TW201421635A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW201421635A
TW201421635A TW102141844A TW102141844A TW201421635A TW 201421635 A TW201421635 A TW 201421635A TW 102141844 A TW102141844 A TW 102141844A TW 102141844 A TW102141844 A TW 102141844A TW 201421635 A TW201421635 A TW 201421635A
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die
layer
forming
connector
metal
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TWI518858B (zh
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yi-chao Mao
Chin-Chuan Chang
Jui-Pin Hung
Jing-Cheng Lin
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Taiwan Semiconductor Mfg
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Abstract

本發明提供一種半導體裝置，包括：一半導體晶粒；一接著層，於半導體晶粒之一第一側；一塑形化合物，圍繞半導體晶粒與接著層，其中塑形化合物與接著層齊平；一第一後鈍化內連線(post-passiviation interconnect,PPI)，電性連接至半導體晶粒之一第二側；一第一連接器，電性連接至第一PPI，其中第一連接器位於塑形化合物上並對準塑形化合物。

Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置及其製造方法。
隨著半導體工藝的發展，半導體晶粒逐漸地變小。同時，必須整合更多的功能至半導體晶粒中。因此，在半導體晶粒中，必須有越來越多的輸入輸出(I/O)墊封裝於較小的範圍裡，且I/O墊的密度隨著時間快速的增加。因此，半導體晶粒的封裝變得更困難，其對封裝的產能造成不利的影響。
傳統的封裝技術可分成兩個類別。在第一類別中，在切割晶圓上的晶粒前進行封裝。這項封裝技術具有一些有利的特徵，例如高產能(throughput)與低成本。再者，底部封膠(underfill)或塑形(molding)元件的需求較少。然而，此封裝技術也有其缺點。如上述，晶粒的尺寸越來越小，僅可用扇入(fan-in)型封裝分別地封裝晶粒，其中各晶粒的I/O墊被限制到各個晶粒表面上的一個區域。在有限的晶粒範圍內，因為I/O墊之間距的限度，侷限了I/O墊的數量。若降低墊的間距，可能會存在焊錫橋(solder bridge)。此外，在固定球體尺寸的需求下，焊球具有一定的尺寸，這限制了在晶粒表面上可封裝的焊球數。
在另一類別的封裝中，封裝前從晶圓上切割晶 粒，且僅封裝“良品裸晶(known-good-dies)”。此封裝技術的一個有利特徵為形成扇出(fan-out)封裝的可能性，這代表晶粒上的I/O墊可被重新分佈(redistribute)至大於晶粒的範圍，因此，增加了封裝在晶粒表面上的I/O墊的數量。
本發明一實施例為一半導體裝置，包括：一半導體晶粒；一接著層，於半導體晶粒之一第一側；一塑形化合物，圍繞半導體晶粒與接著層，其中塑形化合物與接著層齊平；一第一後鈍化內連線(post-passiviation interconnect,PPI)，電性連接至半導體晶粒之一第二側；一第一連接器，電性連接至第一PPI，其中第一連接器位於塑形化合物上並對準塑形化合物。
本發明另一實施例為一種半導體裝置的製造方法，包括：形成一晶粒；以一接著層接附晶粒於於一切割黏晶膠帶上；切割晶粒；將晶粒於切割黏晶膠帶脫離；以接著層將晶粒接附於一載體，其中接著層與晶粒相接；以及以一聚合物將晶粒塑形，其中聚合物圍繞著(encircle)晶粒與接著層。
本發明又一種半導體裝置的製造方法，包括：形成多個晶粒於一基底上；以一膠層將些晶粒貼附至一切割黏晶膠帶；切割些晶粒；以膠層貼附些晶粒於一載體基底上，其中些晶粒至少兩者與載體基底之間的膠層為分離的，且其中分離的膠層大抵上對準於兩個晶粒；以及以一塑形化合物包覆(encapsulate)些晶粒，其中一部份的塑形化合物係位於兩個晶粒之間。
100‧‧‧晶粒
20‧‧‧基底
22‧‧‧積體電路裝置
24‧‧‧第一接合墊
26‧‧‧第二接合墊
28‧‧‧第一鈍化層
30‧‧‧第二鈍化層
32‧‧‧第一金屬柱
34‧‧‧第二金屬柱
36‧‧‧切割黏晶膠帶
38‧‧‧接著層
39‧‧‧切割線
40‧‧‧第一載體基底
42‧‧‧塑形化合物
44‧‧‧第一介電層
46‧‧‧第一開口
48‧‧‧第二開口
50‧‧‧第一後鈍化內連線
52‧‧‧第二後鈍化內連線
54‧‧‧光阻層
56‧‧‧第二介電層
58‧‧‧第三開口
60‧‧‧第四開口
62‧‧‧第一底凸塊金屬層
64‧‧‧第二底凸塊金屬層
66‧‧‧光阻
68‧‧‧第一連接器
70‧‧‧第二連接器
74‧‧‧塗層膠帶
76‧‧‧切割線
200‧‧‧封裝體
第1~14圖係根據不同示範性實施例繪示出封裝體在製造的中間階段之剖面示意圖。
第15圖係根據實施例繪示出示範性的封裝體。
本說明書將根據第1~14圖敘述封裝體結構在不同的製造階段。以下將會配合圖式對本發明實施例作出詳述。本說明書儘可能地在圖式與說明書中使用相同的參考數字對應到相同或相似的部件。在圖式中，為了清楚及方便性，而擴大形狀及厚度。以下說明將特別針對本發明實施例之裝置或是其中元件的形成部分。可以理解的是，未特別繪示或說明的元件可具有各種不同習知的型式。當本發明公開後，所屬技術領域中具有通常知識者亦能夠理解不脫離本發明之精神和範圍的等效構造可在不脫離本發明之精神和範圍內作任意之更動、替代與潤飾。
本說明書全文中所提及關於”一實施例”的意思是指有關於本實施例中所提及特定的特徵(feature)、結構、或特色係包含於本發明的至少一實施例中。因此，本說明書全文中各處所出現的”一實施例中”用語所指的並不全然表示為相同的實施例。再者，特定的特徵、結構、或特色能以任何適當方式而與一或多個實施例作結合。可以理解的是以下的圖式並未依照比例繪示，而僅僅提供說明之用。
以下將敘述有關特定背景的實施例，即帶有扇入(fan-in)封裝體結構。請參照第1圖，其顯示晶粒100在製程的 中間階段，包括基底20、第一接合墊24、以及第二接合墊26。基底20可為矽、鍺化矽、碳化矽、陶瓷基底、石英基底等、或前述之組合。基底20可包括塊材(bulk)矽、摻雜或未摻雜、或矽覆絕緣(silicon-on-insulator,SOI)基底的主動(active)層。可使用其他基底，包括多層(multi-layered)基底、梯度(gradient)基底、或混成定向(hybrid orientation)基底。
基底20可包括積體電路(integrated circuit)裝置22。此技藝人士應理解，可使用各種廣泛的積體電路裝置22(例如，電晶體、電容器、電阻器、或前述之組合等)以達成設計晶粒100的結構與功能上之需求。可使用任何適合的方法製造積體電路裝置22。
基底20亦可包括內連線(interconnect)結構(未顯示)。可在積體電路裝置22上形成內連線結構，內連線結構係設計用來連接不同的積體電路裝置22，以形成功能性電路。內連線結構可由介電層(例如，低介電常數材料)與導電層(例如，銅)交替形成，且可藉由任何適合的製程(例如，沉積、鑲嵌(damascene)、雙鑲嵌(dual damscene))形成。導電與介電層可包括金屬線與導孔(via)(未顯示)，以將積體電路裝置22電性連接至第一接合墊24及/或第二接合墊26。只有一部份的基底20繪示在圖中，如此將能充分的詳細敘述示範實施例。
在內連線結構上可形成第一與第二接合墊24、26，且接合墊24與內連線結構電性連接(未顯示)，以助於提供外部連線至積體電路裝置。第一與第二接合墊24、26可包括鋁、銅、鎳等、或前述之組合。第一與第二接合墊24、26的 形成可透過使用沉積製程(例如，濺鍍)以形成一材料層(未顯示)。之後，部份的材料層可透過適合的製程(例如微影遮罩(photolithographic masking)與蝕刻)移除而形成第一與第二接合墊24、26。然而，可使用任何其他適合的製程形成第一與第二接合墊24、26。第一與第二接合墊24、26之厚度可介於約0.5~4μm。
如第2圖所示，可在基底20與接合墊24之上形成第一鈍化層28。第一鈍化層28可由一或多種適合的介電材料製造，例如，氧化矽、氮化矽、低介電常數材料(例如，碳摻雜氧化物(carbon doped oxides))、極(extremely)低介電常數材料(例如，多孔碳摻雜二氧化矽(porous carbon doped silicon dioxide))、聚合物(例如，聚亞醯胺(polyimide))、阻焊料(solder resist)、聚苯噁唑(polybenzoxazole,PBO))、苯並環丁烯(benzocyclobutene,BCB)、塑形化合物等、或前述之組合。可透過如化學氣相沉積(chemical vapor deposition,CVD)的製程形成第一鈍化層28，然而亦可使用任何合適的製程，且第一鈍化層28之後度介於約0.5~30μm。一些實施例中，第一與第二接合墊24、26之頂表面與第一鈍化層28之底表面大抵上為齊平。
第3圖繪示出在第一鈍化層28上之第二鈍化層30的形成、在第一與第二鈍化層30與30中且電性連接至第一接合墊24之第一金屬柱(pillar)32的形成、以及在第一與第二鈍化層30與30中且電性連接至第二接合墊26的第二金屬柱34之形成。
可在第一鈍化層28上形成第二鈍化層30。第二鈍化層30可由聚合物(例如，聚亞醯胺(polyimide))所組成。另外，第二鈍化層30可由相似於第一鈍化層28的材料所組成，例如，氧化矽、氮化矽、低介電常數材料、極(extremely)低介電常數材料、苯並環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO))等、或前述之組合。第二鈍化層30之厚度可介於約2~15μm。
在形成第二鈍化層30之後，可在第一接合墊24上形成第一金屬柱(pillar)32，以透過第一及第二鈍化層28、30物理性與電性接觸到第一接合墊24。同時，可藉由形成第一金屬柱32的製程而在第一鈍化層28上形成第二金屬柱，以透過第一與第二鈍化層28、30而提供物理與電性接觸至第二接合墊26。
可藉由在第一與第二鈍化層26、28中形成開口進而形成第一與第二金屬柱32、34，開口可用，例如，蝕刻、研磨(milling)、雷射技術、或前述之組合等方式形成。可以保角(conformally)的方式在第二鈍化層30上與開口中沉積薄阻障(barrier)層(未顯示)，沉積的方式可包括CVD，原子層沉積(atomic layer deposition,ALD)等、或前述之組合。阻障層可包括氮化物或氮氧化物，例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢、二氧化矽等、或前述之組合。可在薄阻障層上與開口中沉積導電材料。可由電化學電鍍(eletro-chemical plating)製程、CVD、ALD、物理氣相沉積(physical vapor deposition,PVD)等、或前述之組合形成導電材料。導電材料可 為銅、鎢、鋁、銀、金等、或前述之組合。接著，可圖案化導電材料以形成第一與第二金屬柱32、34。
在一實施例中，第一金屬柱32的頂表面30A大抵上與第二鈍化層30之頂表面及第二金屬柱34之頂表面齊平。另一實施例中，第一金屬柱32之頂表面及/或第二金屬柱34之頂表面可低於第二鈍化層30之頂表面，且第二鈍化層30有一薄部份覆蓋著第一金屬柱32及/或第二金屬柱34。
第4圖繪示出將晶粒100貼附至切割黏晶膠帶(dicing tape)36。切割黏晶膠帶36可在隨後使一晶粒100從相鄰的晶粒100分離的切割製程(singulation)期間，提供暫時的機械與結構支撐。可將晶粒100貼附(affix)或接合(bond)至切割黏晶膠帶36，其中切割黏晶膠帶36可包括內嵌式接著(embedded adhesive)層38。如第4圖所示，可有多個在晶圓上彼此相同的晶粒100設置於切割黏晶膠帶36上。
可沿著切割線(scribe line)39進行切割製程，以形成單一晶粒100。可藉由切割(cutting)製程或單粒化製程進行切割製程，其中可使用機械或雷射切刀以將多個晶粒100互相分離。在切割製程之後，分離的晶粒100可由切割黏晶膠帶36上移除或脫離(de-bond)。
第5圖繪示出將晶粒100固定至第一載體基底40。第一載體基底40可在隨後的加工步驟期間提供暫時的機械與結構支撐。可使用已存在的接著層38將晶粒100固定至第一載體基底40。儘管只繪示出單一個晶粒100，本發明可有多個彼此相同的晶粒100置於第一載體基底40上。一實施例 中，其中晶粒100包括基底20、及與基底20之底表面接觸的接著層38。一些實施例中，在相鄰的晶粒100之間留有間隔，其中在間隔中不含有接著層。在一實施例中，第一載體基底40可包括玻璃、氧化矽、氧化鋁等、或前述之組合。接著層38可包括任何合適的接著劑，例如，晶粒接附膜(die attach film)等。
第6圖繪示出在晶粒100上對聚合物42塑形。聚合物42可為塑形化合物，因此，儘管其可為其他材料所形成，以下仍可被稱為塑形化合物42。塑形化合物42可包括有機材料，例如環氧樹脂(epoxy)，其可填入晶粒100之間的間隔。塑形化合物42也覆蓋可晶粒100之頂表面。一實施例中，塑形化合物42之底表面與第一載體基底40接觸。可進行硬化(curing)製程以將塑形化合物42固化(solidify)。
又如第6圖所示，可在塑形化合物42上進行平坦化(planarization)製程(例如研磨(grinding))直到暴露出第一金屬柱32與第二金屬柱34，亦可能會暴露出第二鈍化層30。因此，第二鈍化層30之頂表面、第一金屬柱32的頂表面、第二金屬柱34之頂表面、塑形化合物42之頂表面大抵上相互齊平。在本發明實施例中，其中第一金屬柱32及/或第二金屬柱34係嵌入(embedded)第二鈍化層30中，且亦可研磨部份的第二鈍化層30。如此一來，在研磨後，在晶粒100上可能不再有塑形化合物42。在第6圖之結構的上視圖中，塑形化合物42可圍繞(encircled)晶粒100。
第7圖繪示出在塑形化合物42、第二鈍化層30、 第一金屬柱32、及第二金屬柱34上方形成第一介電層44。第一介電層44可由一或多個合適的介電材料所形成，例如，氧化矽、氮化矽、低介電常數材料(例如，碳摻雜氧化物(carbon doped oxides))、極低介電常數材料(例如，多孔碳摻雜二氧化矽(porous carbon doped silicon dioxide))、聚合物(例如，聚亞醯胺(polyimide))、聚苯噁唑(polybenzoxazole,PBO))、苯並環丁烯(benzocyclobutene,BCB)等、或前述之組合。可透過如化學氣相沉積的製程形成第一介電層44，然而，可使用任何合適的製程。
形成第一介電層44之後，如第8圖所示，可形成穿透第一介電層44的第一開口46與第二開口48。第一開口46可形成於第一介電層44中以暴露出部份的第一金屬柱32，而第二開口48可形成於第一介電層44中以暴露出部份的第二金屬柱34。可藉由，例如，蝕刻、研磨(milling)、雷射技術、或前述之組合等方式形成第一開口46與第二開口48。一些實施例中，可同時形成第一開口46與第二開口48。
第9圖繪示出在第一開口46中形成第一後鈍化內連線(post-passivation interconnect,PPI)50、與在第二開口48中形成第二PPI 52。第一PPI 50可在第一金屬柱32與隨後形成的底凸塊金屬層(under bump metallization,UBM)62(詳見第11圖)之間提供電性連接，而第二PPI 52可在第二金屬柱34與隨後形成的UBM 64(詳見第11圖)之間提供電性連接。
一實施例中，第一與第二PPI 50、52可包括銅、鎢、鋁、銀、金等、或前述之組合。一些實施例中，第一與第 二PPIs 50、52可包括上述的阻障層(關於第一金屬柱32與第二金屬柱34的段落)。可藉由形成光阻層54後將其圖案化，接著再形成第一與第二PPI 50、52，可藉由電化學電鍍製程、CVD、ALD、PVD等、或前述之組合形成第一與第二PPI 50、52。在形成第一與第二PPI 50、52後，可移除光阻層54。
第10圖繪示出在第一介電層44、第一PPI 50、與第二PPI 52上方形成第二介電層56。一些實施例中，雖然第一與第二介電層44、56不必為相同材料，但第二介電層56可包括相同於第一介電層44的材料，例如，氧化矽、氮化矽、碳摻雜氧化物(carbon doped oxides)、多孔碳摻雜二氧化矽(porous carbon doped silicon dioxide)、聚亞醯胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)等、或前述之組合。可透過如化學氣相沉積的製程形成第二介電層56，然而，可使用任何合適的製程。
在沉積第二介電層56之後，可形成第三開口58與第四開口60。可在第二介電層56中形成第三開口58以暴露出一部份的第一PPI 50，且可在第二介電層56中形成第四開口60以暴露出第二PPI 52。
第三開口58與第四開口60至少其中一者係形成於塑形化合物42上且對準塑形化合物42，而另一個開口則是形成於第二鈍化層30上並對準第二鈍化層30。第三開口58與第四開口60可用，例如，蝕刻、研磨、雷射技術、或前述之組合等方式形成。一些實施例中，可同時形成第三開口58 與第四開口60。
第11圖繪示出第一UBM 62與第二UBM 64的形成。可形成第一UBM 62以延伸至第三開口58中並與第一PPI 50電性接觸，而可形成第二UBM 64以延伸至第四開口60中並與第二PPI 52電性接觸。第一UBM 62與第二UBM 64可包括一或多層的導電材料。有多種適用於形成第一UBM 62與第二UBM 64的材料與層之合適排列，例如，鉻/鉻-銅合金/銅/金的排列、鈦/鈦-鎢合金/銅的排列、或銅/鎳/金的排列。形成光阻66並將其圖案化，以暴露出部份的第二介電層56，且覆蓋另一部份的第一介電層56。可進行一電鍍製程以將材料與層鍍於暴露出的部份第二介電層56，進而形成第一UBM 62與第二UBM 64，可使用任何合適的材料形成第一UBM 62與第二UBM 64。在完成電鍍製程後，可將光阻66移除。
第12圖繪示出分別與第一及第二UBM 62、64電性與物理接觸的第一連接器68與第二連接器70之形成。一實施例中，第一與第二連接器68、70可為C4凸塊(bump)、微凸塊(microbump)、焊球(solder ball)等，且第一與第二連接器68、70可包括一材料，例如，錫、銀、無鉛的錫、銅等、或前述之組合。如第13圖所示，在第一載體基底40上可有多個彼此相同的封裝體200。
如第14圖所示，在形成第一與第二連接器68、70後，多個封裝體200可從載體基底40脫離或移除。接著，可在多個封裝體200從載體基底40移除的一側上貼附或貼合塗層膠帶(coating tape)74。塗層膠帶74可提供保護與結構支撐 給其下的封裝體200。一些實施例中，可使用退火(annealing)製程貼附塗層膠帶74。
塗層膠帶74貼附於多個封裝體200後，可在多個封裝體200上進行功能測試(functional test)。可透過第一PPI 50與通過第一連接器68的第一UBM 62而對晶粒100進行功能測試，以查證連接性(connectivity)。亦可透過第二PPI 52與通過第二連接器70的第二UBM 64而對晶粒100進行功能測試，以查證連接性。此外，進行功能測試亦可同時查證封裝體200之某些功能。
在進行功能測試以後，接著，沿著切割線(scribe line)76將封裝體200切割成單一封裝體200。一些實施例中，可在切割期間使用切割黏晶膠帶(未顯示)。可藉由切削(cutting)製程或分割製程進行切割製程，其中可使用機械或雷射切刀以將多個封裝體200互相分離。
第15圖繪示出經過切割後的單一範例封裝體200。範例封裝體200包括晶粒100與至少一個設置在封裝體200之扇出部份(fan-out portion)的連接器元件。一些實施例中，封裝體200可包括至少一連接器元件位於晶粒100上方且對準晶粒100。如第15圖所示，接著層38位於晶粒100上方且對準於晶粒100，而塗層膠帶74位於整個封裝體200上且對準於整個封裝體200。雖然第15圖繪示出封裝體200僅有兩個連接器(第一與第二連接器68、70)，其他實施例可在封裝體200之扇出部份上具有多個連接器(參見第15圖的第二連接器70)，與在晶粒100上方具有多個與其對準的連接器(參見第15 圖的第一連接器68)。
藉由只在晶粒100上使用接著層38，將對封裝體200具有較佳的變形控制(warp control)，且晶粒100在第一載體基底40上具有較小的偏移(shift)。經測試發現，變形控制改善了將近60%。而且，亦晶粒100的厚度偏差(thickness variation)，這可使在研磨第一與第二金屬柱32、34時，能更準確地偵測研磨終點(grinding end point)。此外，在接著層38中僅需少量的接著材料以形成封裝體200，這可降低形成封裝體200的成本。
然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
200‧‧‧封裝體
20‧‧‧基底
22‧‧‧積體電路裝置
24‧‧‧第一接合墊
26‧‧‧第二接合墊
30‧‧‧第二鈍化層
32‧‧‧第一金屬柱
34‧‧‧第二金屬柱
38‧‧‧接著層
42‧‧‧塑形化合物
44‧‧‧第一介電層
50‧‧‧第一後鈍化內連線
52‧‧‧第二後鈍化內連線
56‧‧‧第二介電層
62‧‧‧第一底凸塊金屬層
64‧‧‧第二底凸塊金屬層
68‧‧‧第一連接器
70‧‧‧第二連接器
74‧‧‧塗層膠帶

Claims (10)

  1. 一種半導體裝置，包括：一半導體晶粒；一接著層，於該半導體晶粒之一第一側；一塑形化合物，圍繞該半導體晶粒與該接著層，其中該塑形化合物與該接著層齊平；一第一後鈍化內連線(post-passiviation interconnect,PPI)，電性連接至該半導體晶粒之一第二側；以及一第一連接器，電性連接至該第一PPI，其中該第一連接器位於該塑形化合物上並對準該塑形化合物。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該半導體晶粒更包括：一第一接合墊；一第一鈍化層，位於該接合墊與該第一PPI之間；以及一第一金屬柱，其中該金屬柱延伸穿過該第一鈍化層且將該第一接合墊電性連接至該第一鈍化層，其中該塑形化合物之一部分與該第一金屬柱齊平。
  3. 如申請專利範圍第1項所述之半導體裝置，更包括：一第二PPI，電性連接至該半導體晶粒的該第二側；以及一第二連接器，電性連接至該第二PPI，其中該第二連接器位於該半導體晶粒上且對準於該半導體晶粒。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括：一膠帶，貼附於該接著層與該塑形化合物。
  5. 一種半導體裝置的製造方法，包括： 形成一晶粒；以一接著層接附該晶粒於於一切割黏晶膠帶上；切割該晶粒；將該晶粒於該切割黏晶膠帶脫離；以該接著層將該晶粒接附於一載體，其中該接著層與該晶粒相接；以及以一聚合物將該晶粒塑形，其中該聚合物圍繞著(encircle)該晶粒與該接著層。
  6. 如申請專利範圍第5項所述之半導體裝置的製造方法，其中形成該晶粒的方法包括：形成一接合墊於一半導體基底上；形成一鈍化層於該接合墊與該半導體基底上方；形成一金屬柱於該接合墊上方，該金屬柱電性連接至該接合墊；薄化該晶粒與該聚合物以使該金屬柱、該鈍化層、與該聚合物齊平；形成一介電層於該晶粒與該聚合物上方；形成一開口於該介電層中，其中透過該開口暴露出該金屬柱；形成一PPI於該介電層上，該PPI透過該金屬柱而電性連接至該接合墊；形成一連接器於該聚合物上方，該連接器對準於該聚合物，其中該連接器電性連接至該PPI；形成延伸至該介電層中的該開口的一底凸塊金屬層；以及 形成一金屬凸塊於該底凸塊金屬層，其中該金屬凸塊透過該底凸塊金屬層電性連接至該PPI。
  7. 如申請專利範圍第5項所述之半導體裝置的製造方法，更包括：形成一連接器於該聚合物上方，該連接器對準於該聚合物，其中該連接器電性連接至該晶粒；將該晶粒從該載體脫離；接合一塗層膠帶於該晶粒的相反於該連接器的一側；以及切割該晶粒與連接器以形成該半導體裝置。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該塗層膠帶大抵上覆蓋該半導體裝置的一側，該側包括該接著層與該聚合物。
  9. 一種半導體裝置的製造方法，包括：形成多個晶粒於一基底上；以一膠層將該些晶粒貼附至一切割黏晶膠帶；切割該些晶粒；以該膠層貼附該些晶粒於一載體基底上，其中該些晶粒至少兩者與該載體基底之間的膠層為分離的，且其中該分離的膠層大抵上對準於該兩個晶粒；以及以一塑形化合物包覆(encapsulate)該些晶粒，其中一部份的塑形化合物係位於該兩個晶粒之間。
  10. 如申請專利範圍第9項所述之半導體裝置的製造方法，更包括：形成至少兩個接合墊於該基底上且於該兩個晶粒中； 形成一鈍化層於該兩個接合墊與基底上方；形成至少一個金屬柱於該兩個接合墊上且電性連接至該兩個接合墊，其中該至少一個金屬柱延伸穿過該鈍化層；研磨該塑形化合物與該些晶粒以暴露出該些金屬柱，其中該些金屬柱、該鈍化層、與該塑形化合物之頂表面齊平；形成多個連接器於該些晶粒與該塑形化合物上方，其中至少一個連接器透過一PPI電性連接至該至少一個金屬柱；將該些晶粒從該載體基底脫離；貼合一膠帶至該些晶粒，其中該將帶將分離的該些膠層與該塑形化合物相接；以及切割該些晶粒，其中被切割的該兩個晶粒包括該些連接器至少一者於該塑形化合物上且對準於該塑形化合物。
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