CN105514071A - 一种扇出型芯片的封装方法及封装结构 - Google Patents

一种扇出型芯片的封装方法及封装结构 Download PDF

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CN105514071A
CN105514071A CN201610046292.1A CN201610046292A CN105514071A CN 105514071 A CN105514071 A CN 105514071A CN 201610046292 A CN201610046292 A CN 201610046292A CN 105514071 A CN105514071 A CN 105514071A
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chip
fan
layer
projection
packing
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CN105514071B (zh
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仇月东
林正忠
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to US15/560,965 priority patent/US10593641B2/en
Priority to PCT/CN2016/082816 priority patent/WO2017124670A1/zh
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Priority to US16/780,167 priority patent/US10971467B2/en
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Abstract

本发明提供一种扇出型芯片的封装方法及封装结构，所述封装结构包括带凸块的第一芯片以及不带凸块的第二芯片，所述第二芯片表面形成有第一介质层，且所述第一介质层中制备有通孔；塑封材料；第二介质层；金属布线层，实现第一芯片以及第二芯片的电性引出，并实现第一芯片以及第二芯片之间的互连；凸块下金属层以及微凸点。本发明通过在带凸块的第一芯片以及不带凸块的第二芯片表面制作具有通孔的介质层，露出第一芯片的凸块以及露出第二芯片的金属焊盘，后续制作金属布线层实现第一芯片以及第二芯片的电性引出以及互连，以实现第一芯片及第二芯片的集成封装。

Description

一种扇出型芯片的封装方法及封装结构
技术领域
本发明涉及一种半导体芯片的封装方法及结构，特别是涉及一种扇出型芯片的封装方法及封装结构。
背景技术
随着集成电路制造业的快速发展，人们对集成电路的封装技术的要求也不断提高，现有的封装技术包括球栅阵列封装(BGA)、芯片尺寸封装(CSP)、圆片级封装(WLP)、三维封装(3D)和系统封装(SiP)等。其中，圆片级封装(WLP)由于其出色的优点逐渐被大部分的半导体制造者所采用，它的全部或大部分工艺步骤是在已完成前工序的硅圆片上完成的，最后将圆片直接切割成分离的独立器件。圆片级封装(WLP)具有其独特的优点：①封装加工效率高，可以多个圆片同时加工；②具有倒装芯片封装的优点，即轻、薄、短、小；③与前工序相比，只是增加了引脚重新布线(RDL)和凸点制作两个工序，其余全部是传统工艺；④减少了传统封装中的多次测试。因此世界上各大型IC封装公司纷纷投入这类WLP的研究、开发和生产。
在现有的扇出型芯片封装技术中，半导体芯片在切割后才会制作焊料凸块，这样，在生产过程中，可能遇到一些的异常问题，例如，如何封装预先形成有初始凸块的半导体芯片，或者如何实预先形成有初始凸块的芯片以及不带有初始凸块的芯片之间的互连。
现有技术中，如何对预先形成有初始凸块的芯片以及不带有初始凸块的芯片的集成封装以及如何实现其之间的互连，并没有十分良好有效的方法。
鉴于以上原因，提供一种能够有效实现带有初始凸块的半导体芯片以及不带有初始凸块的芯片的封装及互连的封装方法及封装结构实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种扇出型芯片的封装方法，用于提供一种能够有效实现带有初始凸块的半导体芯片以及不带有初始凸块的芯片的封装及互连的封装方法及封装结构。
为实现上述目的及其他相关目的，本发明提供一种扇出型芯片的封装方法，所述扇出型封装方法包括：步骤1)，提供带凸块的第一芯片以及不带凸块的第二芯片，于所述第二芯片表面形成第一介质层，并于所述第一介质层中制备出通孔；步骤2)，提供一表面形成有粘合层的载体，并将第一芯片及第二芯片粘合于所述粘合层；步骤3)，对第一芯片以及第二芯片进行封装，且封装后露出有第一芯片的凸块以及第二芯片表面第一介质层中的通孔；步骤4)，沉积覆盖第一芯片及第二芯片的第二介质层，于第一芯片的各凸块处以及第二芯片的通孔处打开窗口；步骤5)，基于所述窗口制作金属布线层，实现第一芯片以及第二芯片的电性引出，并实现第一芯片以及第二芯片之间的互连；步骤6)，于所述金属布线层上制作凸块下金属层以及微凸点。
作为本发明的扇出型芯片的封装方法的一种优选方案，还包括步骤7)，去除所述载体以及粘合层。
优选地，所述载体包括玻璃、透明半导体材料、以及透明聚合物中的一种。
优选地，所述粘合层包括UV粘合胶，步骤7)中，采用曝光方法使所述UV粘合胶降低黏性，以实现其与塑封材料的分离。
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤1)于所述第一介质层中制备出通孔后，还包括于所述第一介质层表面粘合胶带进行保护的步骤；步骤3)进行封装后，还包括将所述胶带去除的步骤。
作为本发明的扇出型芯片的封装方法的一种优选方案，所述第一介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。
作为本发明的扇出型芯片的封装方法的一种优选方案，采用旋涂法、化学气相衬底法或等离子增强化学气相沉积法于所述芯片表面形成介质层。
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤3)中，对第一芯片以及第二芯片进行封装后的塑封材料高度不超过各凸块以及第一介质层，以使各凸块以及第一介质层露出于塑封材料的表面。
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤3)中，对第一芯片以及第二芯片进行封装采用的塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤3)中，对第一芯片以及第二芯片进行封装采用的工艺包括：压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺以及旋涂工艺中的一种。
作为本发明的扇出型芯片的封装方法的一种优选方案，步骤5)中，采用蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺制作所述金属布线层。
作为本发明的扇出型芯片的封装方法的一种优选方案，所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。
作为本发明的扇出型芯片的封装方法的一种优选方案，所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。
本发明还提供一种扇出型芯片的封装结构，包括：带凸块的第一芯片以及不带凸块的第二芯片，所述第二芯片表面形成有第一介质层，且所述第一介质层中制备有通孔；塑封材料，填充于各第一芯片及第二芯片之间，所述塑封材料的高度不超过各凸块以及第一介质层的高度，以露出第一芯片的凸块以及第二芯片表面第一介质层中的通孔；第二介质层，覆盖于第一芯片及第二芯片，所述第二介质层于第一芯片的各凸块处以及第二芯片的通孔处具有窗口；金属布线层，填充于各窗口以及形成于所述第二介质层表面，实现第一芯片以及第二芯片的电性引出，并实现第一芯片以及第二芯片之间的互连；凸块下金属层以及微凸点，形成于所述金属布线层之上。
作为本发明的扇出型芯片的封装结构的一种优选方案，所述第一介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。
作为本发明的扇出型芯片的封装结构的一种优选方案，所述塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为本发明的扇出型芯片的封装结构的一种优选方案，所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。
作为本发明的扇出型芯片的封装结构的一种优选方案，所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种。
作为本发明的扇出型芯片的封装结构的一种优选方案，所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。
如上所述，本发明的扇出型芯片的封装方法及封装结构，具有以下有益效果：本发明通过在带凸块的第一芯片以及不带凸块的第二芯片表面制作具有通孔的介质层，露出第一芯片的凸块以及露出第二芯片的金属焊盘，后续制作金属布线层实现第一芯片以及第二芯片的电性引出以及互连，以实现第一芯片及第二芯片的集成封装。本发明提供了一种有效集成封装带凸块的第一芯片以及不带凸块的第二芯片的方法及结构，具有良好的效果，在半导体封装领域具有广泛的应用前景。
附图说明
图1～图13显示为本发明的扇出型芯片的封装方法各步骤所呈现的结构示意图，其中，图13显示为本发明的扇出型芯片的封装结构的结构示意图。
元件标号说明
101第二芯片
102金属焊盘
103第一介质层
104胶带
201第一芯片
202金属焊盘
203凸块
301载体
302粘合层
303塑封材料
304第二介质层
305金属布线层
306凸块下金属
307微凸点
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图13。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1～图13所示，本实施例提供一种扇出型芯片的封装方法，所述扇出型封装方法包括：
如图1～图5所示，首先进行步骤1)，提供带凸块203的第一芯片201以及不带凸块203的第二芯片101，于所述第二芯片101表面形成第一介质层103，并于所述第一介质层103中制备出通孔。
作为示例，所述凸块203制作于第一芯片201的金属焊盘202上
作为示例，所述第一介质层103包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。
作为示例，采用旋涂法、化学气相衬底法或等离子增强化学气相沉积法于所述芯片表面形成介质层。
在本实施例中，包括步骤：
如图1～图2所示，首先进行步骤1-1)，提供不带凸块203的第二芯片101的晶圆，采用等离子增强化学气相沉积法于晶圆形成二氧化硅层，作为第一介质层103；
如图3所示，然后进行步骤1-2)，采用光刻-刻蚀工艺于所述二氧化硅层中制备出通孔，所述通孔内露出有第二芯片101的金属焊盘102；
如图4所示，接着进行步骤1-3)，于所述第一介质层103(二氧化硅层)表面粘合胶带104进行保护；
如图5所示，最后进行步骤1-4)，对所述晶圆进行裂片获得独立的第二芯片101。
如图6所示，然后进行步骤2)，提供一表面形成有粘合层302的载体301，并将第一芯片201及第二芯片101粘合于所述粘合层302。
作为示例，所述粘合层302可以为如胶带104、通过旋涂形成的UV粘合胶或者环氧树脂等材料，在本实施例中，所述粘合层302为通过旋涂形成的UV粘合胶，该UV粘合胶在紫外光照射下黏性会降低。
作为示例，所述载体301可以为玻璃、陶瓷、金属、聚合物等材料，在本实施例中，所述载体301包括玻璃、透明半导体材料、以及透明聚合物中的一种，以使得后续可以从载体301的背面对上述的UV粘合胶进行曝光操作，大大简化后续的剥离工艺。
如图7～图8所示，接着进行步骤3)，对第一芯片201以及第二芯片101进行封装，且封装后露出有第一芯片201的凸块203以及第二芯片101表面第一介质层103中的通孔，进行封装后，通过撕除的方法将所述胶带104去除。
作为示例，对第一芯片201以及第二芯片101进行封装后的塑封材料303高度不超过各凸块203以及第一介质层103，以使各凸块203以及第一介质层103露出于塑封材料303的表面。
作为示例，对第一芯片201以及第二芯片101进行封装采用的塑封材料303包括聚酰亚胺、硅胶以及环氧树脂中的一种。其中，所述塑封材料303添通过添加剂而形成不透光材料。
作为示例，对第一芯片201以及第二芯片101进行封装采用的工艺包括：压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺以及旋涂工艺中的一种。在本实施例中，通过注塑工艺对第一芯片201以及第二芯片101进行封装，所述塑封材料303为不透光的硅胶。
如图9～图10所示，接着进行步骤4)，沉积覆盖第一芯片201及第二芯片101的第二介质层304，于第一芯片201的各凸块203处以及第二芯片101的通孔处打开窗口。
作为示例，所述第二介质层304为采用等离子增强化学气相沉积法形成二氧化硅层，并采用光刻-刻蚀工艺第一芯片201的各凸块203处以及第二芯片101的通孔处打开窗口。当然，可以依据需求同时在第二介质层304中刻蚀出所需的布线形状，以便于后续金属布线层305的制备。
如图11所示，接着进行步骤5)，基于所述窗口制作金属布线层305，实现第一芯片201以及第二芯片101的电性引出，并实现第一芯片201以及第二芯片101之间的互连。
作为示例，所述金属布线层305具体包括两部分，第一部分用于第一芯片201以及第二芯片101的电性引出，第二部分用于第一芯片201以及第二芯片101之间的互连。
作为示例，采用蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺制作所述金属布线层305。
作为示例，所述金属布线层305的材料包括铝、铜、锡、镍、金及银中的一种。
如图12所示，然后进行步骤6)，于所述金属布线层305上制作凸块下金属306层以及微凸点307。
作为示例，所述微凸点307包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述微凸点307包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。
在本实施例中，所述微凸点307为金锡焊球，其制作包括步骤：首先于所述凸块下金属306层表面形成金锡层，然后采用高温回流工艺使所述金锡层回流成球状，降温后形成金锡焊球。
如图13所示，最后进行步骤7)，去除所述载体301以及粘合层302。
作为示例，所述载体301包括玻璃、透明半导体材料、以及透明聚合物中的一种。
作为示例，所述粘合层302为UV粘合胶，步骤7)中，采用曝光方法使所述UV粘合胶降低黏性，以实现其与塑封材料303的分离。
如图13所示，本实施例还提供一种扇出型芯片的封装结构，包括：带凸块203的第一芯片201以及不带凸块203的第二芯片101，所述第二芯片101表面形成有第一介质层103，且所述第一介质层103中制备有通孔；塑封材料303，填充于各第一芯片201及第二芯片101之间，所述塑封材料303的高度不超过各凸块203以及第一介质层103的高度，以露出第一芯片201的凸块203以及第二芯片101表面第一介质层103中的通孔；第二介质层304，覆盖于第一芯片201及第二芯片101，所述第二介质层304于第一芯片201的各凸块203处以及第二芯片101的通孔处具有窗口；金属布线层305，填充于各窗口以及形成于所述第二介质层304表面，实现第一芯片201以及第二芯片101的电性引出，并实现第一芯片201以及第二芯片101之间的互连；凸块下金属306层以及微凸点307，形成于所述金属布线层305之上。
作为示例，所述第一介质层103包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。
作为示例，所述塑封材料303包括聚酰亚胺、硅胶以及环氧树脂中的一种。
作为示例，所述金属布线层305的材料包括铝、铜、锡、镍、金及银中的一种。
作为示例，所述微凸点307包括金锡焊球、银锡焊球、铜锡焊球中的一种。
作为示例，所述微凸点307包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。
如上所述，本发明的扇出型芯片的封装方法及封装结构，具有以下有益效果：本发明通过在带凸块203的第一芯片201以及不带凸块203的第二芯片101表面制作具有通孔的介质层，露出第一芯片201的凸块203金属焊盘以及露出第二芯片101的金属焊盘，后续制作金属布线层305实现第一芯片201以及第二芯片101的电性引出以及互连，以实现第一芯片201及第二芯片101的集成封装。本发明提供了一种有效集成封装带凸块203的第一芯片201以及不带凸块203的第二芯片101的方法及结构，具有良好的效果，在半导体封装领域具有广泛的应用前景。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (19)

1.一种扇出型芯片的封装方法，其特征在于，所述扇出型封装方法包括：
步骤1)，提供带凸块的第一芯片以及不带凸块的第二芯片，于所述第二芯片表面形成第一介质层，并于所述第一介质层中制备出通孔；
步骤2)，提供一表面形成有粘合层的载体，并将第一芯片及第二芯片粘合于所述粘合层；
步骤3)，对第一芯片以及第二芯片进行封装，且封装后露出有第一芯片的凸块以及第二芯片表面第一介质层中的通孔；
步骤4)，沉积覆盖第一芯片及第二芯片的第二介质层，于第一芯片的各凸块处以及第二芯片的通孔处打开窗口；
步骤5)，基于所述窗口制作金属布线层，实现第一芯片以及第二芯片的电性引出，并实现第一芯片以及第二芯片之间的互连；
步骤6)，于所述金属布线层上制作凸块下金属层以及微凸点。
2.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：还包括步骤7)，去除所述载体以及粘合层。
3.根据权利要求2所述的扇出型芯片的封装方法，其特征在于：所述载体包括玻璃、透明半导体材料、以及透明聚合物中的一种。
4.根据权利要求3所述的扇出型芯片的封装方法，其特征在于：所述粘合层包括UV粘合胶，步骤7)中，采用曝光方法使所述UV粘合胶降低黏性，以实现其与塑封材料的分离。
5.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤1)于所述第一介质层中制备出通孔后，还包括于所述第一介质层表面粘合胶带进行保护的步骤；步骤3)进行封装后，还包括将所述胶带去除的步骤。
6.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：所述第一介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。
7.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：采用旋涂法、化学气相衬底法或等离子增强化学气相沉积法于所述芯片表面形成介质层。
8.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤3)中，对第一芯片以及第二芯片进行封装后的塑封材料高度不超过各凸块以及第一介质层，以使各凸块以及第一介质层露出于塑封材料的表面。
9.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤3)中，对第一芯片以及第二芯片进行封装采用的塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
10.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤3)中，对第一芯片以及第二芯片进行封装采用的工艺包括：压缩成型工艺、印刷工艺、传递模塑工艺、液体密封剂固化成型工艺、真空层压工艺以及旋涂工艺中的一种。
11.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：步骤5)中，采用蒸镀工艺、溅射工艺、电镀工艺或化学镀工艺制作所述金属布线层。
12.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。
13.根据权利要求1所述的扇出型芯片的封装方法，其特征在于：所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种，或者，所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。
14.一种扇出型芯片的封装结构，其特征在于，包括：
带凸块的第一芯片以及不带凸块的第二芯片，所述第二芯片表面形成有第一介质层，且所述第一介质层中制备有通孔；
塑封材料，填充于各第一芯片及第二芯片之间，所述塑封材料的高度不超过各凸块以及第一介质层的高度，以露出第一芯片的凸块以及第二芯片表面第一介质层中的通孔；
第二介质层，覆盖于第一芯片及第二芯片，所述第二介质层于第一芯片的各凸块处以及第二芯片的通孔处具有窗口；
金属布线层，填充于各窗口以及形成于所述第二介质层表面，实现第一芯片以及第二芯片的电性引出，并实现第一芯片以及第二芯片之间的互连；
凸块下金属层以及微凸点，形成于所述金属布线层之上。
15.根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述第一介质层包括二氧化硅、磷硅玻璃、碳氧化硅、碳化硅、以及聚合物中的一种。
16.根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述塑封材料包括聚酰亚胺、硅胶以及环氧树脂中的一种。
17.根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述金属布线层的材料包括铝、铜、锡、镍、金及银中的一种。
18.根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述微凸点包括金锡焊球、银锡焊球、铜锡焊球中的一种。
19.根据权利要求14所述的扇出型芯片的封装结构，其特征在于：所述微凸点包括铜柱，形成于铜柱上的镍层、以及形成于所述镍层上的焊球。
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