WO2022165854A1 - 一种芯片互连封装结构及方法 - Google Patents

一种芯片互连封装结构及方法 Download PDF

Info

Publication number
WO2022165854A1
WO2022165854A1 PCT/CN2021/076104 CN2021076104W WO2022165854A1 WO 2022165854 A1 WO2022165854 A1 WO 2022165854A1 CN 2021076104 W CN2021076104 W CN 2021076104W WO 2022165854 A1 WO2022165854 A1 WO 2022165854A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
interconnection
pattern
packaging
sacrificial
Prior art date
Application number
PCT/CN2021/076104
Other languages
English (en)
French (fr)
Inventor
王垚
李子白
凌云志
向迅
崔银花
胡川
陈志涛
Original Assignee
广东省科学院半导体研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 广东省科学院半导体研究所 filed Critical 广东省科学院半导体研究所
Priority to US17/434,480 priority Critical patent/US20220254651A1/en
Priority to CN202180001243.5A priority patent/CN113169075B/zh
Priority to PCT/CN2021/076104 priority patent/WO2022165854A1/zh
Publication of WO2022165854A1 publication Critical patent/WO2022165854A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/485—Adaptation of interconnections, e.g. engineering charges, repair techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/211—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

Definitions

  • the present application relates to the technical field of semiconductor packaging, and in particular, to a chip interconnect packaging structure and method.
  • the purpose of the present application is to provide a chip interconnect packaging structure and method in view of the above-mentioned deficiencies in the prior art, so as to improve the problem of manufacturing precision of the existing multi-chips during short-distance interconnection, and it is impossible to manufacture finer interconnects. Connection line problem.
  • a chip interconnect packaging method includes: forming a sacrificial pattern layer on one side surface of a support structure; forming an interconnection wiring pattern layer on the sacrificial pattern layer, and interconnecting the wiring pattern
  • the winding pattern of the layer corresponds to the sacrificial pattern position of the sacrificial pattern layer; a first insulating layer is formed on the interconnecting winding pattern layer; a plurality of chips arranged at intervals are formed on the first insulating layer, and the plurality of chips are respectively interconnected with
  • the positions of the interconnecting routing patterns of the routing pattern layer correspond; the support structure is removed, and a first interconnection hole penetrating the sacrificial pattern, the interconnecting routing pattern and the first insulating layer is formed on one side of the sacrificial pattern layer, and the first interconnection The hole is also in alignment and communication with the first interconnection pin of the chip corresponding to the projection position.
  • a first interconnection hole is formed on one side of the sacrificial pattern layer penetrating the sacrificial pattern, the interconnection wiring pattern and the first insulating layer, and the first interconnection hole is also connected to the first interconnection of the chip corresponding to the projection position.
  • the method further includes: forming a conductive material in the first interconnection hole, and the conductive material in the first interconnection hole is electrically connected to the interconnection routing pattern and the first interconnection pin of the chip.
  • the line width of the interconnecting wiring pattern is 0.5 micrometers to 2 micrometers
  • the line spacing of the interconnecting wiring patterns is 0.5 micrometers to 2 micrometers.
  • the method further includes: forming a plastic encapsulation body on the plurality of chips.
  • a first interconnection hole is formed on one side of the sacrificial pattern layer penetrating the sacrificial pattern, the interconnection wiring pattern and the first insulating layer, and the first interconnection hole is also connected to the first interconnection of the chip corresponding to the projection position.
  • the method further includes: removing the sacrificial pattern layer, or removing the sacrificial metal layer when the sacrificial pattern layer includes an insulating sacrificial layer and a metal sacrificial layer sequentially disposed on the interconnecting wire pattern layer.
  • the method further includes: A first package winding layer is formed on the side of the winding pattern layer away from the chip; a second interconnection hole penetrating the first package winding layer is formed on the side of the first package winding layer, and the second interconnection hole is also connected with the projection.
  • the interconnection routing pattern corresponding to the position is connected in position.
  • the method further includes: further forming a third interconnection penetrating the first packaging wiring layer on the side of the first packaging wiring layer.
  • the third interconnection hole is also connected with the second interconnection pin of the chip corresponding to the projection position.
  • forming the first package wiring layer on the side of the interconnect wiring pattern layer away from the chip includes: forming a second insulating layer on the side of the interconnect wiring pattern layer away from the chip, and forming the second insulating layer on the side of the interconnect wiring pattern layer away from the chip.
  • a first packaging wiring pattern layer is formed on one side, and the first packaging wiring pattern of the first packaging wiring pattern layer corresponds to the position of the interconnect wiring pattern.
  • a second interconnection hole penetrating the first packaged winding layer is formed on one side of the first packaged winding layer, and after the second interconnected hole is also aligned and connected with the winding pattern corresponding to the projected position, the method further includes: The method includes: forming a second packaging wire layer on the side of the first packaging wire layer away from the chip; forming a fourth interconnection hole penetrating the second packaging wire layer on the side of the second packaging wire layer, and the fourth The interconnection hole is also in alignment and communication with the first package winding layer corresponding to the projected position.
  • forming the second packaging wiring layer on the side of the first packaging wiring layer away from the chip includes: forming a third insulating layer on the side of the first packaging wiring layer away from the chip; A second package wiring pattern layer is formed on the side away from the chip.
  • the line width of the interconnecting wiring pattern is smaller than the line width of the first packaging wiring pattern of the first packaging wiring pattern layer; the line spacing of the interconnecting wiring pattern is smaller than that of the first packaging wiring pattern layer.
  • the pitch of the package winding pattern is smaller than the line width of the first packaging wiring pattern of the first packaging wiring pattern layer.
  • the line width of the first packaging wiring pattern of the first packaging wiring pattern layer is 2 micrometers to 5 micrometers, and the line spacing of the first packaging wiring pattern of the first packaging wiring pattern layer is 2 micrometers to 5 micrometers. microns.
  • the line width of the second packaging wiring pattern of the second packaging wiring pattern layer is greater than 5 microns.
  • Another aspect of the embodiments of the present application provides a chip interconnect packaging structure prepared by using any of the above-mentioned chip interconnect packaging methods, including: sequentially arranging an interconnection winding pattern layer and a plurality of chips on a sacrificial pattern layer ;
  • the wiring pattern of the interconnection winding pattern layer corresponds to the position of the sacrificial pattern of the sacrificial pattern layer, and a plurality of chips are correspondingly arranged on the interconnection winding pattern of the interconnection winding pattern layer; open on one side of the sacrificial pattern layer
  • the first interconnection hole penetrates the sacrificial pattern and the interconnection routing pattern, and the first interconnection hole is also in alignment and communication with the first interconnection pin of the chip corresponding to the projection position.
  • a chip interconnect package structure is provided, which is prepared by applying any one of the above chip interconnect package structures.
  • the present application provides a chip interconnect packaging method.
  • a sacrificial pattern layer is formed on one side surface of a support structure; an interconnection winding pattern layer is formed on the sacrificial pattern layer, and the wiring pattern of the interconnection winding pattern layer and the sacrificial pattern are interconnected.
  • the positions of the sacrificial patterns of the layers correspond to each other; a first insulating layer is formed on the interconnection winding pattern layer; a plurality of chips arranged at intervals are formed on the first insulating layer, and the plurality of chips are respectively connected to the interconnections of the interconnection winding pattern layer.
  • the position of the line pattern corresponds; the support structure is removed, and a first interconnection hole is formed on one side of the sacrificial pattern layer that penetrates the sacrificial pattern, the interconnection winding pattern and the first insulating layer, and the first interconnection hole is also corresponding to the projection position of the chip.
  • the first interconnection pins are connected to each other.
  • the present application provides a chip interconnect packaging structure, through the arrangement of the sacrificial pattern layer, the opening positions of multiple chip interconnects can be assisted to define, and then after the interconnect winding pattern layer and the chip are formed in sequence, it can be The position of the openings in the sacrificial pattern precisely realizes the interconnection between the multiple chips.
  • FIG. 1 is a schematic flowchart of a chip interconnect packaging method provided by an embodiment of the present application
  • FIG. 2 is one of the schematic structural diagrams of a chip interconnect packaging structure provided by an embodiment of the present application
  • FIG. 3 is a second structural schematic diagram of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 4 is a top view of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 5 is one of the schematic structural diagrams of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 6 is a third schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 7 is a fourth schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 8 is a fifth schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 9 is a sixth schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the present application.
  • FIG. 10 is a second schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the application.
  • FIG. 11 is a seventh schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the application.
  • FIG. 12 is an eighth schematic structural diagram of a chip interconnect packaging structure provided by an embodiment of the present application.
  • Icon 010-chip; 020-plastic body; 011-first interconnection pin; 012-second interconnection pin; 101-first insulating layer; 102-first interconnection hole; 103-interconnection wire pattern layer; 104-sacrificial layer; 104a-metal sacrificial layer; 104b-insulation sacrificial layer; 201-second insulating layer; 202-second interconnection hole; 203-first package winding pattern layer; 204-third interconnection 301-the third insulating layer; 302-the fourth interconnection hole; 303-the second package wiring pattern layer; 401-solder resist layer; 402-solder ball; 001-temporary support layer; ; 003 - Support structure.
  • a chip interconnect packaging method is provided.
  • the method may include:
  • a support structure 003 is provided, and a sacrificial pattern layer is formed on one surface of the support structure 003 , that is, the sacrificial pattern layer is formed under the support structure 003 in FIG. 2 .
  • the sacrificial pattern layer may be a hierarchical structure formed by first forming an entire sacrificial layer 104 on the surface of the support structure 003 , and then performing a patterning process on the entire sacrificial layer 104 .
  • the patterning of the sacrificial layer 104 can be set according to the position of the first interconnection hole 102 to be formed later (hereinafter referred to as the opening position), that is, the sacrificial pattern in the sacrificial pattern layer includes at least one first interconnection hole 102. formation position, such as two or more opening positions.
  • the interconnection wiring pattern layer 103 is continuously formed on the sacrificial pattern layer.
  • the wiring layer, and then the layered structure is formed after the patterning process is performed on the interconnecting wiring layer of the entire layer.
  • the interconnection winding pattern layer 103 may be formed in a manner corresponding to the position of the sacrificial pattern layer, that is, after the interconnection winding layer is patterned, the interconnection winding pattern of the interconnection winding pattern layer 103 and the sacrificial pattern layer 103 are formed.
  • the positions of the sacrificial patterns of the pattern layer correspond to each other, for example, the pins in the interconnect routing pattern and the positions of the openings in the sacrificial patterns are in one-to-one correspondence.
  • a first insulating layer 101 is first formed on the interconnection winding pattern layer 103; then a plurality of chips 010 are formed on the first insulating layer 101, and the plurality of chips 010 are arranged in a spaced manner from each other. Mutual interference between multiple chips 010 is effectively avoided. Meanwhile, the first insulating layer 101 should be located between the interconnect wiring pattern layer 103 and the chip 010 layer.
  • the first insulating layer 101 can be an insulating material or an anisotropic conductive material to form an adhesive layer with an adhesive function. At this time, when multiple chips 010 are formed on the first insulating layer 101, the multiple chips 010 can be precisely aligned
  • the interconnecting wiring pattern layer 103 is adhered and disposed on the first insulating layer 101 . In order to further improve the stability of the bonding, curing treatment can be performed on the structure after the bonding is completed.
  • a plurality of chips 010 are continuously formed on the first insulating layer 101 , and the plurality of chips 010 may be arranged on the same layer with a certain interval.
  • the plurality of chips 010 respectively correspond to the interconnection winding patterns, so that the first interconnection pins 011 in the plurality of chips 010 correspond to the pins in the interconnection winding pattern, and the above-mentioned correspondence may be along the vertical support structure 003.
  • the correspondence of directions that is, the orthographic projection positions of the corresponding two in the same plane parallel to the plane of the support structure 003 are aligned.
  • the first interconnection pins 011 on the surface of the chip 010 , the pin patterns of the interconnection winding pattern layer 103 and the positions of the openings on the surface of the sacrificial layer 104 are in a one-to-one correspondence, that is, the above three structures Corresponding in the direction perpendicular to the temporary support layer 001 , that is, the orthographic projections of the two corresponding ones in the same plane parallel to the plane of the temporary support layer 001 partially or completely overlap.
  • S050 Remove the support structure, and form a first interconnection hole on one side of the sacrificial pattern layer that penetrates the sacrificial pattern, the interconnection wiring pattern and the first insulating layer, and the first interconnection hole also corresponds to the first interconnection hole of the chip corresponding to the projection position.
  • the interconnect pins are connected to each other.
  • the support structure 003 is removed, and then a first interconnection hole 102 is formed on one side of the sacrificial pattern layer according to the position of the opening in the sacrificial pattern, and the first interconnection hole 102 sequentially penetrates the sacrificial pattern layer.
  • pattern, the interconnection routing pattern and the first insulating layer 101, and at the same time, the first interconnection hole 102 also extends to the chip 010.
  • the interconnection The pins in the winding pattern correspond to the first interconnect pins 011 of the chip 010, so the first interconnect pins 011 of the chip 010 and the opening positions in the sacrificial pattern at least partially overlap at the projected positions of the chip 010,
  • the first interconnection hole 102 extends to the chip 010 , it can connect the pins in the interconnection routing pattern with the first interconnection pin 011 of the chip 010 , so as to realize the chip 010 and the interconnection routing pattern layer 103 After the multiple chips 010 are accurately connected to the interconnection winding pattern layer 103, the interconnection between the multiple chips 010 is realized.
  • the sacrificial pattern layer Through the arrangement of the sacrificial pattern layer, it is possible to assist in defining the opening positions of the interconnection of multiple chips 010, and then after the interconnection winding pattern layer 103 and the chip 010 are formed in sequence, it can be accurately realized according to the opening positions in the sacrificial pattern.
  • the interconnection among the plurality of chips 010 is interconnected. First, the structure design and process fabrication of the sacrificial pattern layer and the interconnection winding pattern layer 103 are carried out, and then the chip 010 and the interconnection winding pattern layer 103 are mounted, and then the vertical interconnection structure is formed, and the sacrificial pattern layer is removed. Then the construction of the subsequent fan-out package winding layer is carried out.
  • the sacrificial pattern in the sacrificial pattern layer can not only define the position of the first interconnection hole 102, but also define the aperture size thereof.
  • the interconnection routing pattern of the interconnection routing pattern layer 103 may include a plurality of interconnection lines, and each interconnection line may have two pins, which are respectively connected to the two chips 010 that are interconnected.
  • One of the first interconnect pins 011 corresponds to one of the first interconnect pins 011, and then through the connection of the first interconnect holes 102, the preliminary connection of the two chips 010 is realized, which is schematically shown on the sacrificial pattern layer as shown in FIG. 4 .
  • part of the three interconnecting lines, the end of the three lines and the first interconnection pin 011 of one of the interconnecting chips 010 are correspondingly overlapped or partially overlapped up and down, and pass through the first interconnection hole of the end.
  • the interconnection pins are correspondingly overlapped up and down or partially overlapped, and are connected through the first interconnection hole 102 at the other end of the interconnection line.
  • the first interconnection pins 011 may be high-density interconnection pins in the chip 010
  • the interconnection winding pattern layer 103 may also correspond to a fine line winding layer.
  • the assisted positioning of the sacrificial pattern layer can improve the precision of fine interconnection among the multi-chip 010, thereby increasing the bandwidth of data transmission.
  • the support structure 003 acts as a temporary support, and its material can be one or more of silicon, silicon dioxide, glass, laser release material, thermal release material, etc.
  • the support structure 003 includes a temporary support layer 001 (silicon, silicon dioxide, glass, etc.) and a releasable layer 002 (laser release material, thermal release material, etc.), which can be removed after removing the releasable layer 002 to expose the sacrificial pattern layer
  • the surface of the sacrificial pattern layer is removed, it is carried out by releasing and removing, so as to reduce the influence on the sacrificial pattern layer, thereby improving the precision of forming the first interconnection hole 102 in the sacrificial pattern layer; in another embodiment, as shown in FIG.
  • the supporting Structure 003 includes temporary support layer 001 .
  • the support structure 003 may be removed by wet etching, dry etching, laser release removal, thermal release removal, and the like. When selecting the removal method, it can be adaptively selected according to the material of the support structure 003, which is not limited in this application.
  • the material of the sacrificial pattern layer can be metal, polyimide (Polyimide), benzocyclobutene (BCB), parylene, industrial liquid crystal polymer (LCP), epoxy resin, silicon oxide, silicon One or more of nitrides, aluminum oxides, and the like.
  • the sacrificial pattern layer includes a metal sacrificial layer 104a and an insulating sacrificial layer 104b, and the insulating sacrificial layer 104b should be located between the metal sacrificial layer 104a and the interconnection wiring pattern layer 103;
  • the sacrificial pattern layer may also be an insulating sacrificial layer 104b.
  • a first interconnection hole 102 penetrating the sacrificial pattern, the interconnection wiring pattern and the first insulating layer 10 is formed on one side of the sacrificial pattern layer, and the first interconnection hole 102 also corresponds to the projection position of the chip 010.
  • the method further includes: forming a conductive material in the first interconnection hole 102 , and the conductive material in the first interconnection hole 102 interconnects the wiring pattern and the first interconnection of the chip 010 .
  • the interconnect pin 011 is electrically connected.
  • the first interconnection hole 102 in order to realize the electrical connectability of the first interconnection pin 011 and the interconnection lines in the interconnection winding pattern layer 103, the first interconnection hole A conductive material is formed in 102, and the first interconnection pin 011 and the interconnection lines in the interconnection winding pattern layer 103 are connected by the conductive material to form a conductive electrical connection structure, thereby realizing the chip 010 and the interconnection winding.
  • the pattern layer 103 is electrically connected, so that the interconnected chips 010 can be interconnected through the interconnecting wire pattern layer 103, thereby transmitting data and the like.
  • the line width of the interconnecting wiring pattern is 0.5 micrometers to 2 micrometers
  • the line spacing of the interconnecting wiring patterns is 0.5 micrometers to 2 micrometers.
  • the line width of the interconnection wiring pattern may be the line width of the interconnection lines in the interconnection wiring pattern, and the setting range may be 0.5 micrometers to 2 micrometers (including 0.5 micrometers and 2 micrometers);
  • the line spacing of the line pattern can be the spacing between two adjacent interconnecting lines in the interconnection wiring pattern, and its setting range can be 0.5 micrometers to 2 micrometers (including 0.5 micrometers and 2 micrometers), so as to ensure multi-chip While the 010 interconnection is stable, the bandwidth of the chip 010 data transmission is improved.
  • a plastic packaging body 020 may also be formed on the plurality of chips 010 , and the plastic packaging body 020 may be formed of an encapsulating material.
  • the plastic package 020 completely covers the plurality of chips 010 , that is, covers all the sidewalls except the side where the chips 010 and the first insulating layer 101 are attached, so as to improve the stability of the chips 010 .
  • the plastic package 020 may be formed on the plurality of chips 010 first, and then the support structure 003 is removed, and subsequent process steps are performed.
  • a first interconnection hole 102 penetrating the sacrificial pattern and interconnecting the first insulating layer 101 of the wiring pattern is formed on one side of the sacrificial pattern layer, and the first interconnection hole 102 is also the first interconnection hole 102 corresponding to the projection position.
  • the method further includes: removing the sacrificial pattern layer, or, when the sacrificial pattern layer includes the insulating sacrificial layer 104b and the metal sacrificial layer 104a sequentially disposed on the interconnecting wire pattern layer, removing Metal sacrificial layer 104a.
  • the sacrificial pattern layer on the interconnection wiring pattern layer 103 may be partially removed or completely removed. Removed, it can be illustrated by the following two embodiments:
  • the sacrificial pattern layer on the interconnection winding pattern layer 103 is completely removed, and then the first layer is directly formed on the surface of the interconnection winding pattern layer 103 through subsequent embodiments.
  • the first packaging winding pattern in the first packaging winding layer is aligned up and down with the interconnecting wiring pattern.
  • the second interconnection hole 202 penetrates the first package wiring layer and extends to the surface of the interconnection wiring pattern layer 103 .
  • the part of the sacrificial pattern layer located on the interconnection wiring pattern layer 103 is removed, that is, when the sacrificial pattern layer includes insulation located on the interconnection wiring pattern layer 103
  • the metal sacrificial layer 104a can be removed, the insulating sacrificial layer 104b can be retained, and part of the insulating sacrificial layer 104b can also be retained. Then, a first package is formed on the surface of the remaining sacrificial pattern layer through subsequent embodiments.
  • the first packaging wiring pattern in the first packaging wiring layer is aligned up and down with the interconnecting wiring pattern.
  • the second interconnect hole 202 penetrates the first package wire layer and the remaining sacrificial pattern layers (eg, the insulating sacrificial layer 104b in FIG. 11 ) in sequence and extends to the interconnect wire The surface of the pattern layer 103 .
  • the manner of removing the sacrificial pattern layer may include at least one of wet etching, dry etching, mechanical polishing, chemical mechanical polishing, and the like.
  • the method further includes: 103 A first package winding layer is formed on the side away from the chip 010; a second interconnection hole 202 penetrating the first package winding layer is formed on the side of the first package winding layer, and the second interconnection hole 202 is also connected with the projection.
  • the interconnection routing pattern corresponding to the position is connected in position.
  • a first The packaging winding layer that is, the first packaging wiring layer is formed on the side of the interconnecting wiring pattern layer 103 away from the chip 010. As shown in FIG. 7 or FIG. 9, the first packaging is formed above the interconnecting wiring pattern layer 103. winding layer.
  • part of the pins in the first package wiring pattern of the first package wiring layer as shown in FIG. 7 or FIG.
  • a penetrating second interconnection hole 202 may also be formed on the first package wiring layer, so that the first package wiring layer on the first package wiring layer is connected. The pins in the package routing pattern communicate with the pins in the interconnect routing pattern.
  • the conductive material in the first interconnection hole 102, can be continuously formed in the second interconnection hole 202, so that the pins in the interconnection routing pattern can be wound with the first package.
  • the pins in the first package wire pattern in the wire layer form an electrical connection structure.
  • the method further includes: if it is also necessary to make the first packaging wire layer and the chip 010 communicate with each other, the method may also be performed after forming the first packaging wire layer.
  • the wiring layer is used, the pins in the first packaging wiring pattern in the first packaging wiring layer (as shown in FIG. 7 or FIG. 11 on the outermost pin of the first packaging wiring layer pattern layer)
  • the second interconnection pins 012 are aligned up and down. As shown in FIG. 7 or FIG.
  • a third interconnection hole 204 penetrating the first package winding layer is also formed on one side of the first package winding layer, and the third interconnection hole 204 is also formed with the chip 010 corresponding to the projected position.
  • the second interconnection pins 012 of the first package wiring layer are aligned and connected, so as to realize the communication between the first package wiring layer pattern layer in the first package wiring layer and the chip 010 .
  • the second interconnection pins 012 may be low-density interconnection pins in the chip 010 .
  • the third interconnection hole 204 may be further formed, and the third interconnection hole 204 will penetrate the first package winding layer and the interconnection winding in turn.
  • the pattern layer 103 (there is no lead at the penetration position of the third interconnection hole 204 ) and the first insulating layer 101 extend to the surface of the chip 010 .
  • the second interconnection hole 202 and the third interconnection hole 204 are in the same embodiment, they may be formed in the same process, or may be formed successively, which are not specifically limited in this application.
  • the third interconnection hole 204 may be further formed, and the third interconnection hole 204 will penetrate the first package winding layer and the remaining sacrificial pattern layer in turn. (eg the insulating sacrificial layer 104b in FIG. 11 ), the interconnecting wiring pattern layer 103 (there is no lead at the penetration position of the third interconnection hole 204 ) and the first insulating layer 101 and extend to the surface of the chip 010 .
  • forming the first package wiring layer on the side of the interconnect wiring pattern layer away from the chip 010 includes: as shown in FIG. 7 or FIG. 11 , forming the first package wiring layer on the side of the interconnect wiring pattern layer 103 away from the chip 010 .
  • the second insulating layer 201 forms the first packaging wiring pattern layer 203 on the side of the second insulating layer 201 away from the chip 010 , that is, the second insulating layer 201 is formed on the first packaging wiring pattern layer 203 and the interconnect wiring pattern layer 103 structure in between.
  • the first encapsulation routing pattern of the first encapsulation routing pattern layer 203 corresponds to the position of the interconnect routing pattern (that is, the pins connected to the two correspond to each other).
  • the first packaging wiring pattern of the packaging wiring pattern layer 203 also corresponds to the position of the chip 010 (ie, the pins connected to the two correspond to each other), and the third interconnection holes 204 pass through the first packaging wiring layer in turn.
  • the first package wiring pattern layer 203 and the second insulating layer 201 corresponds to the position of the chip 010 (ie, the pins connected to the two correspond to each other), and the third interconnection holes 204 pass through the first packaging wiring layer in turn.
  • the support structure 003 may select a glass carrier plate as the temporary support layer 001 , and laser release material as the releasable layer 002
  • the sacrificial pattern layer may be a metal sacrificial layer 104a and an insulating sacrificial layer 104b, and the metal sacrificial layer 104a and the insulating sacrificial layer 104b may be completely removed before forming the first packaging wiring layer.
  • the temporary support layer 001 may only use a silicon wafer as the support structure 003, and at the same time, the sacrificial pattern layer may only use silicon oxide. layer, the silicon oxide sacrificial pattern layer can be completely removed.
  • the support structure 003 may select a wafer as the temporary support layer 001 , and a thermal release material as the releasable layer 002 , and at the same time,
  • the sacrificial pattern layer can be selected from a metal sacrificial layer 104a and an insulating sacrificial layer 104b, and only the metal sacrificial layer 104a can be removed before forming the first packaging wiring layer.
  • a second interconnection hole 202 penetrating the first packaged winding layer is formed on one side of the first packaged winding layer, and after the second interconnected hole 202 is also aligned and connected with the winding pattern corresponding to the projection position,
  • the method further includes: forming a second packaging wiring layer on the side of the first packaging wiring layer away from the chip 010; forming a fourth interconnection hole penetrating the second packaging wiring layer on the side of the second packaging wiring layer 302, the fourth interconnection hole 302 is also in alignment and communication with the first package winding layer corresponding to the projected position.
  • a second packaging wiring layer may be further formed on the side of the first packaging wiring layer away from the chip 010, as shown in FIG. 8 or In FIG. 12 , a second package wiring layer is formed over the first package wiring layer.
  • the pins in the second packaging wiring pattern of the second packaging wiring layer and the first packaging wiring pattern of the first packaging wiring layer may be pin alignment.
  • a penetrating fourth interconnection hole 302 may also be formed on the second package winding layer, so as to connect the first package winding layer on the second package winding layer.
  • the pins in the two package wiring patterns communicate with the pins in the first package wiring pattern of the first package wiring layer.
  • the conductive material can be continuously formed in the fourth interconnection hole 302, so as to enable the pins in the wiring pattern of the second package to communicate with the first package
  • the pins in the winding pattern form an electrical connection structure.
  • the formation of the first interconnection hole 102 , the second interconnection hole 202 , the third interconnection hole 204 and the fourth interconnection hole 302 may be performed by laser printing, photolithography, or dry etching. and many other methods to prepare. Forming the conductive material in the interconnection hole may be only on the sidewalls and bottom of the interconnection hole, or may be in a form such that the conductive material completely fills the interconnection hole.
  • the method of forming the conductive material in the interconnection hole can be by magnetron sputtering or electroless plating of the seed layer metal on the sidewall and bottom of the interconnection hole, or by filling the conductive material in the interconnection hole by an electroplating process, or It is to fill the interconnection holes with the conductive material by the method of printing the conductive material with a screen/stencil, which is not limited in this application.
  • the conductive material in the first interconnection hole 102 , the second interconnection hole 202 , the third interconnection hole 204 and the fourth interconnection hole 302 may be copper, aluminum, tungsten, conductive paste, tin-silver alloy, tin-silver-copper alloy , at least one of gold-tin alloy and the like.
  • the remaining space inside the interconnect hole can be filled with the material of the next level formed thereon, such as the remaining space of the first interconnect hole 102
  • the second insulating layer 201 may be filled with the material of the second insulating layer 201 when the second insulating layer 201 is formed.
  • forming the second packaging wiring layer on the side of the first packaging wiring layer away from the chip 010 includes: as shown in FIG. 8 or FIG. Three insulating layers 301 ; a second packaging wire pattern layer 303 is formed on the side of the third insulating layer 301 away from the chip 010 .
  • the second packaging wiring pattern of the second packaging wiring pattern layer 303 corresponds to the position of the first packaging wiring pattern (ie, the pins connected to the two correspond to each other).
  • Materials of the first insulating layer 101 , the second insulating layer 201 and the third insulating layer 301 in the embodiments of the present application may include polyimide (Polyimide), benzocyclobutene (BCB), parylene , at least one of industrialized liquid crystal polymer (LCP), epoxy resin, silicon oxide, silicon nitride, ceramic, aluminum oxide, glass, and the like.
  • Polyimide Polyimide
  • BCB benzocyclobutene
  • LCP industrialized liquid crystal polymer
  • epoxy resin silicon oxide, silicon nitride, ceramic, aluminum oxide, glass, and the like.
  • the present application may include a multi-layer encapsulation winding layer.
  • the above embodiments schematically show one-layer and two-layer embodiments.
  • three-layer, four-layer and other multi-layer packaging and winding layers are formed, refer to The embodiment of forming the second packaging wiring layer on the first packaging wiring layer will not be repeated in this application.
  • the preparation method can simplify the process of the multi-layer metal circuit structure and reduce the production cost.
  • lead pads can be formed thereon, and then a whole layer of solder resist layer 401 is formed, and at least part of the solder resist layer 401 covering the lead pads is removed by patterning , and grow solder balls 402 on the lead pads.
  • solder resist layer 401 is formed on the second package winding layer, and then a whole-layer solder resist layer 401 is formed, and at least part of the solder resist layer covering the lead pads is removed by patterning 401, and grow solder balls 402 on the pin pads.
  • the line width of the interconnecting wiring pattern is smaller than the line width of the first packaging wiring pattern of the first packaging wiring pattern layer 203; The pitch of the first package wiring pattern.
  • the line width of the first packaging wiring pattern of the first packaging wiring pattern layer 203 may be the line width of the packaging wiring itself in the first packaging wiring pattern.
  • the pitch of the first encapsulation routing pattern of the first encapsulation routing pattern layer 203 may be the pitch between two adjacent encapsulation lines in the first encapsulation routing pattern.
  • the line width of the first packaging wiring pattern may be 2 micrometers to 5 micrometers (including 2 micrometers and 5 micrometers); the line pitch of the first packaging wiring pattern may be 2 micrometers to 5 micrometers (including 2 micrometers and 5 micrometers).
  • the line width of the interconnecting wiring pattern is smaller than the line width of the second packaging wiring pattern of the second packaging wiring pattern layer 303; the line spacing of the interconnecting wiring pattern is smaller than that of the second packaging wiring pattern layer 303 The pitch of the second package wiring pattern.
  • the line width of the second packaging wiring pattern of the second packaging wiring pattern layer 303 may be the line width of the packaging wiring itself in the second packaging wiring pattern.
  • the pitch of the second encapsulation routing pattern of the second encapsulation routing pattern layer 303 may be the pitch between two adjacent encapsulation lines in the second encapsulation routing pattern.
  • the line width of the second package wiring pattern may be greater than 5 microns.
  • the line width of the package wiring patterns of other package wiring pattern layers formed on the second package wiring layer may be greater than 5 microns.
  • the interconnection pattern winding layer and the package winding layer sequentially formed on the side of the interconnection pattern winding layer away from the chip 010 are along the direction from the chip 010 to the interconnection pattern winding layer (ie, FIG. 8 ). or the direction from bottom to top in FIG. 12 ), the line width and line spacing gradually increase.
  • the line width of the interconnecting wiring pattern is smaller than the line width of the second packaging wiring pattern of the second packaging wiring pattern layer 303; the line spacing of the interconnecting wiring pattern is smaller than that of the second packaging wiring pattern layer 303 The pitch of the second package wiring pattern.
  • a sacrificial layer 104 with a pattern is formed on one surface of the support structure 003 , a fine interconnection winding layer is formed on the sacrificial layer 104 , and the winding pattern of the fine interconnection winding layer corresponds to the pattern position of the sacrificial layer 104 .
  • a first insulating layer 101 is formed on the fine interconnection winding layer, and a plurality of chips 010 are mounted, and the chip pins are aligned with the pattern of the fine interconnection winding layer.
  • the above structure is encapsulated from the side of the chip 010 through the plastic encapsulation body 020, the temporary support layer 001 is removed, and the first interconnection hole penetrating the sacrificial layer 104, the fine interconnect wiring layer, and the first insulating layer 101 is formed on the side of the sacrificial layer 104 102, so that the fine interconnection wiring layer is electrically connected with the high-density interconnection pins of the chip.
  • All or part of the sacrificial layer 104 is removed, at least one insulating layer and at least one packaging winding layer are alternately prepared on the first insulating layer 101, and each layer of packaging winding layer and low-density pins of the chip are connected through interconnect holes , and/or, at least one of the previously prepared winding layers is electrically connected.
  • a sacrificial layer 104 with a pattern is formed on one side surface of the support structure 003; a fine interconnection winding layer is formed on the sacrificial layer 104, and the fine interconnection winding layer corresponds to the pattern position of the sacrificial layer 104; A first insulating layer 101 is formed on the layer; a plurality of chips 010 are mounted on the side of the first insulating layer 101 away from the fine interconnection winding layer, and the plurality of chips 010 are respectively arranged on the interconnection windings of the fine interconnection winding layer.
  • the alignment of the high-density inter-chip interconnection pins of the chip 010 and the fine interconnection winding layer is realized; the multiple chips 010 are plastic-sealed with an encapsulation material, and the first insulating layer 101 is covered; the support structure 003 is removed , using the pattern of the sacrificial layer 104 to form a first interconnection hole 102 that penetrates the sacrificial layer 104, the fine interconnection wiring layer and the first insulating layer 101 and exposes the high-density interconnection pins of the chip 010; A conductive material is formed in the hole 102, and the connection between the fine interconnection winding layer and the high-density interconnection pins is realized through the first interconnection hole 102; after removing all or part of the sacrificial layer 104, the fine interconnection winding layer and the first interconnection A second insulating layer 201 is formed on the insulating layer 101, covering the fine interconnection wiring layer and the first interconnection hole 102;
  • connection of the winding layer; the package winding layer farthest from the chip is provided with a pin pad, the solder mask layer 401 is covered on the package winding layer farthest from the chip, and the solder mask covering at least part of the pin pad is removed. layer 401 and grow solder balls 402 on the lead pads.
  • FIG. 2 Another aspect of the embodiments of the present application provides a chip interconnect packaging structure prepared by using any of the above-mentioned chip interconnect packaging methods, including: as shown in FIG. 2 , sequentially arranging interconnect wires on the sacrificial pattern layer The pattern layer 103 and a plurality of chips 010; the wiring pattern of the interconnection winding pattern layer 103 corresponds to the sacrificial pattern position of the sacrificial pattern layer, and the plurality of chips 010 are respectively arranged on the interconnection windings of the interconnection winding pattern layer 103.
  • a first interconnection hole 102 penetrating the sacrificial pattern and the interconnection wiring pattern is opened on one side of the sacrificial pattern layer, and the first interconnection hole 102 is also corresponding to the projection position of the first interconnection pin of the chip 010 011 Alignment connection.
  • the chip interconnect package structure includes multiple chips 010 and multiple winding layers and insulating layers; the chips include devices and pins, and the pins include high-density interconnect pins and low-density interconnect pins; multiple winding layers Including the interconnection winding pattern layer 103 and the package winding layer (for example, the first and second package winding layers), the line width and line spacing of the interconnection winding pattern layer 103 is smaller than the line width and line spacing of the package winding layer;
  • the wiring pattern layer 103 is connected to the chip 010 through the high-density interconnection pins of the chip 010; the first interconnection holes 102 between the interconnection wiring pattern layer 103 and the high-density interconnection pins of the chip 010 use a sacrificial layer
  • the structure (sacrificial layer 104 ) and the interconnection wiring pattern layer 103 are formed with a pin structure, and high-density interconnection pins of the interconnection wiring pattern layer 103 and the chip 010 are realized by arranging
  • chip interconnect packaging structure may also form corresponding structures in sequence corresponding to the aforementioned chip interconnect packaging method.
  • the chip interconnect packaging structure and method of the present application are manufactured by first performing the structural design and process of the sacrificial pattern layer and the interconnecting wiring pattern layer, and then performing the mounting of the chip and the interconnecting wiring pattern layer, and then forming the vertical interconnection pattern layer. Connect the structure, remove the sacrificial pattern layer, and then carry out the construction of the subsequent fan-out package winding layer, thereby improving the alignment accuracy between layers in the vertical direction, realizing multi-chip short-distance high-precision interconnection, and increasing the bandwidth of data transmission.
  • the preparation method can also simplify the process of the multi-layer metal circuit structure, reduce the production cost, and can be applied to the fields of integrated circuits, optoelectronic devices and the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本申请提供一种芯片互连封装结构及方法，涉及半导体封装技术领域，在支撑结构形成牺牲图案层；在牺牲图案层上形成互连绕线图案层，互连绕线图案层与牺牲图案层的牺牲图案位置对应；在互连绕线图案层上形成第一绝缘层；在第一绝缘层上形成多个间隔设置的芯片，多个芯片分别与互连绕线图案层的互连绕线图案位置对应；去除支撑结构，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通。通过牺牲图案层的设置，可以辅助定义出多个芯片互连的开孔位置，进而在后续依次形成互连绕线图案层和芯片后，能够根据牺牲图案中的开孔位置精确实现多个芯片之间的互连互通。

Description

一种芯片互连封装结构及方法 技术领域
本申请涉及半导体封装技术领域，具体而言，涉及一种芯片互连封装结构及方法。
背景技术
半导体工业通过不断减小最小特征尺寸来不断提高多种电子部件，例如晶体管、二极管、电阻器和电容器等的集成度，这使得更多的部件集中到给定区域，从而提高了芯片的运算能力。但是随着最小特征尺寸不断在纳米尺度下探，已经濒临物理极限。同时，人工智能、物联网、5G、自动驾驶、高性能云计算等技术又处于快速发展当中。在此背景下，需要实现多种芯片在短距离上形成互连的同时提高数据传输带宽。
现有的多芯片短距离互连方案，通常由于制造精度的问题，无法制造更精细的互连线路，进而导致无法提高数据传输带宽。
发明内容
本申请的目的在于，针对上述现有技术中的不足，提供一种芯片互连封装结构及方法，以改善现有多芯片在短距离互连时由于制造精度的问题，无法制造更精细的互连线路的问题。
为实现上述目的，本申请实施例采用的技术方案如下：
本申请实施例的一方面，提供一种芯片互连封装方法，方法包括：在支撑结构的一侧表面形成牺牲图案层；在牺牲图案层上形成互连绕线图案层，互连绕线图案层的绕线图案与牺牲图案层的牺牲图案位置对应；在互连绕线图案层上形成第一绝缘层；在第一绝缘层上形成多个间隔设置的芯片，多个芯片分别与互连绕线图案层的互连绕线图案位置对应；去除支撑结构，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通。
可选的，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通之后，方法还包括：在第一互连孔内形成导电材料，第一互连孔内的导电材料对互连绕线图案和芯片的第一互连引脚电连接。
可选的，互连绕线图案的线宽为0.5微米至2微米，互连绕线图案的线距为0.5微米至2微米。
可选的，在第一绝缘层上形成多个间隔设置的芯片之后，方法还包括：在多个芯片上形成塑封体。
可选的，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通之后，方法还包括：去除牺牲图案层，或，当牺牲图案层包括依次设置于互连绕线图案层上的绝缘牺牲层和金属牺牲层时，去除金属牺牲层。
可选的，在去除牺牲图案层，或，当牺牲图案层包括依次设置于互连绕线图案层上的绝缘牺牲层和金属牺牲层时，去除金属牺牲层之后，方法还包括：在互连绕线图案层远离芯片的一侧形成第一封装绕线层；在第一封装绕线层一侧形成穿透第一封装绕线层的第二互连孔，第二互连孔还与投影位置对应的互连绕线图案对位连通。
可选的，在牺牲图案层远离芯片的一侧形成第一封装绕线层之后，方法还包括：在第一封装绕线层一侧还形成穿透第一封装绕线层的第三互连孔，第三互连孔还与投影位置对应的芯片的第二互连引脚对位连通。
可选的，在互连绕线案层远离芯片的一侧形成第一封装绕线层包括：在互连绕线图案层远离芯片的一侧形成第二绝缘层，在第二绝缘层远离芯片一侧形成第一封装绕线图案层，第一封装绕线图案层的第一封装绕线图案与互连绕线图案位置对应。
可选的，在第一封装绕线层一侧形成穿透第一封装绕线层的第二互连孔，第二互连孔还与投影位置对应的绕线图案对位连通之后，方法还包括：在第一封装绕线层远离芯片的一侧形成有第二封装绕线层；在第二封装绕线层一侧形成穿透第二封装绕线层的第四互连孔，第四互连孔还与投影位置对应的第一封装绕线层对位连通。
可选的，在第一封装绕线层远离芯片的一侧形成有第二封装绕线层包括：在第一封装绕线层远离芯片的一侧形成有第三绝缘层；在第三绝缘层远离芯片的一侧形成有第二封装绕线图案层。
可选的，互连绕线图案的线宽小于第一封装绕线图案层的第一封装绕线图案的线宽；互连绕线图案的线距小于第一封装绕线图案层的第一封装绕线图案的线距。
可选的，第一封装绕线图案层的第一封装绕线图案的线宽为2微米至5微米，第一封装绕线图案层的第一封装绕线图案的线距为2微米至5微米。
可选的，第二封装绕线图案层的第二封装绕线图案的线宽大于5微米。
本申请实施例的另一方面，提供一种芯片互连封装结构，采用上述任一种的芯片互连封装方法制备，包括：在牺牲图案层上依次设置互连绕线图案层和多个芯片；互连绕线图案层的绕线图案与牺牲图案层的牺牲图案位置对应，多个芯片分别对应设置在与互连绕线图案层的互连绕线图案上；在牺牲图案层一侧开设穿透牺牲图案和互连绕线图案的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通。
本申请实施例的再一方面，提供一种芯片互连封装结构，应用上述任一种的芯片互连封装结构制备。
本申请的有益效果包括：
本申请提供了一种芯片互连封装方法，在支撑结构的一侧表面形成牺牲图案层；在牺牲图案层上形成互连绕线图案层，互连绕线图案层的绕线图案与牺牲图案层的牺牲图案位置对应；在互连绕线图案层上形成第一绝缘 层；在第一绝缘层上形成多个间隔设置的芯片，多个芯片分别与互连绕线图案层的互连绕线图案位置对应；去除支撑结构，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通。通过牺牲图案层的设置，可以辅助定义出多个芯片互连的开孔位置，进而在后续依次形成互连绕线图案层和芯片后，能够根据牺牲图案中的开孔位置精确实现多个芯片之间的互连互通。
本申请提供了一种芯片互连封装结构，通过牺牲图案层的设置，可以辅助定义出多个芯片互连的开孔位置，进而在后续依次形成互连绕线图案层和芯片后，能够根据牺牲图案中的开孔位置精确实现多个芯片之间的互连互通。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施例提供的一种芯片互连封装方法的流程示意图；
图2为本申请实施例提供的一种芯片互连封装结构的结构示意图之一；
图3为本申请实施例提供的一种芯片互连封装结构的结构示意图之二；
图4为本申请实施例提供的一种芯片互连封装结构的俯视图；
图5为本申请实施例提供的一种芯片互连封装结构的结构示意图之一；
图6为本申请实施例提供的一种芯片互连封装结构的结构示意图之三；
图7为本申请实施例提供的一种芯片互连封装结构的结构示意图之四；
图8为本申请实施例提供的一种芯片互连封装结构的结构示意图之五；
图9为本申请实施例提供的一种芯片互连封装结构的结构示意图之六；
图10为本申请实施例提供的一种芯片互连封装结构的结构示意图之二；
图11为本申请实施例提供的一种芯片互连封装结构的结构示意图之七；
图12为本申请实施例提供的一种芯片互连封装结构的结构示意图之八。
图标：010-芯片；020-塑封体；011-第一互连引脚；012-第二互连引脚；101-第一绝缘层；102-第一互连孔；103-互连绕线图案层；104-牺牲层；104a-金属牺牲层；104b-绝缘牺牲层；201-第二绝缘层；202-第二互连孔；203-第一封装绕线图案层；204-第三互连孔；301-第三绝缘层；302-第四互连孔；303-第二封装绕线图案层；401-阻焊层；402-焊料球；001-临时支撑层；002-可释放层；003-支撑结构。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常 在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。需要说明的是，在不冲突的情况下，本申请的实施例中的各个特征可以相互结合，结合后的实施例依然在本申请的保护范围内。
在本申请的描述中，需要说明的是，术语“中间”、“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
在本申请的描述中，还需要说明的是，除非另有明确的规定和限定，术语“设置”、“连通”应做广义理解，例如，可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
本申请实施例的一方面，提供一种芯片互连封装方法，通过设置被图案化的牺牲图案层，为实现多个芯片010之间精细互连起到辅助定位作用，使得多个芯片010之间能够实现短距离精细互连，如图1所示，该方法示意性的可以包括：
S010：在支撑结构的一侧表面形成牺牲图案层。
如图2所示，设置支撑结构003，在支撑结构003的一侧表面形成牺牲图案层，即图2中在支撑结构003下方形成牺牲图案层。牺牲图案层可以是先在支撑结构003的表面形成整层的牺牲层104，然后对整层的牺牲层104进行图案化工艺后形成的层级结构。牺牲层104的图案化可以根据后续需要形成的第一互连孔102的位置(以下简称开孔位置)进行设定，即牺牲图案层中的牺牲图案中包括至少一处第一互连孔102的形成位置，例如两个以上的开孔位置。
S020：在牺牲图案层上形成互连绕线图案层，互连绕线图案层的绕线图案与牺牲图案层的牺牲图案位置对应。
如图2所示，在牺牲图案层形成后，继续在牺牲图案层上形成互连绕线图案层103，互连绕线图案层103可以是先在支撑结构003的表面形成整层的互连绕线层，然后对整层的互连绕线层进行图案化工艺后形成的层级结构。
互连绕线图案层103可以是采用与牺牲图案层位置对应的方式形成，即在对互连绕线层进行图案化处理后，使得互连绕线图案层103的互连绕线图案和牺牲图案层的牺牲图案位置对应，例如使得互连绕线图案中的引脚和牺牲图案中的开孔位置一一对应。
S030：在互连绕线图案层上形成第一绝缘层。
如图2所示，在互连绕线图案层103上先形成第一绝缘层101；然后在第一绝缘层101上形成多个芯片010，将多个芯片010采用相互间隔的方式设置，可以有效避免多个芯片010之间相互干扰。同时，第一绝缘层101应位于互连绕线图案层103和芯片010层之间。
第一绝缘层101可以是绝缘材料或异向导电材料形成具有粘合作用的粘合层，此时，在第一绝缘层101上形成多个芯片010时，多个芯片010可以采用精准对位互连绕线图案层103的方式粘合设置于第一绝缘层101上。为了进一步的提高粘合的稳定性，可以对粘合完成后的结构进行固化处理。
S040：在第一绝缘层上形成多个间隔设置的芯片，多个芯片分别与互连绕线图案层的互连绕线图案位置对应。
如图2、图3、图9所示，在第一绝缘层101上继续形成多个芯片010，多个芯片010可以是同层间隔一定间距排布。多个芯片010分别与互连绕线图案对应，使得多个芯片010中的第一互连引脚011和互连绕线图案中的引脚对应，上述的对应可以是沿垂直支撑结构003的方向的对应，即相对应的两者在平行支撑结构003平面的同一平面内的正投影位置对齐。最终，如图4所示，芯片010表面的第一互连引脚011、互连绕线图案层103的引脚图案以及牺牲层104表面图案开孔位置均一一对应，即上述三者结构沿垂直于临时支撑层001的方向对应，即相对应的两者在平行于临时支撑层001平面的同一平面内的正投影部分或者全部重叠。
S050：去除支撑结构，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层的第一互连孔，第一互连孔还与投影位置对应的芯片的第一互连引脚对位连通。
在完成S040后，如图5所示，去除支撑结构003，然后根据牺牲图案中的开孔位置在牺牲图案层的一侧形成第一互连孔102，第一互连孔102依次穿透牺牲图案、互连绕线图案和第一绝缘层101，同时，第一互连孔102还延伸至芯片010，由于牺牲图案中的开孔位置与互连绕线图案中的引脚对应，互连绕线图案中的引脚与芯片010的第一互连引脚011对应，因此，芯片010的第一互连引脚011和牺牲图案中的开孔位置在芯片010的投影位置至少部分重叠，在第一互连孔102延伸至芯片010时，其可以将互连绕线图案中的引脚和芯片010的第一互连引脚011连通，从而实现芯片010和互连绕线图案层103的精确连通，进而在多个芯片010均精确连通至互连绕线图案层103后，实现多个芯片010之间的互连通。通过牺牲图案层的设置，可以辅助定义出多个芯片010互连的开孔位置，进而在后续依次形成互连绕线图案层103和芯片010后，能够根据牺牲图案中的开孔位置精确实现多个芯片010之间的互连互通。首先进行牺牲图案层和互连绕线图案层103的结构设计和工艺制成，再进行芯片010与互连绕线图案层103的贴装，之后再形成垂直互连结构，去除牺牲图案层，继而进行后续扇出封装绕线层的构建。因此，可以提高垂直方向上的层间对准精度，实现多芯片 010短距离高精度互连。此外，牺牲图案层中的牺牲图案不仅可以定义第一互连孔102的位置，还可以对其孔径大小也作出定义。
互连绕线图案层103的互连绕线图案中可以包括有多条互连线路，每一条互连线路都可以具有两个引脚，这两个引脚分别与互连的两个芯片010中的一个第一互连引脚011对应，进而通过第一互连孔102的连通，实现两个芯片010的初步连通，示意性的如图4所示在牺牲图案层上示意性的给出了三条互连线路中的一部分，该三条线路中的端部和互连芯片010中的一者的第一互连引脚011上下对应重叠或者部分重叠，并通过端部的第一互连孔102实现连通，同理，随着互连线路延伸至互连芯片010中的另一者的正上方时，该三条线路中的另一端部也和互连芯片010中的另一者的第一互联引脚上下对应重叠或者部分重叠，并通过互连线路另一端部的第一互连孔102实现连通。
在本申请实施例中，如图2所示，第一互连引脚011可以是芯片010中的高密度互联引脚，互连绕线图案层103也可以对应为精细线路绕线层，通过牺牲图案层的辅助定位，可以提高多芯片010之间的精细互连精度，从而提高数据传输的带宽。
支撑结构003起到临时支撑的作用，其材料可以是硅、二氧化硅、玻璃、激光释放材料、热释放材料等等中的一种或多种，例如其中的一种实施例中，如图2所示，支撑结构003包括临时支撑层001(硅、二氧化硅、玻璃等)和可释放层002(激光释放材料、热释放材料等)，可以在去除可释放层002以露出牺牲图案层的表面时，通过释放去除的方式进行，从而减少对牺牲图案层的影响，进而提高牺牲图案层中形成第一互连孔102的精度；另一种实施例中，如图3所示，支撑结构003包括临时支撑层001。支撑结构003的去除方式可以是通过湿法刻蚀、干法刻蚀、激光释放去除、热释放去除等等。在选择去除方式时，可以根据支撑结构003的材料进行适应性选择，本申请对其不做限制。
牺牲图案层的构成材料可以是金属、聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、工业化液晶聚合物(LCP)、环氧树脂、硅氧化、硅氮化物、铝氧化物等等中的一种或多种。例如其中的一种实施例中，如图2所示，牺牲图案层包括金属牺牲层104a和绝缘牺牲层104b，绝缘牺牲层104b应位于金属牺牲层104a和互连绕线图案层103之间；在另一种实施例汇总，如图3所示，牺牲图案层也可以是绝缘牺牲层104b。
可选的，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案和第一绝缘层10的第一互连孔102，第一互连孔102还与投影位置对应的芯片010的第一互连引脚011对位连通之后，方法还包括：在第一互连孔102内形成导电材料，第一互连孔102内的导电材料对互连绕线图案和芯片010的第一互连引脚011电连接。
示意的，在形成有第一互连孔102后，为了实现第一互连引脚011和 互连绕线图案层103中的互连线路的可电连接性，还可以在第一互连孔102内形成导电材料，通过导电材料将第一互连引脚011和互连绕线图案层103中的互连线路连接，形成可导电的电连接结构，由此实现芯片010和互连绕线图案层103的电连接，从而使得互连的芯片010可以通过互连绕线图案层103实现互连，进而传输数据等。
可选的，互连绕线图案的线宽为0.5微米至2微米，互连绕线图案的线距为0.5微米至2微米。
示例的，互连绕线图案的线宽可以是互连绕线图案中的互连线路自身的线路宽度，其设置范围可以是0.5微米至2微米(包括0.5微米和2微米)；互连绕线图案的线距可以是互连绕线图案中的相邻两条互连线路之间的间距，其设置范围可以是0.5微米至2微米(包括0.5微米和2微米)，从而能够保证多芯片010互连稳定的同时，提高芯片010数据传输的带宽。
可选的，如图2所示，在第一绝缘层10上形成多个间隔设置的芯片010之后，还可以在多个芯片010上形成塑封体020，塑封体020可以由包封材料形成。塑封体020完全将多个芯片010包覆，即包覆芯片010与第一绝缘层101贴合一侧之外的所有侧壁，以提高芯片010的稳定性。在前述实施例中去除支撑结构003之前，可以先在多个芯片010上形成塑封体020，然后再去除支撑结构003，并进行后续的工艺步骤。
可选的，在牺牲图案层一侧形成穿透牺牲图案、互连绕线图案第一绝缘层101的第一互连孔102，第一互连孔102还与投影位置对应的芯片010的第一互连引脚011对位连通之后，方法还包括：去除牺牲图案层，或，当牺牲图案层包括依次设置于互连绕线图案层上的绝缘牺牲层104b和金属牺牲层104a时，去除金属牺牲层104a。
在对前述实施例中形成有第一互连孔102的结构且在第一互连孔102内填充有导电材料之后，可以对互连绕线图案层103上的牺牲图案层进行部分去除或完全去除，示意的可以由以下两种实施例对其进行说明：
其中的一种实施例中，如图6所示，将位于互连绕线图案层103上的牺牲图案层完全去除，然后通过后续实施例在互连绕线图案层103的表面直接形成第一封装绕线层，第一封装绕线层中的第一封装绕线图案与互连绕线图案上下对位。在此实施例中，如图7所示，第二互连孔202则穿透第一封装绕线层并且延伸至互连绕线图案层103的表面。
其中的另一种实施例中，如图10所示，将位于互连绕线图案层103上的牺牲图案层的部分去除，即当牺牲图案层包括位于互连绕线图案层103上的绝缘牺牲层104b和金属牺牲层104a时，可以将金属牺牲层104a去除，保留绝缘牺牲层104b，也可以保留部分绝缘牺牲层104b，然后，通过后续实施例在剩余牺牲图案层的表面形成第一封装绕线层，第一封装绕线层中的第一封装绕线图案与互连绕线图案上下对位。在此实施例中，如图11所示，第二互连孔202依次穿透第一封装绕线层和剩余牺牲图案层(例如图 11中的绝缘牺牲层104b)并且延伸至互连绕线图案层103的表面。
在上述实施例中，对牺牲图案层去除的方式可以包括湿法蚀刻、干法蚀刻、机械磨平、化学机械抛光等等中的至少一种。
在去除牺牲图案层，或，当牺牲图案层包括依次设置于互连绕线图案层上的绝缘牺牲层和金属牺牲层时，去除金属牺牲层之后，方法还包括：在互连绕线图案层103远离芯片010的一侧形成第一封装绕线层；在第一封装绕线层一侧形成穿透第一封装绕线层的第二互连孔202，第二互连孔202还与投影位置对应的互连绕线图案对位连通。
示例的，在前述两种实施例中(完全去除牺牲图案层和部分去除牺牲图案层)形成的互连绕线图案层103的表面或在剩余牺牲图案层的表面，还可以进一步的形成第一封装绕线层，即在互连绕线图案层103远离芯片010的一侧形成第一封装绕线层，如图7或图9中，在互连绕线图案层103的上方形成第一封装绕线层。在此实施例中，在形成第一封装绕线层时，可以使得第一封装绕线层的第一封装绕线图案中的部分引脚(如图7或图11中位于第一封装绕线图案层203中靠近中间部分的引脚)和互连绕线图案中的引脚(如图7或图11中位于互连绕线图案层103中与芯片010第一互连引脚011对应的引脚的旁侧的引脚)对位。为了实现第一封装绕线层和互连绕线图案的连通，还可以在第一封装绕线层上形成穿透的第二互连孔202，从而将第一封装绕线层上的第一封装绕线图案中的引脚和互连绕线图案中的引脚连通。此外，还可以参照在第一互连孔102内形成导电材料的方式，继续在第二互连孔202内形成导电材料，以便于使得互连绕线图案中的引脚能够和第一封装绕线层中的第一封装绕线图案中的引脚形成电连接结构。
可选的，在牺牲图案层远离芯片010的一侧形成第一封装绕线层之后，方法还包括：若还需要使得第一封装绕线层和芯片010连通，还可以在形成第一封装绕线层时，使得第一封装绕线层中的第一封装绕线图案中的引脚(如图7或图11中位于第一封装绕线层图案层最外侧的引脚)与芯片010的第二互连引脚012上下对位。如图7或图11所示，在第一封装绕线层一侧还形成穿透第一封装绕线层的第三互连孔204，第三互连孔204还与投影位置对应的芯片010的第二互连引脚012对位连通，从而实现第一封装绕线层中的第一封装绕线层图案层与芯片010的连通。
在本申请实施例中，如图8或图12所示，第二互连引脚012可以是芯片010中的低密度互联引脚。
在完全去除牺牲图案层实施例的基础上，如图7所示，还可以继续形成第三互连孔204，第三互连孔204将依次穿透第一封装绕线层、互连绕线图案层103(在第三互连孔204穿透位置并无引脚)和第一绝缘层101并延伸至芯片010的表面。第二互连孔202和第三互连孔204在同一实施例中时，两者可以是同一工艺中形成，也可以是先后形成，本申请对其不做具体限定。
在部分去除牺牲图案层实施例的基础上，如图11所示，还可以继续形成第三互连孔204，第三互连孔204将依次穿透第一封装绕线层、剩余牺牲图案层(例如图11中的绝缘牺牲层104b)、互连绕线图案层103(在第三互连孔204穿透位置并无引脚)和第一绝缘层101并延伸至芯片010的表面。
可选的，在互连绕线案层远离芯片010的一侧形成第一封装绕线层包括：如图7或图11所示，在互连绕线图案层103远离芯片010的一侧形成第二绝缘层201在第二绝缘层201远离芯片010一侧形成第一封装绕线图案层203，即形成第二绝缘层201位于第一封装绕线图案层203和互连绕线图案层103之间的结构。第一封装绕线图案层203的第一封装绕线图案与互连绕线图案位置对应(即两者连通的引脚对应)，在还包括第三互连孔204的实施例中，第一封装绕线图案层203的第一封装绕线图案还与芯片010位置对应(即两者连通的引脚对应)，第三互连孔204在穿透第一封装绕线层时，依次穿过第一封装绕线图案层203和第二绝缘层201。
示意的，在一种实施例中，如图2、图5、图6、图7和图8所示，支撑结构003可以选用玻璃载板作为临时支撑层001，激光释放材料作为可释放层002，同时，牺牲图案层可以选用金属牺牲层104a和绝缘牺牲层104b，在形成第一封装绕线层之前，可以完全去除金属牺牲层104a和绝缘牺牲层104b。
示意的，在另一种实施例中，如图3所示，临时支撑层001可以仅选用硅晶圆作为支撑结构003，同时，牺牲图案层可以仅选用氧化硅，在形成第一封装绕线层之前，可以完全去除氧化硅牺牲图案层。
示意的，在再一种实施例中，如图9、图10、图11和图12所示，支撑结构003可以选用晶圆作为临时支撑层001，热释放材料作为可释放层002，同时，牺牲图案层可以选用金属牺牲层104a和绝缘牺牲层104b，在形成第一封装绕线层之前，可以仅去除金属牺牲层104a。
可选的，在第一封装绕线层一侧形成穿透第一封装绕线层的第二互连孔202，第二互连孔202还与投影位置对应的绕线图案对位连通之后，方法还包括：在第一封装绕线层远离芯片010的一侧形成有第二封装绕线层；在第二封装绕线层一侧形成穿透第二封装绕线层的第四互连孔302，第四互连孔302还与投影位置对应的第一封装绕线层对位连通。
示例的，在前述实施例中形成有第二互连孔202的结构上，还可以进一步的在第一封装绕线层远离芯片010的一侧形成第二封装绕线层，即如图8或图12中，在第一封装绕线层的上方形成第二封装绕线层。在此实施例中，在形成第二封装绕线层时，可以使得第二封装绕线层的第二封装绕线图案中的引脚和第一封装绕线层的第一封装绕线图案中的引脚对位。为了实现第二封装绕线层和第一封装绕线层的连通，还可以在第二封装绕线层上形成穿透的第四互连孔302，从而将第二封装绕线层上的第二封装绕线图 案中的引脚和第一封装绕线层的第一封装绕线图案中的引脚连通。此外，还可以参照在第一互连孔102内形成导电材料的方式，继续在第四互连孔302内形成导电材料，以便于使得第二封装绕线图案中的引脚能够和第一封装绕线图案中的引脚形成电连接结构。
在本申请实施例中，第一互连孔102、第二互连孔202、第三互连孔204和第四互连孔302的形成，可以是由激光打印、光刻、干法刻蚀等等多种工艺方法制备。在互连孔内形成导电材料可以是仅在互连孔的侧壁和底部，也可以是使得导电材料完全填充互连孔的形式。在互连孔内形成导电材料的方式可以是在互连孔的侧壁和底部通过磁控溅射或化学镀种子层金属，也可以是利用电镀工艺在互连孔内填充导电材料，还可以是用丝网/钢网印刷导电材料的方法在互连孔内填满导电材料，本申请对其不做限制。第一互连孔102、第二互连孔202、第三互连孔204和第四互连孔302内的导电材料可以为铜、铝、钨、导电膏、锡银合金、锡银铜合金、金锡合金等等中的至少一种。
当仅在互连孔的侧壁和底部涂覆导电材料时，在互连孔内部的剩余空间可以由在其上形成的下一层级的材料所填充，例如第一互连孔102剩余的空间可在形成第二绝缘层201时，由第二绝缘层201的材料填充。
可选的，在第一封装绕线层远离芯片010的一侧形成有第二封装绕线层包括：如图8或图12，在第一封装绕线层远离芯片010的一侧形成有第三绝缘层301；在第三绝缘层301远离芯片010的一侧形成有第二封装绕线图案层303。第二封装绕线图案层303的第二封装绕线图案与第一封装绕线图案位置对应(即两者连通的引脚对应)。
本申请实施例中的第一绝缘层101、第二绝缘层201和第三绝缘层301的材料可以包括聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、工业化液晶聚合物(LCP)、环氧树脂、硅氧化、硅氮化物、陶瓷、铝氧化物、玻璃等等中的至少一种。
本申请可以包括有多层封装绕线层，以上实施例中示意性的给出了一层和两层的实施例，在形成有三层、四层等等多层封装绕线层时，可以参照第一封装绕线层上形成第二封装绕线层的实施例，本申请对此不再赘述。通过该种制备方法可以简化多层金属线路结构的工序，降低生产成本。
当最后一层封装绕线层形成完毕后，可以在其上形成引脚焊盘，然后形成整层的阻焊层401，通过图案化去掉至少部分覆盖在引脚焊盘上的阻焊层401，并且在引脚焊盘种植焊料球402。例如图8或图12中，在第二封装绕线层上形成形成引脚焊盘，然后形成整层的阻焊层401，通过图案化去掉至少部分覆盖在引脚焊盘上的阻焊层401，并且在引脚焊盘种植焊料球402。
可选的，互连绕线图案的线宽小于第一封装绕线图案层203的第一封装绕线图案的线宽；互连绕线图案的线距小于第一封装绕线图案层203的第一封装绕线图案的线距。
示意的，第一封装绕线图案层203的第一封装绕线图案的线宽可以是第一封装绕线图案中的封装线路自身的线路宽度。第一封装绕线图案层203的第一封装绕线图案的线距可以是第一封装绕线图案中的相邻两条封装线路之间的间距。第一封装绕线图案的线宽可以是2微米至5微米(包括2微米和5微米)；第一封装绕线图案的线距可以是2微米至5微米(包括2微米和5微米)。
可选的，互连绕线图案的线宽小于第二封装绕线图案层303的第二封装绕线图案的线宽；互连绕线图案的线距小于第二封装绕线图案层303的第二封装绕线图案的线距。
示意的，第二封装绕线图案层303的第二封装绕线图案的线宽可以是第二封装绕线图案中的封装线路自身的线路宽度。第二封装绕线图案层303的第二封装绕线图案的线距可以是第二封装绕线图案中的相邻两条封装线路之间的间距。第二封装绕线图案的线宽可以是大于5微米。当包括多个封装绕线层时，形成于第二封装绕线层上的其它封装绕线图案层的封装绕线图案的线宽可以是大于5微米。
可选的，互连图案绕线层和依次形成于互连图案绕线层远离芯片010一侧的封装绕线层沿所述芯片010至所述互连图案绕线层的方向(即图8或图12中从下至上的方向)的线宽线距逐渐增大。
可选的，互连绕线图案的线宽小于第二封装绕线图案层303的第二封装绕线图案的线宽；互连绕线图案的线距小于第二封装绕线图案层303的第二封装绕线图案的线距。
示意的，在支撑结构003的一侧表面形成具有图案的牺牲层104，在牺牲层104上形成精细互连绕线层，精细互连绕线层的绕线图案与牺牲层104的图案位置对应。在精细互连绕线层上形成第一绝缘层101，并且贴装多个芯片010，芯片引脚与精细互连绕线层的图案对准。从芯片010一侧通过塑封体020塑封以上结构，去除临时支撑层001，在牺牲层104一侧形成穿透牺牲层104、精细互连绕线层、第一绝缘层101的第一互连孔102，以使精细互连绕线层与芯片高密度互连引脚电连接。去除全部或者部分牺牲层104，在第一绝缘层101上再交替制备至少一层绝缘层和至少一层封装绕线层，并通过互连孔将每层封装绕线层与芯片低密度引脚，和/或，在先制备的至少一层绕线层电连接。
在支撑结构003的一侧表面形成具有图案的牺牲层104；在牺牲层104上形成精细互连绕线层，精细互连绕线层与牺牲层104的图案位置对应；在精细互连绕线层上形成第一绝缘层101；在第一绝缘层101远离精细互连绕线层的一侧贴装多个芯片010，多个芯片010分别对应设置在精细互连绕线层的互连绕线图案上，实现芯片010的高密度芯片间互连引脚与精细互连绕线层的对准；使用包封材料将多个芯片010塑封，并覆盖第一绝缘层101；去除支撑结构003，利用牺牲层104的图案形成穿透牺牲层104、精 细互连绕线层和第一绝缘层101并且露出芯片010的高密度互连引脚的第一互连孔102；在第一互连孔102内形成导电材料，通过第一互连孔102实现精细互连绕线层和高密度互连引脚的连通；去除全部或者部分牺牲层104之后，在精细互连绕线层和第一绝缘层101之上形成第二绝缘层201，覆盖精细互连绕线层和第一互连孔102；在第二绝缘层2201上形成第一封装绕线图案层203，在第一封装绕线图案层203上形成第二互连孔202、第三互连孔204，第三互连孔202贯穿第一封装绕线图案层203、第二绝缘层201、精细互连绕线层、第一绝缘层101，并露出芯片低密度互连引脚，和/或，第二互连孔202贯穿第一封装绕线图案层203、第二绝缘层201，并露出精细互连绕线层；在第二互连孔202内形成导电材料，实现芯片低密度互连引脚与精细互连绕线层、第一封装绕线图案层的连通；在第一封装绕线图案层远离芯片方向的一侧，再交替制备至少一层绝缘层和至少一层封装绕线图案层，每层绝缘层上形成互连孔，互连孔内形成导电材料，并通过互连孔内导电材料实现每层封装绕线层的连通；最远离芯片的封装绕线层设置有引脚焊盘，在最远离芯片的封装绕线层上覆盖阻焊层401，去掉至少部分覆盖在引脚焊盘上的阻焊层401，并且在引脚焊盘种植焊料球402。
本申请实施例的另一方面，提供一种芯片互连封装结构，采用上述任一种的芯片互连封装方法制备，包括：如图2所示，在牺牲图案层上依次设置互连绕线图案层103和多个芯片010；互连绕线图案层103的绕线图案与牺牲图案层的牺牲图案位置对应，多个芯片010分别对应设置在与互连绕线图案层103的互连绕线图案上；在牺牲图案层一侧开设穿透牺牲图案和互连绕线图案的第一互连孔102，第一互连孔102还与投影位置对应的芯片010的第一互连引脚011对位连通。即芯片互连封装结构包括多个芯片010以及多个绕线层和绝缘层；芯片包括器件和引脚，引脚包括高密度互连引脚和低密度互连引脚；多个绕线层包括互连绕线图案层103和封装绕线层(例如第一、第二封装绕线层)，互连绕线图案层103的线宽线距小于封装绕线层的线宽线距；互连绕线图案层103通过芯片010的高密度互连引脚连接芯片010；互连绕线图案层103与芯片010的高密度互连引脚之间的第一互连孔102，利用牺牲层结构(牺牲层104)和互连绕线图案层103引脚结构形成，并且通过在第一互连孔102内设置导电材料实现互连绕线图案层103和芯片010的高密度互连引脚的电连接；互连绕线图案层103的引脚、芯片010的高密度互连引脚、牺牲层104的图案三者精准对位。
此外，芯片互连封装结构还可以对应前述芯片互连封装方法依次形成对应结构。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
工业实用性
本申请的芯片互连封装结构及方法通过先进行牺牲图案层和互连绕线图案层的结构设计和工艺制成，再进行芯片与互连绕线图案层的贴装，之后再形成垂直互连结构，去除牺牲图案层，继而进行后续扇出封装绕线层的构建，从而提高垂直方向上的层间对准精度，实现多芯片短距离高精度互连，进而提高数据传输的带宽。同时，还可以通过该种制备方法简化多层金属线路结构的工序，降低生产成本，可以应用于集成电路、光电子器件等领域。

Claims (14)

  1. 一种芯片互连封装方法，其特征在于，所述方法包括：
    在支撑结构的一侧表面形成牺牲图案层；
    在所述牺牲图案层上形成互连绕线图案层，所述互连绕线图案层的绕线图案与所述牺牲图案层的牺牲图案位置对应；
    在所述互连绕线图案层上形成第一绝缘层；
    在所述第一绝缘层上形成多个间隔设置的芯片，多个所述芯片分别与所述互连绕线图案层的互连绕线图案位置对应；
    去除所述支撑结构，在所述牺牲图案层一侧形成穿透所述牺牲图案、所述互连绕线图案和所述第一绝缘层的第一互连孔，所述第一互连孔还与投影位置对应的所述芯片的第一互连引脚对位连通。
  2. 如权利要求1所述的芯片互连封装方法，其特征在于，在所述牺牲图案层一侧形成穿透所述牺牲图案、所述互连绕线图案和所述第一绝缘层的第一互连孔，所述第一互连孔还与投影位置对应的所述芯片的第一互连引脚对位连通之后，所述方法还包括：
    在所述第一互连孔内形成导电材料，所述第一互连孔内的所述导电材料对所述互连绕线图案和所述芯片的第一互连引脚电连接。
  3. 如权利要求1或2所述的芯片互连封装方法，其特征在于，所述互连绕线图案的线宽为0.5微米至2微米，所述互连绕线图案的线距为0.5微米至2微米。
  4. 如权利要求1所述的芯片互连封装方法，其特征在于，所述在所述第一绝缘层上形成多个间隔设置的芯片之后，所述方法还包括：
    在多个所述芯片上形成塑封体。
  5. 如权利要求1至4任一项所述的芯片互连封装方法，其特征在于，在所述牺牲图案层一侧形成穿透所述牺牲图案、所述互连绕线图案和所述第一绝缘层的第一互连孔，所述第一互连孔还与投影位置对应的所述芯片的第一互连引脚对位连通之后，所述方法还包括：
    去除所述牺牲图案层，或，当所述牺牲图案层包括依次设置于所述互连绕线图案层上的绝缘牺牲层和金属牺牲层时，去除所述金属牺牲层。
  6. 如权利要求5所述的芯片互连封装方法，其特征在于，在所述去除所述牺牲图案层，或，当所述牺牲图案层包括依次设置于所述互连绕线图案层上的绝缘牺牲层和金属牺牲层时，去除所述金属牺牲层之后，所述方法还包括：
    在所述互连绕线图案层远离所述芯片的一侧形成第一封装绕线层；
    在所述第一封装绕线层一侧形成穿透所述第一封装绕线层的第二互连孔，所述第二互连孔还与投影位置对应的所述互连绕线图案对位连通。
  7. 如权利要求6所述的芯片互连封装方法，其特征在于，在所述牺牲图案层远离所述芯片的一侧形成第一封装绕线层之后，所述方法还包括：
    在所述第一封装绕线层一侧还形成穿透所述第一封装绕线层的第三互连孔，所述第三互连孔还与投影位置对应的所述芯片的第二互连引脚对位连通。
  8. 如权利要求6或7所述的芯片互连封装方法，其特征在于，在所述互连绕线案层远离所述芯片的一侧形成第一封装绕线层包括：
    在所述互连绕线图案层远离所述芯片的一侧形成第二绝缘层
    在所述第二绝缘层远离所述芯片一侧形成所述第一封装绕线图案层，所述第一封装绕线图案层的第一封装绕线图案与所述互连绕线图案位置对应。
  9. 如权利要求6至8任一项所述的芯片互连封装方法，其特征在于，在所述第一封装绕线层一侧形成穿透所述第一封装绕线层的第二互连孔，所述第二互连孔还与投影位置对应的所述绕线图案对位连通之后，所述方法还包括：
    在所述第一封装绕线层远离所述芯片的一侧形成有第二封装绕线层；
    在所述第二封装绕线层一侧形成穿透所述第二封装绕线层的第四互连孔，所述第四互连孔还与投影位置对应的所述第一封装绕线层对位连通。
  10. 如权利要求9所述的芯片互连封装方法，其特征在于，所述在所述第一封装绕线层远离所述芯片的一侧形成有第二封装绕线层包括：
    在所述第一封装绕线层远离所述芯片的一侧形成有第三绝缘层；
    在所述第三绝缘层远离所述芯片的一侧形成有第二封装绕线图案层。
  11. 如权利要求8所述的芯片互连封装方法，其特征在于，所述互连绕线图案的线宽小于所述第一封装绕线图案层的第一封装绕线图案的线宽；所述互连绕线图案的线距小于所述第一封装绕线图案层的第一封装绕线图案的线距。
  12. 如权利要求9所述的芯片互连封装方法，其特征在于，所述第一封装绕线图案层的第一封装绕线图案的线宽为2微米至5微米，所述第一封装绕线图案层的第一封装绕线图案的线距为2微米至5微米。
  13. 如权利要求10所述的芯片互连封装方法，其特征在于，所述第二封装绕线图案层的第二封装绕线图案的线宽大于5微米。
  14. 一种芯片互连封装结构，其特征在于，采用如权利要求1至13任一项所述的芯片互连封装方法制备，包括：
    在所述牺牲图案层上依次设置互连绕线图案层和多个芯片；所述互连绕线图案层的绕线图案与所述牺牲图案层的牺牲图案位置对应，多个芯片分别对应设置在与所述互连绕线图案层的互连绕线图案上；在所述牺牲图案层一侧开设穿透所述牺牲图案和所述互连绕线图案的第一互连孔，所述第一互连孔还与投影位置对应的所述芯片的第一互连引脚对位连通。
PCT/CN2021/076104 2021-02-08 2021-02-08 一种芯片互连封装结构及方法 WO2022165854A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US17/434,480 US20220254651A1 (en) 2021-02-08 2021-02-08 Chip interconnection package structure and method
CN202180001243.5A CN113169075B (zh) 2021-02-08 2021-02-08 一种芯片互连封装结构及方法
PCT/CN2021/076104 WO2022165854A1 (zh) 2021-02-08 2021-02-08 一种芯片互连封装结构及方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/076104 WO2022165854A1 (zh) 2021-02-08 2021-02-08 一种芯片互连封装结构及方法

Publications (1)

Publication Number Publication Date
WO2022165854A1 true WO2022165854A1 (zh) 2022-08-11

Family

ID=76876012

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/076104 WO2022165854A1 (zh) 2021-02-08 2021-02-08 一种芯片互连封装结构及方法

Country Status (3)

Country Link
US (1) US20220254651A1 (zh)
CN (1) CN113169075B (zh)
WO (1) WO2022165854A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242653B (zh) * 2022-02-21 2022-06-03 威海艾迪科电子科技股份有限公司 一种扇出封装结构及其形成方法
CN114420574B (zh) * 2022-03-31 2022-06-21 威海嘉瑞光电科技股份有限公司 一种柔性封装构件及其形成方法
CN115565888A (zh) * 2022-12-02 2023-01-03 广东省科学院半导体研究所 用于芯片粒精细线路的载板结构、封装结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105514071A (zh) * 2016-01-22 2016-04-20 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
US20160218082A1 (en) * 2015-01-22 2016-07-28 Qualcomm Incorporated Damascene re-distribution layer (rdl) in fan out split die application
CN106068558A (zh) * 2014-03-04 2016-11-02 高通股份有限公司 包括高密度互连和重分布层的集成器件
CN112262460A (zh) * 2018-04-10 2021-01-22 维斯普瑞公司 柔性基板上无焊料集成多个半导体裸片的方法和设备

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106068558A (zh) * 2014-03-04 2016-11-02 高通股份有限公司 包括高密度互连和重分布层的集成器件
US20160218082A1 (en) * 2015-01-22 2016-07-28 Qualcomm Incorporated Damascene re-distribution layer (rdl) in fan out split die application
CN105514071A (zh) * 2016-01-22 2016-04-20 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
CN112262460A (zh) * 2018-04-10 2021-01-22 维斯普瑞公司 柔性基板上无焊料集成多个半导体裸片的方法和设备

Also Published As

Publication number Publication date
CN113169075A (zh) 2021-07-23
US20220254651A1 (en) 2022-08-11
CN113169075B (zh) 2022-06-03

Similar Documents

Publication Publication Date Title
WO2022165854A1 (zh) 一种芯片互连封装结构及方法
TWI521669B (zh) 具有堆疊式封裝能力之半導體封裝件及其製作方法
KR101187214B1 (ko) 본드 패드를 통과하여 연장된 비아를 갖는 마이크로전자 소자를 포함하는 적층형 마이크로전자 어셈블리
TWI801531B (zh) 半導體結構與其形成方法
KR20190003403A (ko) 반도체 패키지 및 방법
TWI493674B (zh) 具有內建定位件、中介層、以及增層電路之複合線路板
TWI544599B (zh) 封裝結構之製法
TWI611534B (zh) 適用於可堆疊式半導體組體之具有凹穴的互連基板、其製作方法及垂直堆疊式半導體組體
TWI754839B (zh) 封裝結構及其形成方法
CN110518001B (zh) 半导体封装和制造工艺
US11469186B2 (en) Semiconductor device package and method for manufacturing the same
CN112054006A (zh) 半导体设备封装及其制造方法
CN112750810A (zh) 半导体封装件及制造方法
KR20210117186A (ko) 반도체 디바이스 및 반도체 디바이스 제조 방법
TWI578421B (zh) 可堆疊半導體封裝構造及其製造方法
JP2012253227A (ja) 配線基板及びその製造方法
TWI731619B (zh) 封裝結構及其形成方法
JP5125531B2 (ja) 配線基板及び半導体装置
US7067907B2 (en) Semiconductor package having angulated interconnect surfaces
JP4028211B2 (ja) 半導体装置
JP3893268B2 (ja) 半導体装置の製造方法
WO2022021018A1 (zh) 芯片精细线路扇出封装结构及其制作方法
CN206225357U (zh) 一种混合密度封装基板的结构
CN219917166U (zh) 半导体封装装置
KR20200071920A (ko) 반도체 패키지 및 그 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21923864

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21923864

Country of ref document: EP

Kind code of ref document: A1