WO2022021018A1 - 芯片精细线路扇出封装结构及其制作方法 - Google Patents

芯片精细线路扇出封装结构及其制作方法 Download PDF

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Publication number
WO2022021018A1
WO2022021018A1 PCT/CN2020/104923 CN2020104923W WO2022021018A1 WO 2022021018 A1 WO2022021018 A1 WO 2022021018A1 CN 2020104923 W CN2020104923 W CN 2020104923W WO 2022021018 A1 WO2022021018 A1 WO 2022021018A1
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Prior art keywords
chip
layer
fine
insulating layer
interconnection
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PCT/CN2020/104923
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English (en)
French (fr)
Inventor
燕英强
王垚
胡川
向迅
陈志涛
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广东省半导体产业技术研究院
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Application filed by 广东省半导体产业技术研究院 filed Critical 广东省半导体产业技术研究院
Priority to US18/015,576 priority Critical patent/US20230253333A1/en
Priority to CN202080100355.1A priority patent/CN115552577A/zh
Priority to PCT/CN2020/104923 priority patent/WO2022021018A1/zh
Publication of WO2022021018A1 publication Critical patent/WO2022021018A1/zh

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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Definitions

  • the present application relates to the field of chip technology, and in particular, to a chip fine circuit fan-out package structure and a manufacturing method thereof.
  • the present application provides a chip fine line fan-out package structure and a manufacturing method thereof, the purpose of which at least includes improving the problem that the existing chip fine line fan-out package structure is difficult to meet various needs of users.
  • the present application provides a chip fine line fan-out package structure, the fine line fan-out package structure includes a plurality of chips and a plurality of winding layers,
  • Chips include devices and pins, and pins include high-density inter-chip interconnect pins and low-density chip interconnect pins,
  • the multiple winding layers include a fine winding layer between chips and a package winding layer, and the line width and line spacing of the fine winding layer between chips is smaller than the line width and line spacing of the package winding layer.
  • the fine winding layer between chips connects the chips through high-density inter-chip pins,
  • the fabrication of fine-line fan-out package structures includes:
  • a first interconnection hole is prepared on the fine winding layer between chips, and a conductive material is arranged in the first interconnection hole to realize the electrical connection between the chip and the fine winding layer between the chips,
  • At least one encapsulation winding layer is fabricated on the first insulating layer, insulating layers are arranged between the encapsulation winding layers, and the encapsulation winding layers are connected to the chip or other winding layers through interconnection holes filled with conductive materials.
  • an adhesive layer is formed with an insulating adhesive material or an anisotropic conductive material, so that the pin side of the chip is attached to the fine wiring layer between the adjacent chips, and the pin of the chip and the fine wiring layer between the chips are attached. Precise alignment.
  • the first interconnection hole penetrates the first insulating layer, the fine winding layer between chips, and the adhesive layer to the high-density interchip pins of the chip, and the first interconnection hole is filled with conductive material;
  • the wire layer realizes high-density inter-chip pin electrical interconnection between different chips through the conductive material filled in the first interconnection hole.
  • the insulating layer includes a second insulating layer
  • the interconnection hole includes a second interconnection hole
  • the package winding layer includes a first package winding layer
  • the second insulating layer covers the first insulating layer and the first interconnection hole
  • the first encapsulation winding layer is arranged on the second insulating layer; the second interconnection hole or through the first insulating layer and the second insulating layer to the fine winding layer between chips, and/or through the second insulating layer, the first insulating layer layer, inter-chip fine wiring layer and adhesive layer to low-density chip interconnect pins, and only the sidewalls of the second interconnect hole are coated with conductive material to achieve the first package wiring layer and the inter-chip fine wiring layer and and/or Low Density Chip Interconnect pins are electrically interconnected.
  • the insulating layer further includes a third insulating layer
  • the interconnection hole further includes a third interconnection hole
  • the packaging wire layer further includes a second packaging wire layer
  • the third insulating layer covers the first packaging wire layer, and The material of the third insulating layer fills the second interconnection hole; the third interconnection hole penetrates through the third insulating layer, the second packaging wire layer is disposed on the third insulating layer, and is connected with the conductive material in the third interconnection hole through the third insulating layer.
  • the first package winding layer is electrically connected.
  • the line width and line spacing of the encapsulation winding layer is larger than that of the fine winding layer between chips, the fine winding layer between chips is 0.5-2 microns, and the line width and line spacing of the first packaging winding layer is 2-5 microns.
  • the line width of other package winding layers is more than 5 microns.
  • the materials of the first insulating layer and the insulating layers between the encapsulation winding layers include polyimide (Polyimide), benzocyclobutene (BCB), parylene, industrial liquid crystal polymer At least one of (LCP), epoxy resin, silicon oxide, silicon nitride, ceramic, aluminum oxide, glass.
  • the conductive material in the first interconnection hole, the second interconnection hole and the third interconnection hole is at least one of copper, aluminum, tungsten, conductive paste, tin-silver alloy, tin-silver-copper alloy, and gold-tin alloy. A sort of.
  • the present application provides a method for fabricating a chip fine circuit fan-out package structure, including:
  • a first insulating layer, an inter-chip fine winding layer and an adhesive layer are sequentially fabricated;
  • the pins of the chips include high-density inter-chip interconnect pins and low-density chip interconnect pins.
  • the winding layer is precisely aligned;
  • a first interconnection hole is opened on the first insulating layer, the first interconnection hole penetrates the first insulating layer, the fine wiring layer between chips and the adhesive layer and exposes the high-density interchip pins of the chip, and the first interconnection
  • the holes are filled with conductive material, so that the fine winding layer between chips is electrically connected with the high-density inter-chip pins of the chip;
  • a second insulating layer is coated on the first insulating layer, the second insulating layer covers the first insulating layer and the first interconnection holes, and a first package winding layer is prepared on the second insulating layer; second interconnection holes are prepared , the second interconnection hole penetrates through the first package wiring layer, the second insulating layer, the first insulating layer and the inter-chip fine wiring layer and exposes low-density chip interconnect pins, and/or, penetrates through the first package wiring layer, the second insulating layer, and the first insulating layer expose the fine wiring layer between chips; fill the conductive material in the second interconnection hole, and connect the low-density chip interconnection pins and the chip through the conductive material in the second interconnection hole The fine winding layer and the first package winding layer are electrically connected;
  • At least one insulating layer and at least one encapsulating winding layer are alternately prepared on the first package winding layer away from the chip, and interconnect holes are made on each insulating layer, and the interconnect holes are filled with conductive materials;
  • the conductive material in the hole forms an electrical connection between each package winding layer, and the line width and line spacing of the fine winding layers between chips are smaller than the line width and line spacing of each package winding layer;
  • the package winding layer farthest from the chip is provided with a pin pad, the solder mask layer is covered on the package winding layer farthest from the chip, and the solder mask layer covering at least part of the pin pad is removed; Disc planting solder balls.
  • the line width and line spacing of each winding layer including the fine winding layer between chips, the first packaging winding layer and other packaging winding layers gradually increases in the direction away from the chip.
  • the conductive material in the second interconnection hole electrically connects the low-density chip interconnection pins with the first package wiring layer, and/or electrically connects the fine wiring layer between chips and the first package wiring layer.
  • a conductive material is coated on the sidewall and bottom of the second interconnection hole, and the remaining space in the second interconnection hole is filled with the material of the third insulating layer, or the second interconnection hole is filled with the conductive material.
  • each interconnection hole with a conductive material, including:
  • the interconnection holes are formed by means of laser drilling, or are formed by means of photolithography and dry etching.
  • the winding layer includes the inter-chip fine wire layer and the packaging wire.
  • the two layers have different line widths and line spacings, so users can choose to use different winding layers according to actual needs. Therefore, the chip fine circuit fan-out packaging structure provided by the present application and the packaging structure prepared by the manufacturing method provided by the present application can meet the needs of users in more scenarios.
  • FIG. 1 is a schematic diagram of a chip fine circuit fan-out package structure in an embodiment of the present application
  • FIG. 2 is a flowchart of a method for manufacturing a chip fine circuit fan-out package structure in an embodiment of the present application
  • 3 to 15 are schematic diagrams of a chip fine circuit fan-out package structure in a manufacturing process according to an embodiment of the present application.
  • Icon 010-chip fine circuit fan-out package structure; 100-chip; 101-high-density chip interconnection pins; 102-low-density chip interconnection pins; 110-encapsulation material; 200-adhesive layer; 300 - fine wiring layer between chips; 400 - first insulating layer; 410 - first interconnection hole; 500 - second insulating layer; 510 - second interconnection hole; 600 - first package winding layer; 700 - first Three insulating layers; 710-third interconnection hole; 800-second package wiring layer; 900-solder resist layer; 910-solder ball; 020-temporary support material.
  • FIG. 1 is a schematic diagram of a chip fine circuit fan-out package structure 010 in an embodiment of the present application.
  • the chip fine circuit fan-out package structure 010 includes a chip 100 and a plurality of winding layers, and the plurality of winding layers includes an inter-chip fine wire layer 300 and a plurality of packaging wire layers, the chip 100 and the inter-chip fine wire layer 300 and A plurality of packaging winding layers are arranged overlappingly, and the pins of the chip 100 are electrically connected to the fine winding layer 300 between chips or at least one packaging winding layer through the electrical interconnection holes, and the fine winding layers 300 between chips or the packaging
  • the winding layers are all electrically connected to the chip 100 or at least one of the other package winding layers through electrically interconnected holes, and the fine winding layers 300 between chips have different line widths and line spacings from each package winding layer.
  • the line width and line spacing of the fine winding layers 300 between chips are smaller than the line width and line spacing of each package winding layer.
  • the number of chips 100 included in the chip fine circuit fan-out package structure 010 can be determined according to needs, such as two as shown in the figure, of course, it can also include one chip 100, and the chip 100 passes through the fine wiring layer 300 between chips or The package winding layer is connected to other components, or the chip fine circuit fan-out package structure 010 may include three or more chips 100 .
  • the different line widths and line spacings in the embodiments of the present application refer to: the line widths of different winding layers are different, and the line spacings of different winding layers are also different. As shown in FIG.
  • a chip fine circuit fan-out package structure 010 provided by an embodiment of the present application includes a chip 100 arranged layer by layer, an adhesive layer 200 , an inter-chip fine wiring layer 300 , a first insulating layer 400 , The second insulating layer 500 , the first packaging wiring layer 600 , the third insulating layer 700 , the second packaging wiring layer 800 , the solder resist layer 900 and the solder balls 910 .
  • the chip 100 is encapsulated by an encapsulation material 110 . As shown in FIG. 1 , the encapsulation material 110 can completely cover the chip 100 , or the top of the chip 100 can be exposed.
  • the multiple packaging winding layers only include the first packaging winding layer 600 and the second packaging winding layer 800.
  • the The number of layers may be 2, or may be 2 or more.
  • the inter-chip fine routing layer 300 is electrically connected to the high-density inter-chip interconnect pins 101 of the chip 100 through the first interconnection holes 410 .
  • the interconnection holes (including the first interconnection hole 410 , the second interconnection hole 510 , and the third interconnection hole 710 ) in the embodiments of the present application are all electrically conductive hole structures.
  • the inner wall and bottom of the hole or the conductive material (such as metal or other non-metal conductive material) filled in the interconnection hole enables the interconnection hole to realize the function of conducting electricity.
  • the first interconnection holes 410 pass through the lines of the inter-chip fine routing layer 300 and extend to the high-density inter-chip interconnection pins 101 of the chips 100 , and the first interconnection holes 410 are realized by electroplating copper. Electrically, it electrically connects the fine inter-chip wiring layer 300 with the high-density inter-chip interconnect pins 101 of the chip 100 .
  • the electroplated copper is filled in the first interconnection hole 410 , of course, in other optional embodiments, the electroplated copper may be only coated on the inner wall of the first interconnection hole 410 .
  • the first package wiring layer 600 is electrically connected to the inter-chip fine wiring layer 300 and/or the low-density chip interconnection pins of the chip 100 through the electrically conductive second interconnection holes 510 .
  • second interconnection holes 510 there are three types of second interconnection holes 510 , one is a line that passes through the second insulating layer 500 and the first insulating layer 400 , then passes through the fine wiring layer 300 between chips, and then passes through the fine wiring layer 300 between chips.
  • the pins of the chip 100 are reached through the adhesive layer 200, so that the first package wiring layer 600, the fine wiring layer 300 between the chips and the low-density chip interconnection pins 102 of the chip 100 are electrically connected;
  • the connecting hole 510 passes through the inter-chip fine wiring layer 300 but avoids the lines on the inter-chip fine wiring layer 300, and then passes through the adhesive layer 200 to reach the chip 100 pins, so as to realize the electrical connection between the first package winding layer 600 and the chip 100;
  • the third type of second interconnection hole 510 only electrically connects the first package winding layer 600 and the inter-chip fine winding layer 300 .
  • a third insulating layer 700 is spaced between the second packaging wiring layer 800 and the first packaging wiring layer 600 , and the second packaging wiring layer 800 can pass fine wiring between the chips through the electrical third interconnection holes 710
  • the second package wiring layer 800 and the first package wiring layer 600 are electrically connected through third interconnection holes 710 .
  • a solder resist layer 900 is prepared on the side of the second package wiring layer 800 away from the chip 100.
  • the solder resist layer 900 exposes part of the lines of the second package wiring layer 800 through the gap, and the solder balls 910 pass through the gap and the second package wiring layer. 800 line connection.
  • the line width and line spacing of each winding layer of the chip fine line fan-out package structure 010 are different.
  • the line width and line spacing are gradually increased.
  • the line width and line spacing of the fine wiring layer 300 between chips can be selected to be 0.5-2 ⁇ m
  • the line width and line spacing of the first package winding layer 600 can be selected to be 2-5 ⁇ m
  • the second The line width and line spacing of the encapsulation winding layer 800 can be selected to be more than 5 microns, which provides the user with a variety of alternative solutions, which can meet the different needs of the user.
  • the material of each winding layer can be selected from titanium, copper, silver or their alloys, the first insulating layer 400 and the insulating layers (including the first and second insulating layers) between the encapsulated winding layers
  • Materials of the insulating layer 500 and the third insulating layer 700) include polyimide, benzocyclobutene (BCB), parylene, industrialized liquid crystal polymer (LCP), epoxy resin, silicon At least one of oxide, silicon nitride, ceramic, aluminum oxide, glass.
  • the first insulating layer 400 may be a polymer (such as parylene epoxy), an inorganic material (such as silicon dioxide, silicon nitride, etc.), or a ceramic film (alumina, aluminum nitride, etc.) , silicon carbide, etc.).
  • the adhesive material may be an insulating DAF film or other insulating materials with an adhesive function.
  • the material of the second insulating layer 500 may be a permanent photoresist, a photoresist dry film, or a non-photosensitive polymer, an inorganic substance, a ceramic film, or the like.
  • the third insulating layer 700 may be a photosensitive/non-photosensitive material, and may be PI, BCB, parylene or epoxy (DAF film).
  • the conductive material filled in each interconnection hole may be metals such as copper, aluminum, tungsten, or anisotropic conductive adhesive, conductive paste, or alloys such as tin-silver, tin-silver-copper, and gold-tin.
  • the package structure may be a BGA or a surface mount package type (thus omitting the solder balls 910 and omitting the BGA ball mounting process).
  • the present application further provides a method for fabricating a chip fine line fan-out package structure, which can be used to prepare the chip fine line fan-out package structure 010 provided in the embodiment of the present application.
  • the manufacturing method includes: sequentially manufacturing a first insulating layer, an inter-chip fine winding layer and an adhesive layer on the surface of one side of the temporary support material; mounting a plurality of chips on the side of the adhesive layer away from the inter-chip fine wiring layer,
  • the pins of the chip include high-density inter-chip interconnect pins and low-density inter-chip interconnect pins.
  • the pins of the chip and the fine winding layers between the chips are precisely aligned; multiple chips are encapsulated with encapsulation materials and covered with adhesive. layer;
  • a second insulating layer is coated on the first insulating layer, the second insulating layer covers the first insulating layer and the first interconnection holes, and a first package winding layer is prepared on the second insulating layer; second interconnection holes are prepared , the second interconnection hole penetrates through the first package wiring layer, the second insulating layer, the first insulating layer and the inter-chip fine wiring layer and exposes low-density chip interconnect pins, and/or, penetrates through the first package wiring layer, the second insulating layer, and the first insulating layer expose the fine wiring layer between chips; fill the conductive material in the second interconnection hole, and connect the low-density chip interconnection pins and the chip through the conductive material in the second interconnection hole The fine winding layer and the first package winding layer are electrically connected;
  • At least one insulating layer and at least one encapsulating winding layer are alternately prepared on the first package winding layer away from the chip, and interconnect holes are made on each insulating layer, and the interconnect holes are filled with conductive materials;
  • the conductive material in the hole forms an electrical connection between each layer of package winding layers;
  • the package winding layer farthest from the chip is provided with a pin pad, the solder mask layer is covered on the package winding layer farthest from the chip, and the solder mask layer covering at least part of the pin pad is removed; Disc planting solder balls.
  • FIG. 2 is a flowchart of a method for fabricating a chip fine circuit fan-out package structure 010 according to an embodiment of the present application. As shown in Figure 2, in this embodiment, the manufacturing method includes:
  • Step S100 a first insulating layer, a fine wiring layer between chips and an adhesive layer are formed layer by layer on the temporary support material.
  • step S200 the chip is mounted on the side of the adhesive layer away from the fine winding layer between chips, and the high-density interconnection pins between chips and the fine winding layer between chips are precisely aligned.
  • Step S300 a first interconnection hole is opened on the first insulating layer, the first interconnection hole passes through the fine winding layer between chips and reaches the high-density interchip interconnection pins of the chip, and the first interconnection hole is electrically oriented, So that the fine wiring layer between chips is electrically connected with the high-density inter-chip interconnect pins of the chip.
  • Step S400 alternately preparing at least one insulating layer and at least one encapsulating winding layer on the first insulating layer, and electrically connecting each encapsulating winding layer to the pins of the chip through interconnect holes, and/or , which is electrically connected with the at least one encapsulation winding layer prepared previously, wherein the line width and line spacing of each encapsulation winding layer including the fine winding layers between chips are different.
  • the chip fine circuit fan-out package structure 010 with multi-layer winding layers can be produced by the production method provided in the embodiment of the present application, and the multi-layer winding layer includes the inter-chip fine wire layer 300 and the multi-layer package winding layer.
  • the inter-chip fine wiring layer 300 connects each chip, and its line width and line spacing are smaller than that of the package wiring layer. Because the package structure has winding layers with different line widths and line spacings, they are electrically connected to each other or to the pins of the chip 100 . Therefore, the chip fine circuit fan-out package structure 010 can meet the different needs of users.
  • 3 to 14 are schematic diagrams of the chip fine circuit fan-out package structure 010 in the manufacturing process according to an embodiment of the present application.
  • the above steps S100 to S400 are described below by taking the fabrication of the chip fine circuit fan-out package structure 010 in the embodiment of FIG. 1 as an example.
  • Step S100 a first insulating layer, a fine wiring layer between chips and an adhesive layer are formed layer by layer on the temporary support material.
  • step S100 may specifically include: preparing a first insulating layer 400 on the temporary support material 020; preparing an inter-chip fine wiring layer 300 on the first insulating layer 400 (as shown in FIG. 3 ); An adhesive material is prepared on the inter-chip fine wiring layer 300 to form an adhesive layer 200 (as shown in FIG. 4 ).
  • the material of the temporary support material 020 includes: metal, glass, silicon or ceramic. The temporary support material 020 is removed before opening the first interconnection holes 410 .
  • preparing the inter-chip fine wiring layer 300 on the first insulating layer 400 may specifically include: sputtering a metal material on the first insulating layer 400, and using photolithography and etching to form the inter-chip fine wiring layer 300 Alternatively, a seed layer is sputtered on the first insulating layer 400, and an inter-chip fine wiring layer 300 is formed by photolithography and copper electroplating processes.
  • the metal material and seed layer can be selected from titanium, copper, silver, or their alloys.
  • the photolithography includes forming the photoresist into a circuit pattern (by means of photolithography, etc.), and the etching includes removing the metal not covered by the photoresist by dry or wet methods, removing the photoresist, and forming the remaining metal between chips. Fine winding layer 300 .
  • step S200 a chip is mounted on the side of the adhesive layer away from the fine wiring layer between chips.
  • the side of the chip 100 with the pins is attached to the adhesive layer 200 .
  • the high-density inter-chip interconnect pins 101 and the low-density chip pins 102 of the chip 100 are finely wound between the chips.
  • the wire layer 300 has no electrical connection relationship.
  • the number of chips 100 can be selected as multiple.
  • the chip 100 is sealed with an encapsulation material. As shown in FIG. 6 , the chip 100 can be completely encapsulated; the upper surface of the chip 100 can also be exposed.
  • the temporary support material 020 used for support is removed to facilitate subsequent processing on the first insulating layer 400 , as shown in FIG. 7 .
  • Step S300 a first interconnection hole is opened on the first insulating layer, the first interconnection hole passes through the fine winding layer between chips and reaches the high-density interchip interconnection pins of the chip, and the first interconnection hole is electrically oriented, So that the fine wiring layer between chips is electrically connected with the high-density inter-chip interconnect pins of the chip.
  • a first interconnection hole 410 is opened on the first insulating layer 400 , and there are a plurality of first interconnection holes 410 , all of which are away from the side of the first insulating layer 400 away from the chip 100 (the lower part in FIG. 8 ). side) is opened to one side of the chip 100 , and the first interconnection hole 410 extends to the high-density inter-chip interconnection pin 101 of the chip 100 .
  • the first interconnection hole 410 is formed by means of laser drilling, or is formed by means of photolithography or dry etching. When opening the first interconnection hole 410 and subsequent steps, the structure shown in FIG. 8 can be turned over for processing.
  • the first interconnect hole 410 is then filled with conductive material to achieve electrical properties.
  • a specific manner of electrically characterizing the first interconnection hole 410 is to use a copper electroplating process to fill the first interconnection hole 410 with copper (as shown in FIG. 9 ).
  • the inner wall of the first interconnection hole 410 is covered with copper, which can also realize the electrical connection between the inter-chip fine wiring layer 300 and the high-density inter-chip interconnection pins 101 of the chip 100 .
  • Step S400 alternately preparing at least one insulating layer and at least one encapsulation winding layer on the first insulating layer, and interconnecting each encapsulation winding layer with the low-density chip pins of the chip through interconnection holes, And/or, at least one of the previously prepared winding layers is electrically connected.
  • Step S400 specifically includes: preparing a second insulating layer 500 on the side of the first insulating layer 400 away from the chip 100 ; opening a second interconnection hole 510 on the second insulating layer 500 , and the second interconnection hole 510 is lower than the chip 100 .
  • the density of chip pins and/or the fine wiring layer 300 between chips are connected; metal material is deposited on the second insulating layer 500, and the second interconnection hole 510 is electrically conductive, and the metal material on the second insulating layer 500 is electrically Etching is performed to form a first packaging wire layer 600; a third insulating layer 700 is prepared on the first packaging wire layer 600; a third interconnection hole 710 is opened on the third insulating layer 700, and the third interconnection hole 710 is connected The first packaging winding layer 600; depositing a metal material on the third insulating layer 700, making the third interconnection hole 710 electrically conductive, and etching the metal material on the third insulating layer 700 to form a second packaging winding Line layer 800 .
  • the second interconnection holes 510 are connected to the low-density chip pins of the chip 100 and/or the inter-chip fine wiring layer 300 , which means that the plurality of second interconnection holes 510 are all connected to the chip 100 .
  • the low-density chip pins are connected, or all of them are connected to the inter-chip fine wiring layer 300 , or some of them are connected to the low-density chip pins of the chip 100 , and the other part is connected to the inter-chip fine wiring layer 300 .
  • a second insulating layer 500 is first prepared on the first insulating layer 400 to cover the copper filled in the first interconnection holes 410 .
  • the second interconnection holes 510 have various forms: the first one is to extend only to the fine wiring layer 300 between chips, exposing part of the lines of the fine wiring layer 300 between chips; the second one is The lines passing through the inter-chip fine wiring layer 300 extend to the low-density chip pins 102 of the chip 100; the third type is that although it passes through the inter-chip fine wiring layer 300, it is not connected to the inter-chip fine wiring layer 300.
  • the direct electrical connection extends to the low-density chip interconnect pins 102 of the chip 100, and thus there is no line connection to the fine routing layer 300 between chips.
  • the three second interconnection holes 510 provide three interconnections.
  • a seed layer (titanium, copper or an alloy of the two) is magnetron sputtered on the second insulating layer 500 .
  • photoresist is applied, photolithography is performed (the second interconnection hole 510 and the circuit pattern are exposed after exposure and development), and copper is plated with a copper electroplating process, which makes the second interconnection hole 510 electrically conductive (in FIG. 12 ). Only the inner wall of the second interconnection hole 510 is covered with copper), and the circuit portion of the first package wiring layer 600 is also plated with copper.
  • the photoresist is removed to expose the seed layer, and this part of the seed layer is removed by a dry method or a wet method to obtain a first package wire layer 600, as shown in FIG. 13 .
  • a third insulating layer 700 is prepared on the first packaging wire layer 600 , and a part of the material of the third insulating layer 700 fills the second interconnection holes 510 . Then, a third interconnection hole 710 is opened on the third insulating layer 700 , and the third interconnection hole 710 is connected to the lines of the first package winding layer 600 .
  • the opening method of the third interconnection hole 710 is similar to that of the first interconnection hole 410 and will not be repeated here.
  • a metal material is deposited on the third insulating layer 700 , and the third interconnection hole 710 is electrically conductive, and the metal material on the third insulating layer 700 is etched to form a second packaging wire layer 800.
  • the manner of fabricating the second package wiring layer 800 and electrically electrifying the third interconnection hole 710 is similar to the manner of fabricating the first encapsulation wiring layer 600 and electrically electrifying the second interconnection hole 510, except that when The third interconnection hole 710 is completely filled with copper when the third interconnection hole 710 is electrically treated by the copper electroplating process.
  • the manufacturing method of the embodiment of the present application further includes preparing a solder resist layer 900 on the package winding layer farthest from the chip 100 , the solder resist layer 900 forms a gap, and through the gap formed by the solder resist layer 900 , the solder balls 910 are connected to the most distant
  • the package winding layer of the chip 100 finally obtains the chip fine circuit fan-out package structure 010 as shown in FIG. 1 .
  • the second packaging wiring layer 800 is the packaging wiring layer farthest from the chip 100 , and is also the packaging wiring layer with the widest line width and line spacing. Therefore, a solder resist layer 900 is provided on the second package wiring layer 800 , and the solder balls 910 are connected to the lines of the second package wiring layer 800 to realize electrical connection with the second package wiring layer 800 .
  • the second package wiring layer 800 may also be connected to the low-density chip pins 102 of the chip 100 or to the fine wiring layer 300 between chips.
  • the process of making each interconnection hole electrically conductive may be: physical vapor deposition, electroless plating, chemical vapor deposition process to prepare the interconnection hole seed layer, and then use electroless plating or electroplating process Fill conductive metal; alternatively, fill interconnect holes with conductive paste, solder paste, silver paste, etc. using stencil or screen printing.
  • a chip fine line fan-out package structure With the method for fabricating a chip fine line fan-out package structure provided by the embodiment of the present application, not only a chip fine line fan-out package structure with a plurality of interconnecting winding layers with different line widths and line spacings can be fabricated, so as to satisfy various requirements of users. need.
  • insulating materials and processing technology it is possible to optimize the stress size and distribution of the fan-out package structure of chip fine lines, optimize thermal resistance characteristics, and optimize electrical measurement characteristics, thereby improving the performance and performance of chip fine line fan-out package structures. reliability.
  • the chip fine circuit fan-out package structure provided by the present application and the package structure obtained by the manufacturing method provided by the present application enable users to select winding layers with different line widths and line spacings for signal transmission during use, which can meet the needs of users in more Use requirements in multiple scenarios.

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Abstract

本申请的实施例提供了一种芯片精细线路扇出封装结构及其制作方法，涉及芯片技术领域。本申请实施例提供的芯片精细线路扇出封装结构，以及本申请实施例提供的制作方法制作得到的芯片精细线路扇出封装结构，包括芯片间精细绕线层和封装绕线层，芯片间精细绕线层的线宽线距小于封装绕线层的线宽线距，因此用户可以根据实际需要选择使用不同的封装绕线层。因此，本申请提供的芯片精细线路扇出封装结构以及本申请提供的制作方法所制得的封装结构能够满足用户在更多场景下的使用需求。

Description

芯片精细线路扇出封装结构及其制作方法 技术领域
本申请涉及芯片技术领域，具体而言，涉及一种芯片精细线路扇出封装结构及其制作方法。
背景技术
5G移动互联网、人工智能、物联网、自动驾驶、高性能计算等技术的发展，要求集成电路等半导体器件被广泛地应用。并且根据使用的场景和需求不同，对电路的传输速率、功耗等指标也有不同的要求。但现有的芯片精细线路扇出封装结构，难以满足用户的多种使用需求。
发明内容
本申请提供一种芯片精细线路扇出封装结构及其制作方法，目的至少包括，改善现有的芯片精细线路扇出封装结构难以满足用户多种需求的问题。
本申请的实施例可以这样实现：
第一方面，本申请提供一种芯片精细线路扇出封装结构，精细线路扇出封装结构包括多个芯片以及多个绕线层，
芯片包括器件和引脚，引脚包括高密度芯片间互连引脚和低密度芯片互连引脚，
多个绕线层包括芯片间精细绕线层和封装绕线层，芯片间精细绕线层的线宽线距小于封装绕线层的线宽线距，
芯片间精细绕线层通过高密度芯片间引脚连接芯片，
精细线路扇出封装结构的制造包括：
在临时支撑材料上铺设第一绝缘层，并在第一绝缘层上生长芯片间精细绕线层，
使用粘合材料完成多个芯片和芯片间精细绕线层管脚对位贴合、固化，对芯片进行塑封，然后去除临时支撑材料，
在芯片间精细绕线层上制备第一互连孔，在第一互连孔内设置导电材料以实现芯片与芯片间精细绕线层的电连接，
在第一绝缘层上制作至少一层封装绕线层，各封装绕线层之间设置有绝缘层，封装绕线层通过填充有导电材料的互连孔连接芯片或者其他绕线层。
可选的，用绝缘粘合材料或异向导电材料形成粘合层，以将芯片的引脚一侧贴合在最 邻近芯片间精细绕线层上，芯片引脚和芯片间精细绕线层精确对位。
可选的，第一互连孔贯穿第一绝缘层、芯片间精细绕线层和粘合层至芯片的高密度芯片间引脚，第一互连孔内填充有导电材料；芯片间精细绕线层通过第一互连孔内填充的导电材料实现不同芯片之间的高密度芯片间引脚电互连。
可选的，绝缘层包括第二绝缘层，互连孔包括第二互连孔，封装绕线层包括第一封装绕线层，第二绝缘层覆盖第一绝缘层和第一互连孔，第一封装绕线层设置于第二绝缘层；第二互连孔或贯穿第一绝缘层和第二绝缘层至芯片间精细绕线层，和/或，贯穿第二绝缘层、第一绝缘层、芯片间精细绕线层和粘合层至低密度芯片互连引脚，第二互连孔内仅侧壁涂覆导电材料以实现第一封装绕线层与芯片间精细绕线层和/或低密度芯片互连引脚电互连。
可选的，绝缘层还包括第三绝缘层，互连孔还包括第三互连孔，封装绕线层还包括第二封装绕线层，第三绝缘层覆盖第一封装绕线层，并且第三绝缘层的材料填满第二互连孔；第三互连孔贯穿第三绝缘层，第二封装绕线层设置于第三绝缘层，并通过第三互连孔内的导电材料与第一封装绕线层电连接。
可选的，封装绕线层的线宽线距大于芯片间精细绕线层，芯片间精细绕线层为0.5-2微米，第一封装绕线层线宽线距为2-5微米。
可选的，包括芯片间精细绕线层和封装绕线层在内的所有的绕线层的线宽线距，在远离芯片的方向上逐渐增大，除第一封装绕线层之外的其他封装绕线层的线宽为5微米以上。
可选的，第一绝缘层以及各封装绕线层之间的绝缘层的材料包括聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、工业化液晶聚合物(LCP)、环氧树脂、硅氧化、硅氮化物、陶瓷、铝氧化物、玻璃中的至少一种。
可选的，第一互连孔、第二互连孔以及第三互连孔内的导电材料为铜、铝、钨、导电膏、锡银合金、锡银铜合金、金锡合金中的至少一种。
第二方面，本申请提供一种芯片精细线路扇出封装结构的制作方法，包括：
在临时支撑材料一侧表面上依次制作第一绝缘层、芯片间精细绕线层以及粘合层；
在粘合层远离芯片间精细绕线层的一侧贴装多个芯片，芯片的引脚包括高密度芯片间互连引脚和低密度芯片互连引脚，芯片的引脚和芯片间精细绕线层精确对位；
用包封材料包封住多个芯片并覆盖粘合层；
去除临时支撑材料；
在第一绝缘层上开设第一互连孔，第一互连孔贯穿第一绝缘层、芯片间精细绕线层和粘合层并露出芯片的高密度芯片间引脚，在第一互连孔填充导电材料，以使芯片间精细绕线层与芯片的高密度芯片间引脚电连接；
在第一绝缘层上再涂覆第二绝缘层，第二绝缘层覆盖第一绝缘层和第一互连孔，在第 二绝缘层上制备第一封装绕线层；制备第二互连孔，第二互连孔贯穿第一封装绕线层、第二绝缘层、第一绝缘层和芯片间精细绕线层并露出低密度芯片互连引脚，和/或，贯穿第一封装绕线层、第二绝缘层、第一绝缘层露出芯片间精细绕线层；在第二互连孔内填充导电材料，并通过第二互连孔内导电材料将低密度芯片互连引脚与芯片间精细绕线层、第一封装绕线层电连接；
在第一封装绕线层远离芯片方向再交替地制备至少一层绝缘层和至少一层封装绕线层，每层绝缘层上制作互连孔，互连孔内填充导电材料；并通过互连孔内导电材料将每层封装绕线层间形成电连接，芯片间精细绕线层的线宽线距小于各个封装绕线层的线宽线距；
最远离芯片的封装绕线层设置有引脚焊盘，在最远离芯片的封装绕线层上覆盖阻焊层，去掉至少部分覆盖在引脚焊盘上的阻焊层；并且在引脚焊盘种植焊料球。
可选的，包括芯片间精细绕线层、第一封装绕线层以及其他封装绕线层在内的各绕线层的线宽线距在远离芯片的方向上逐渐增大。
可选的，第二互连孔内导电材料将低密度芯片互连引脚与第一封装绕线层电连接，和/或使芯片间精细绕线层与第一封装绕线层电连接。
可选的，在第二互连孔侧壁和底部涂覆导电材料，第二互连孔内剩余空间用第三绝缘层的材料填满，或者，第二互连孔内填满导电材料。
可选的，在各个互连孔内填充导电材料，包括：
在互连孔侧壁和底部上磁控溅射或化学镀种子层金属，利用电镀工艺在互连孔内填充导电材料；或用丝网/钢网印刷导电材料的方法在互连孔内填满导电材料。
可选的，互连孔采用激光打孔的方式形成，或者，采用光刻和干法蚀刻的方式形成。
本申请实施例的有益效果例如包括：
本申请实施例提供的芯片精细线路扇出封装结构，以及本申请实施例提供的制作方法制作得到的芯片精细线路扇出封装结构，其绕线层包含了芯片间精细绕线层和封装绕线层，二者线宽线距不同，因此用户可以根据实际需要选择使用不同的绕线层。因此，本申请提供的芯片精细线路扇出封装结构以及本申请提供的制作方法所制得的封装结构能够满足用户在更多场景下的使用需求。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请一种实施例中芯片精细线路扇出封装结构的示意图；
图2为本申请一种实施例中芯片精细线路扇出封装结构的制作方法的流程图；
图3至图15为本申请一种实施例中芯片精细线路扇出封装结构在制作过程中的示意图。
图标：010-芯片精细线路扇出封装结构；100-芯片；101-高密度芯片间互连引脚；102-低密度芯片互连引脚；110-包封材料；200-粘合层；300-芯片间精细绕线层；400-第一绝缘层；410-第一互连孔；500-第二绝缘层；510-第二互连孔；600-第一封装绕线层；700-第三绝缘层；710-第三互连孔；800-第二封装绕线层；900-阻焊层；910-焊料球；020-临时支撑材料。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该发明产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，若出现术语“第一”、“第二”、“第三”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
需要说明的是，在不冲突的情况下，本申请的实施例中的特征可以相互结合。
图1为本申请一种实施例中芯片精细线路扇出封装结构010的示意图。芯片精细线路扇出封装结构010包括芯片100以及多个绕线层，多个绕线层包括芯片间精细绕线层300和多个封装绕线层，芯片100与芯片间精细绕线层300以及多个封装绕线层重叠设置，并且芯片100的引脚通过电性化的互连孔与芯片间精细绕线层300或至少一个封装绕线层电连接，芯片间精细绕线层300或封装绕线层均通过电性化的互连孔与芯片100或者其余封 装绕线层中的至少一个电连接，芯片间精细绕线层300与各个封装绕线层的线宽线距不同，具体的，芯片间精细绕线层300的线宽线距小于各个封装绕线层的线宽线距。芯片精细线路扇出封装结构010所包含的芯片100的数量可以根据需要进行确定，如图中所示的两个，当然也可以包含一个芯片100，该芯片100通过芯片间精细绕线层300或封装绕线层与其他元器件连接，或者该芯片精细线路扇出封装结构010可以包含三个或者三个以上芯片100。应理解，本申请实施例中线宽线距不同是指：不同的绕线层的线宽不同，并且不同的绕线层的线距也不同。如图1所示，本申请的一种实施例提供的芯片精细线路扇出封装结构010包括逐层排列的芯片100、粘合层200、芯片间精细绕线层300、第一绝缘层400、第二绝缘层500、第一封装绕线层600、第三绝缘层700、第二封装绕线层800、阻焊层900以及焊料球910。芯片100由包封材料110封装起来，可以如图1中所示，包封材料110完全包覆芯片100，也可以露出芯片100的顶部。应当理解，在本实施例中，多个封装绕线层仅包含了第一封装绕线层600和第二封装绕线层800，在本申请可选的其他实施例中，封装绕线层的层数可以为2层，也可以为2层及以上。
在可选的实施例中，芯片间精细绕线层300通过第一互连孔410与芯片100的高密度芯片间互连引脚101电连接。应当理解，本申请实施例中的互连孔(包括第一互连孔410、第二互连孔510、第三互连孔710)均为电性化的孔结构，通过涂覆于互连孔内壁、底部或者填充于互连孔内的导电材料(比如金属或其他非金属导电材料)，使互连孔实现导电的功能。可选的，第一互连孔410穿过芯片间精细绕线层300的线路，并延伸到芯片100的高密度芯片间互连引脚101处，第一互连孔410通过电镀铜来实现电性化，使其将芯片间精细绕线层300与芯片100高密度芯片间互连引脚101电连接。在图1的实施例中，电镀的铜填充于第一互连孔410，当然，在可选的其他实施例中，电镀的铜也可以仅仅涂覆于第一互连孔410的内壁。
第一封装绕线层600通过电性化的第二互连孔510与芯片间精细绕线层300和/或芯片100的低密度芯片互连引脚电连接。如图1中所示，第二互连孔510有三种类型，一种是穿过第二绝缘层500、第一绝缘层400之后，又穿过芯片间精细绕线层300的线路，再穿过粘合层200到达芯片100的引脚，这样便将第一封装绕线层600、芯片间精细绕线层300以及芯片100低密度芯片互连引脚102电连接；另一种第二互连孔510是穿过第二绝缘层500、第一绝缘层400之后，经过芯片间精细绕线层300但避让开芯片间精细绕线层300上的线路，再穿过粘合层200到达芯片100的引脚，这样便实现第一封装绕线层600和芯片100的电连接；第三种第二互连孔510仅仅将第一封装绕线层600和芯片间精细绕线层300电连接。
第二封装绕线层800与第一封装绕线层600之间间隔有第三绝缘层700，第二封装绕线 层800可以通过电性化的第三互连孔710与芯片间精细绕线层300、第一封装绕线层600和/或芯片100的引脚连接。如图1中所示，在一种可选的实施例中，第二封装绕线层800与第一封装绕线层600通过第三互连孔710实现电连接。
第二封装绕线层800远离芯片100的一侧制备有阻焊层900，阻焊层900通过间隙露出部分第二封装绕线层800的线路，焊料球910通过间隙与第二封装绕线层800的线路连接。
在本申请实施例中，芯片精细线路扇出封装结构010的各个绕线层的线宽线距不同。可选的，在远离芯片100的方向上，线宽线距逐渐增加。具体到图1实施例中，芯片间精细绕线层300的线宽线距可选为0.5-2微米，第一封装绕线层600的线宽线距可选为2-5微米，第二封装绕线层800的线宽线距可选为5微米以上，这样给用户提供了多种可选择的方案，能够满足用户的不同需要。
在本申请可选的实施例中，各个绕线层的材料可选为钛、铜、银或者他们的合金，第一绝缘层400以及各封装绕线层之间的绝缘层(包括第一二绝缘层500和第三绝缘层700)的材料包括聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、工业化液晶聚合物(LCP)、环氧树脂、硅氧化、硅氮化物、陶瓷、铝氧化物、玻璃中的至少一种。在本实施例中，第一绝缘层400可以是聚合物(比如聚对二甲苯环氧树脂)、无机材料(比如二氧化硅、氮化硅等)，或者陶瓷薄膜(氧化铝、氮化铝、碳化硅等)。粘合材料可选为绝缘的DAF膜或者其他具有粘合功能的绝缘材料。第二绝缘层500的材料可以是永久性光刻胶、光阻干膜，也可以是非光敏性聚合物、无机物、陶瓷薄膜等。第三绝缘层700可以是光敏/非光敏材料，可以是PI、BCB、派瑞林或者环氧树脂(DAF膜)。各个互连孔所填充的导电材料可以是铜、铝、钨等金属，或者异向导电胶、导电膏，或者锡银、锡银铜、金锡等合金。
当然，该封装结构可以是BGA，也可是表面贴装封装类型(从而省去焊料球910，省去BGA植球工艺)。
本申请还提供一种芯片精细线路扇出封装结构的制作方法，可以用于制备本申请实施例提供的芯片精细线路扇出封装结构010。制作方法包括：在临时支撑材料一侧表面上依次制作第一绝缘层、芯片间精细绕线层以及粘合层；在粘合层远离芯片间精细绕线层的一侧贴装多个芯片，芯片的引脚包括高密度芯片间互连引脚和低密度芯片互连引脚，芯片的引脚和芯片间精细绕线层精确对位；用包封材料包封住多个芯片并覆盖粘合层；
去除临时支撑材料；在第一绝缘层上开设第一互连孔，第一互连孔贯穿第一绝缘层、芯片间精细绕线层和粘合层并露出芯片的高密度芯片间引脚，在第一互连孔填充导电材料，以使芯片间精细绕线层与芯片的高密度芯片间引脚电连接；
在第一绝缘层上再涂覆第二绝缘层，第二绝缘层覆盖第一绝缘层和第一互连孔，在第 二绝缘层上制备第一封装绕线层；制备第二互连孔，第二互连孔贯穿第一封装绕线层、第二绝缘层、第一绝缘层和芯片间精细绕线层并露出低密度芯片互连引脚，和/或，贯穿第一封装绕线层、第二绝缘层、第一绝缘层露出芯片间精细绕线层；在第二互连孔内填充导电材料，并通过第二互连孔内导电材料将低密度芯片互连引脚与芯片间精细绕线层、第一封装绕线层电连接；
在第一封装绕线层远离芯片方向再交替地制备至少一层绝缘层和至少一层封装绕线层，每层绝缘层上制作互连孔，互连孔内填充导电材料；并通过互连孔内导电材料将每层封装绕线层间形成电连接；
最远离芯片的封装绕线层设置有引脚焊盘，在最远离芯片的封装绕线层上覆盖阻焊层，去掉至少部分覆盖在引脚焊盘上的阻焊层；并且在引脚焊盘种植焊料球。
图2为本申请一种实施例中芯片精细线路扇出封装结构010的制作方法的流程图。如图2所示，在本实施例中，制作方法包括：
步骤S100，在临时支撑材料上逐层排列的制作第一绝缘层、芯片间精细绕线层以及粘合层。
步骤S200，在粘合层远离芯片间精细绕线层的一侧贴装芯片，高密度芯片间互连引脚与芯片间精细绕线层精确对位。
步骤S300，在第一绝缘层上开设第一互连孔，第一互连孔经过芯片间精细绕线层并到达芯片的高密度芯片间互连引脚，电性化第一互连孔，以使芯片间精细绕线层与芯片的高密度芯片间互连引脚电连接。
步骤S400，在第一绝缘层上再交替地制备至少一层绝缘层和至少一层封装绕线层，并通过互连孔将每层封装绕线层与芯片的引脚电连接，和/或，与在先制备的至少一层封装绕线层电连接，其中，包括芯片间精细绕线层在内的各封装绕线层的线宽线距不同。
通过本申请实施例提供的制作方法可以制作出具有多层绕线层的芯片精细线路扇出封装结构010，多层绕线层中包括芯片间精细绕线层300和多层封装绕线层，芯片间精细绕线层300连接了各个芯片，并且其线宽线距小于封装绕线层。由于该封装结构具有了不同线宽线距的绕线层，且相互电连接或者与芯片100的引脚连接。因此该芯片精细线路扇出封装结构010可以满足用户的不同需求。
图3至图14为本申请一种实施例中芯片精细线路扇出封装结构010在制作过程中的示意图。下面以制作图1实施例的芯片精细线路扇出封装结构010为例，对上述步骤S100～S400进行介绍。
步骤S100，在临时支撑材料上逐层排列的制作第一绝缘层、芯片间精细绕线层以及粘合层。
在可选的实施例中，步骤S100可以具体包括：在临时支撑材料020上制备第一绝缘层400；在第一绝缘层400上制备芯片间精细绕线层300(如图3所示)；在芯片间精细绕线层300上制备粘合材料形成粘合层200(如图4所示)。可选的，临时支撑材料020的材质包括：金属、玻璃、硅或陶瓷。临时支撑材料020在开设第一互连孔410之前去除。
可选的，在第一绝缘层400上制备芯片间精细绕线层300，具体可以包括：在第一绝缘层400上溅射金属材料，采用光刻、蚀刻方式形成芯片间精细绕线层300；或者，在第一绝缘层400上溅射种子层，采用光刻、电镀铜工艺形成芯片间精细绕线层300。金属材料和种子层可以选用钛、铜、银，或者它们的合金。其中的光刻包括将光刻胶形成线路图案(通过光刻等手段)，蚀刻包括利用干法或者湿法去除未被光刻胶覆盖的金属，除去光刻胶，剩下的金属形成芯片间精细绕线层300。
步骤S200，在粘合层远离芯片间精细绕线层的一侧贴装芯片。
如图5所示，将芯片100具有引脚的一侧贴在粘合层200上，此时芯片100的高密度芯片间互连引脚101和低密度芯片引脚102都与芯片间精细绕线层300无电连接关系。芯片100的数量可选为多个。贴装芯片100之后，用包封材料封住芯片100，如图6所示，可以完全包裹芯片100；也可以露出芯片100的上表面。封装好之后，去除掉作为支撑用的临时支撑材料020，以方便后续在第一绝缘层400上进行加工，如图7所示。
步骤S300，在第一绝缘层上开设第一互连孔，第一互连孔经过芯片间精细绕线层并到达芯片的高密度芯片间互连引脚，电性化第一互连孔，以使芯片间精细绕线层与芯片的高密度芯片间互连引脚电连接。
如图8所示，在第一绝缘层400上开设第一互连孔410，第一互连孔410为多个，均从第一绝缘层400远离芯片100的一侧(图8中的下侧)向芯片100一侧开设，第一互连孔410延伸到芯片100的高密度芯片间互连引脚101。可选的，第一互连孔410采用激光打孔的方式形成，或者，采用光刻、干法蚀刻的方式形成。在开设第一互连孔410时，以及后续的步骤，均可以将图8所示的结构翻转，以便加工。
然后对第一互连孔410填充导电材料实现电性化。可选的，电性化第一互连孔410的具体方式是采用电镀铜工艺，将铜填充在第一互连孔410中(如图9所示)。当然，在可选的实施方式中，用铜覆盖在第一互连孔410的内壁，也能够实现芯片间精细绕线层300和芯片100的高密度芯片间互连引脚101电连接。
步骤S400，在第一绝缘层上再交替地制备至少一层绝缘层和至少一层封装绕线层，并通过互连孔将每层封装绕线层与芯片的低密度芯片互连引脚，和/或，在先制备的至少一层绕线层电连接。
制作图1中的芯片精细线路扇出封装结构010为例，在第一绝缘层400上制备了两层 绝缘层和两层封装绕线层。步骤S400具体包括：在第一绝缘层400远离芯片100的一侧制备第二绝缘层500；在第二绝缘层500上开设第二互连孔510，第二互连孔510与芯片100的低密度芯片引脚和/或芯片间精细绕线层300相连；在第二绝缘层500上淀积金属材料，并使第二互连孔510电性化，对第二绝缘层500上的金属材料进行蚀刻，形成第一封装绕线层600；在第一封装绕线层600上制备第三绝缘层700；在第三绝缘层700上开设第三互连孔710，第三互连孔710连接第一封装绕线层600；在第三绝缘层700上淀积金属材料，并使第三互连孔710电性化，对第三绝缘层700上的金属材料进行蚀刻，形成第二封装绕线层800。应当理解，在本申请中，第二互连孔510与芯片100的低密度芯片引脚和/或芯片间精细绕线层300相连，是指多个第二互连孔510均与芯片100的低密度芯片引脚相连，或者均与芯片间精细绕线层300相连，或者其中的部分与芯片100的低密度芯片引脚相连，另一部分与芯片间精细绕线层300相连。
如图10所示，首先在第一绝缘层400上制备了第二绝缘层500，将第一互连孔410中填充的铜覆盖。
如图11所示，然后在第二绝缘层500上开设了多个第二互连孔510，开设方式与第一互连孔410类似，此处不再赘述。如图11中所示，第二互连孔510具有多种形态：第一种为仅延伸至芯片间精细绕线层300，暴露出部分芯片间精细绕线层300的线路；第二种为穿过芯片间精细绕线层300的线路，延伸至芯片100的低密度芯片引脚102；第三种是虽穿过了芯片间精细绕线层300，但不与芯片间精细绕线层300的直接电连接，延伸至芯片100的低密度芯片互连引脚102，因此没有与芯片间精细绕线层300的线路连接。这三种第二互连孔510提供了三种互连方式。
如图12所示，开设了第二互连孔510之后，在第二绝缘层500上磁控溅射种子层(钛、铜或二者的合金)。然后涂覆光刻胶，进行光刻(曝光、显影后露出第二互连孔510以及线路图案)，用电镀铜工艺镀铜，该过程使第二互连孔510电性化(图12中仅令铜覆盖于第二互连孔510的内壁)，同时也令第一封装绕线层600的线路部分被镀铜。然后，去除光刻胶，暴露出种子层，利用干法或者湿法去除这部分种子层，得到第一封装绕线层600，如图13所示。
如图14所示，在第一封装绕线层600上制备第三绝缘层700，第三绝缘层700的部分材料将第二互连孔510填充。然后在第三绝缘层700上开设第三互连孔710，第三互连孔710连接第一封装绕线层600的线路。第三互连孔710开设方式与第一互连孔410类似此处不再赘述。
如图15所示，在第三绝缘层700上淀积金属材料，并使第三互连孔710电性化，对第三绝缘层700上的金属材料进行蚀刻，形成第二封装绕线层800。制作第二封装绕线层800 以及使第三互连孔710电性化的方式与制作第一封装绕线层600和电性化第二互连孔510的方式类似，不同之处在于，当利用电镀铜工艺对第三互连孔710进行电性化时，将第三互连孔710用铜完全填充。本申请实施例的制作方法还包括在最远离芯片100的封装绕线层上制备阻焊层900，阻焊层900形成间隙，通过阻焊层900形成的间隙，将焊料球910连接至最远离芯片100的封装绕线层，最终得到如图1所示的芯片精细线路扇出封装结构010。在图14中，第二封装绕线层800即是最远离芯片100的一个封装绕线层，也是线宽线距最宽的封装绕线层。因此在第二封装绕线层800上设置阻焊层900，焊料球910连接到第二封装绕线层800的线路上，实现与第二封装绕线层800电连接。
应当理解，在可选的其他实施例中，第二封装绕线层800也可以与芯片100的低密度芯片引脚102连接，或者与芯片间精细绕线层300连接。
应当注意，在本实施例中，使各互连孔实现电性化的工艺可以是：物理气相淀积、化学镀、化学气相淀积工艺制备互连孔种子层，然后采用化学镀或电镀工艺填充导电金属；或者，采用钢网或丝网印刷在互连孔内填充导电膏、焊锡膏、银胶等。
通过本申请实施例提供的芯片精细线路扇出封装结构的制作方法，不仅可以制作出具有多个不同线宽线距互连绕线层的芯片精细线路扇出封装结构，以满足用户的多种需求。同时，通过绝缘材料的选择、加工工艺的选择，能够优化芯片精细线路扇出封装结构的应力大小和分布，优化热阻特性，优化电测特性，从而提高芯片精细线路扇出封装结构的性能和可靠性。
工业实用性
本申请提供的芯片精细线路扇出封装结构以及本申请提供的制作方法所制得的封装结构，使得用户在使用时可以选择不同线宽线距的绕线层进行信号传输，能够满足用户在更多场景下的使用需求。

Claims (15)

  1. 一种芯片精细线路扇出封装结构，其特征在于，所述精细线路扇出封装结构包括多个芯片以及多个绕线层，
    所述芯片包括器件和引脚，所述引脚包括高密度芯片间互连引脚和低密度芯片互连引脚，
    所述多个绕线层包括芯片间精细绕线层和封装绕线层，所述芯片间精细绕线层的线宽线距小于所述封装绕线层的线宽线距，
    所述芯片间精细绕线层通过所述高密度芯片间引脚连接所述芯片，
    所述精细线路扇出封装结构的制造包括：
    在临时支撑材料上铺设第一绝缘层，并在所述第一绝缘层上生长所述芯片间精细绕线层，
    使用粘合材料完成所述多个芯片和所述芯片间精细绕线层管脚对位贴合、固化，对所述芯片进行塑封，然后去除所述临时支撑材料，
    在所述芯片间精细绕线层上制备第一互连孔，在所述第一互连孔内设置导电材料以实现所述芯片与所述芯片间精细绕线层的电连接，
    在所述第一绝缘层上制作至少一层所述封装绕线层，各所述封装绕线层之间设置有绝缘层，所述封装绕线层通过填充有导电材料的互连孔连接所述芯片或者其他绕线层。
  2. 根据权利要求1所述的芯片精细线路扇出封装结构，其特征在于，用绝缘粘合材料或异向导电材料形成粘合层，以将所述芯片的引脚一侧贴合在最邻近所述芯片间精细绕线层上，所述芯片引脚和所述芯片间精细绕线层精确对位。
  3. 根据权利要求2所述的芯片精细线路扇出封装结构，其特征在于，
    所述第一互连孔贯穿所述第一绝缘层、所述芯片间精细绕线层和所述粘合层至所述芯片的高密度芯片间引脚，所述第一互连孔内填充有导电材料；所述芯片间精细绕线层通过所述第一互连孔内填充的导电材料实现不同芯片之间的高密度芯片间引脚电互连。
  4. 根据权利要求3所述的芯片精细线路扇出封装结构，其特征在于，
    所述绝缘层包括第二绝缘层，所述互连孔包括第二互连孔，所述封装绕线层包括第一封装绕线层，所述第二绝缘层覆盖所述第一绝缘层和所述第一互连孔，所述第一封装绕线层设置于所述第二绝缘层；所述第二互连孔或贯穿所述第一绝缘层和所述第二绝缘层至所述芯片间精细绕线层，和/或，贯穿所述第二绝缘层、所述第一绝缘层、 所述芯片间精细绕线层和所述粘合层至所述低密度芯片互连引脚，所述第二互连孔内仅侧壁涂覆导电材料以实现所述第一封装绕线层与所述芯片间精细绕线层和/或所述低密度芯片互连引脚电互连。
  5. 根据权利要求4所述的芯片精细线路扇出封装结构，其特征在于，
    所述绝缘层还包括第三绝缘层，所述互连孔还包括第三互连孔，所述封装绕线层还包括第二封装绕线层，所述第三绝缘层覆盖所述第一封装绕线层，并且所述第三绝缘层的材料填满所述第二互连孔；所述第三互连孔贯穿所述第三绝缘层，所述第二封装绕线层设置于所述第三绝缘层，并通过所述第三互连孔内的导电材料与所述第一封装绕线层电连接。
  6. 根据权利要求1所述的芯片精细线路扇出封装结构，其特征在于，所述封装绕线层的线宽线距大于芯片间精细绕线层，所述芯片间精细绕线层为0.5-2微米，第一封装绕线层线宽线距为2-5微米。
  7. 根据权利要求6所述的芯片精细线路扇出封装结构，其特征在于，包括所述芯片间精细绕线层和所述封装绕线层在内的所有的绕线层的线宽线距，在远离所述芯片的方向上逐渐增大，除所述第一封装绕线层之外的其他封装绕线层的线宽为5微米以上。
  8. 根据权利要求1所述的芯片精细线路扇出封装结构，其特征在于，所述第一绝缘层以及各所述封装绕线层之间的绝缘层的材料包括聚酰亚胺(Polyimide)、苯并环丁烯(BCB)、派瑞林(parylene)、工业化液晶聚合物(LCP)、环氧树脂、硅氧化、硅氮化物、陶瓷、铝氧化物、玻璃中的至少一种。
  9. 根据权利要求5所述的芯片精细线路扇出封装结构，其特征在于，所述第一互连孔、所述第二互连孔以及所述第三互连孔内的导电材料为铜、铝、钨、导电膏、锡银合金、锡银铜合金、金锡合金中的至少一种。
  10. 一种芯片精细线路扇出封装结构的制作方法，其特征在于，包括：
    在临时支撑材料一侧表面上依次制作第一绝缘层、芯片间精细绕线层以及粘合层；
    在所述粘合层远离所述芯片间精细绕线层的一侧贴装多个芯片，所述芯片的引脚包括高密度芯片间互连引脚和低密度芯片互连引脚，所述芯片的引脚和芯片间精细绕线层精确对位；
    用包封材料包封住所述多个芯片并覆盖所述粘合层；
    去除所述临时支撑材料；
    在所述第一绝缘层上开设第一互连孔，所述第一互连孔贯穿所述第一绝缘层、所述芯片间精细绕线层和所述粘合层并露出所述芯片的高密度芯片间引脚，在所述第一互连孔填充导电材料，以使所述芯片间精细绕线层与所述芯片的高密度芯片间引脚电 连接；
    在所述第一绝缘层上再涂覆第二绝缘层，所述第二绝缘层覆盖所述第一绝缘层和所述第一互连孔，在所述第二绝缘层上制备第一封装绕线层；制备第二互连孔，所述第二互连孔贯穿所述第一封装绕线层、所述第二绝缘层、所述第一绝缘层和所述芯片间精细绕线层并露出所述低密度芯片互连引脚，和/或，贯穿所述第一封装绕线层、所述第二绝缘层、所述第一绝缘层露出所述芯片间精细绕线层；在所述第二互连孔内填充导电材料，并通过所述第二互连孔内导电材料将所述低密度芯片互连引脚与芯片间精细绕线层、第一封装绕线层电连接；
    在所述第一封装绕线层远离所述芯片方向再交替地制备至少一层绝缘层和至少一层封装绕线层，每层绝缘层上制作互连孔，互连孔内填充导电材料；并通过互连孔内导电材料将每层所述封装绕线层间形成电连接，所述芯片间精细绕线层的线宽线距小于各个所述封装绕线层的线宽线距；
    最远离所述芯片的封装绕线层设置有引脚焊盘，在最远离所述芯片的封装绕线层上覆盖阻焊层，去掉至少部分覆盖在所述引脚焊盘上的阻焊层；并且在所述引脚焊盘种植焊料球。
  11. 根据权利要求10所述的芯片精细线路扇出封装结构的制作方法，其特征在于，包括所述芯片间精细绕线层、第一封装绕线层以及其他封装绕线层在内的各绕线层的线宽线距在远离所述芯片的方向上逐渐增大。
  12. 根据权利要求10所述的芯片精细线路扇出封装结构的制作方法，其特征在于，所述第二互连孔内导电材料将所述低密度芯片互连引脚与所述第一封装绕线层电连接，和/或使芯片间精细绕线层与所述第一封装绕线层电连接。
  13. 根据权利要求10所述的芯片精细线路扇出封装结构的制作方法，其特征在于，在所述第二互连孔侧壁和底部涂覆导电材料，所述第二互连孔内剩余空间用第三绝缘层的材料填满，或者，所述第二互连孔内填满导电材料。
  14. 根据权利要求10所述的芯片精细线路扇出封装结构的制作方法，其特征在于，在各个所述互连孔内填充导电材料，包括：
    在所述互连孔侧壁和底部上磁控溅射或化学镀种子层金属，利用电镀工艺在所述互连孔内填充导电材料；或用丝网/钢网印刷导电材料的方法在所述互连孔内填满导电材料。
  15. 根据权利要求14所述的芯片精细线路扇出封装结构的制作方法，其特征在于，所述互连孔采用激光打孔的方式形成，或者，采用光刻和干法蚀刻的方式形成。
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CN107104096A (zh) * 2017-05-19 2017-08-29 华为技术有限公司 芯片封装结构及电路结构
US20180301351A1 (en) * 2014-02-14 2018-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate Design for Semiconductor Packages and Method of Forming Same
CN109087908A (zh) * 2015-12-31 2018-12-25 华为技术有限公司 封装结构、电子设备及封装方法
CN110197793A (zh) * 2018-02-24 2019-09-03 华为技术有限公司 一种芯片及封装方法
CN111370385A (zh) * 2020-04-13 2020-07-03 中芯长电半导体（江阴）有限公司 扇出型系统级封装结构及其制作方法

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CN109087908A (zh) * 2015-12-31 2018-12-25 华为技术有限公司 封装结构、电子设备及封装方法
CN107104096A (zh) * 2017-05-19 2017-08-29 华为技术有限公司 芯片封装结构及电路结构
CN110197793A (zh) * 2018-02-24 2019-09-03 华为技术有限公司 一种芯片及封装方法
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