TWI819134B - 高密度基板及具有其之堆疊矽封裝組件 - Google Patents

高密度基板及具有其之堆疊矽封裝組件 Download PDF

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Publication number
TWI819134B
TWI819134B TW108139275A TW108139275A TWI819134B TW I819134 B TWI819134 B TW I819134B TW 108139275 A TW108139275 A TW 108139275A TW 108139275 A TW108139275 A TW 108139275A TW I819134 B TWI819134 B TW I819134B
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Taiwan
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conductor
layer
density wiring
dielectric layer
low
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TW108139275A
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TW202021077A (zh
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賈斯匹利特 辛格 甘地
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美商吉林克斯公司
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    • H—ELECTRICITY
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Abstract

本發明提供具有用於晶片封裝組件之高密度佈線的改良互連基板，具有高密度基板的晶片封裝組件，以及用於製造其之方法，其運用具有於低密度佈線區上設置高密度佈線區的基板。於一範例中，提供用於製造互連基板的方法，包含藉由沉積晶種層於低密度佈線區的頂表面上以形成高密度佈線區；在晶種層上圖樣化遮罩層；於晶種層上形成複數個導體柱；移除裸露於所述導體柱之間的遮罩層和晶種層；以及沉積介電層於所述導體柱之間，其中，所述導體柱之至少一些被電耦接至構成低密度佈線區的導體佈線。

Description

高密度基板及具有其之堆疊矽封裝組件
本發明之範例大體上和用於晶片封裝組件的基板有關，且明確的說，和具有用於晶片封裝組件之高密度佈線的基板及具有其之晶片封裝組件有關。
先不提其它，就諸如平板、電腦、影印機、數位相機、智慧型電話、控制系統以及自動提款機的電子裝置而言經常運用以晶片封裝組件來提高功能及較高構件密度的電子構件。習知晶片封裝技術經常利用封裝基板，經常結合貫矽通孔(Through-Silicon-Via，TSV)中介片，以達成複數個積體電路(Integrated Circuit，IC)晶粒被安裝至單一封裝基板。IC晶粒可包含記憶體、邏輯元件或其它IC裝置。
於許多晶片封裝組件中運用有機封裝基板或中介片(統稱為基板)上的高密度佈線來滿足對於以低成本達到改良效能的無止境需求。然而，目前技術需要2：1的觸墊與通孔尺寸用以在形成於基板中的佈線中的通孔之間提供可靠連接線，因而限制佈線線路的密度。除此之外，目前的通孔沉積技術經常造成在堆疊通孔之間的不完美對齊，這會促成應力破裂以及早期裝置失效。佈線密度限制以及通孔應力破裂在其中高頻寬記憶體(High Band-width Memory，HBM)和邏輯晶粒(例如，場可程式化閘陣列(Field Programmable Gate Array， FPGA))被整合於需要高密度佈線之單一封裝組件的應用中特別有問題。於此些應用中，所述記憶體和邏輯晶粒可操作在非常靠近熱接面溫度極限的溫度處，其會惡化應力水平並且導致裝置失效。
所以，需要具有用於晶片封裝組件之高密度佈線的改良基板，以及具有其之堆疊矽封裝組件。
本發明提供具有用於晶片封裝組件之高密度佈線的改良互連基板，具有高密度基板的晶片封裝組件，以及用於製造其之方法，其運用於低密度佈線區上設置高密度佈線區的基板。於一範例中，提供用於製造用於晶片封裝組件之互連基板的方法，其包含藉由沉積第一晶種層於低密度佈線區的頂表面上以形成高密度佈線區；在第一晶種層上圖樣化第一遮罩層；於第一晶種層上形成複數個第一導體柱；移除裸露於所述複數個第一導體柱之間的第一遮罩層和第一晶種層；以及沉積第一介電層於所述複數個第一導體柱之間，其中，所述複數個第一導體柱之至少一些被電耦接至構成低密度佈線區的導體佈線。
於另一範例中也提供用於製造晶片封裝組件的方法，其包含，附接IC晶粒至形成在低密度佈線區的頂表面上的高密度佈線區，所述高密度佈線區具有複數個介電層，每一介電層的厚度小於約5μm，所述高與低密度佈線區構成互連基板的一部分；以及回焊被設置在IC晶粒與互連基板之間的焊接互連線，以便機械性及電性耦接IC晶粒的電路系統和互連基板的電路系統。
於另一範例中提供用於晶片封裝組件的互連基板。該互連基板包含低密度佈線區與高密度佈線區，低密度佈線區包含具有裸露的接觸墊的底層；頂表面；以及互連佈線，其耦接裸露在底層的接觸墊。高密度佈線區設置在低密度佈線區的頂表面上。高密度佈線區包含厚度小於約5μm的複數個介電 層；以及同軸對齊的複數個通孔，其延伸穿過所述複數個介電層。
於又一範例中提供晶片封裝組件，其包含本文中所述的互連基板；以及積體電路晶粒，其具有藉由焊接互連線耦接至互連基板的裸露接觸墊。焊接互連線的焊劑直接接觸經由所述複數個介電層所裸露的通孔的表面。
100:晶片封裝組件
102:蓋板
106:積體電路(IC)晶粒
108:封裝基板
112:介電填充層
114:熱介面材料(TIM)
116:印刷電路板(PCB)
118:焊接互連線
120:補強板
122:焊球
130:頂表面
132:底表面
134:頂表面
140:底表面
142:頂表面
144:底表面
146:頂表面
150:高密度佈線區
152:低密度佈線區
154:接觸墊
156:電路系統
158:接觸墊
160:電路系統
162:接觸墊
164:接觸墊
170:電路系統
180:電子裝置
202:第一累增區
204:核心基板
206:第二累增區
208:介電層
210:孔洞
212:電佈線
214:通孔
216:導電材料
218:介電層
220:孔洞
222:電佈線
224:焊接遮罩
228:介電層
230:孔洞
232:電佈線
250:厚度
252:厚度
254:厚度
302:直徑
304:中心線
306:間距
502:頂表面
504:底表面
600:第一晶種層
700:第一遮罩層
800:開口
802:第一/裸露部分
804:第二/覆蓋部分
902:第一導體柱
1200:第一介電層
1202:頂表面
1202':已薄化頂表面
1202":虛線
1204:頂表面
因此，參考範例施行方式可理解上述特徵的細節以及上面已簡要概述之更具體描述，某些範例施行方式可圖解在附圖中。然而，應注意的是附圖僅圖解典型範例施行方式，且因而不應被視為限制其範疇。
圖1為具有基板之晶片封裝組件的概略剖視圖，其包含用於耦接至設置在低密度互連線區上方之積體電路(IC)晶粒的高密度佈線區。
圖2為圖1之晶片封裝組件一部分的概略部分剖視圖，其詳述互連基板的結構。
圖3為圖2描繪之互連基板的高密度佈線區的一部分的放大概略剖視圖。
圖4為製造互連基板之方法的流程圖，其包含用於耦接至設置在低密度互連線區上方之積體電路(IC)晶粒的高密度佈線區。
圖5至13為根據圖4之方法的各種製造階段期間的互連基板的概略剖視圖。
圖14為製造具有互連基板之晶片封裝組件之方法的流程圖，其包含用於耦接至積體電路(IC)晶粒的高密度佈線區以及用於耦接至封裝基板或印刷電路板的低密度互連線區。
於圖2至3和圖5至13中所示的封裝基板剖視圖中，非導體材料層為交叉斜線，而導體材料層則非交叉斜線，以便最小化圖面混亂且更易於理解。
為幫助理解，可能的話，圖式中使用相同元件符號表示相同元件。可想像的是一範例的元件可有利地併入至其它範例中。
本發明提供具有用於晶片封裝組件之高密度佈線的改良互連基板，具有高密度基板的晶片封裝組件，以及用於製造其之方法，其運用於低密度佈線區上設置高密度佈線區的基板。本文中記載之基板包含設置於低密度佈線區上方的高密度佈線區。高密度佈線區包含不需要精確對齊以實質降低應力誘發破裂之可光成像介電質與通孔的較薄層。再者，通孔的精確對齊不需要使用接觸墊便可視情況製作在基板與積體電路(IC)晶粒之間的焊接連接線，因而降低製造成本與複雜度，同時可因小尺寸要求達到更大佈線密度。因為低密度佈線區可運用在高密度佈線區之下的基板中，所以，利用基板的印刷電路板側的低密度要求達到在基板的非關鍵區中使用低成本習知製造技術可進一步節省成本。優點係，高密度基板和具有其之晶片封裝組件以商業上運用習知製造技術所不可行的佈線密度的來改良可靠度與效能。舉例來說，構成高密度佈線區的薄介電層可讓訊號線設置在數微米的接地線內，因而降低電容性耦接並降低串音，同時依所希改良訊號傳送的速度與可靠度。
現在參考圖1，圖中概略圖解晶片封裝組件100的概略剖視圖，其包含封裝基板108，具有高、低密度佈線區150、152用以提供電力、接地、以及資料訊號給一或更多個積體電路(IC)晶粒106。可想像的是一中介片基板(未顯示)可設置在IC晶粒106之間，且封裝基板108可視情況被運用與製造為具有高、低密度佈線區150、152，如下文參考封裝基板108之構造的詳述。選用中介片基板和封裝基板108兩者於本文中稱為互連基板。晶片封裝組件100在被安裝至印刷電路板(Printed Circuit Board，PCB)116時形成電子裝置180的一部分。
圖1中雖然顯示兩個IC晶粒106；不過，IC晶粒的總數範圍可從一個至能夠配適在晶片封裝組件100裡面的許多個。可運用在晶片封裝組件100中的IC晶粒106的範例包含，但不限於，可程式邏輯裝置(例如，場可程式化閘陣列(FPGA))、記憶體裝置(例如，高頻寬記憶體(HBM))、光學裝置、處理器、或是其它IC邏輯結構。IC晶粒106中的一或更多個可視情況包含諸如光偵測器、雷射、光源、以及類似物的光學裝置。
每一個IC晶粒106包含底表面140與頂表面142。IC晶粒106的底表面140藉由焊接互連線118或其它合宜電連接線被耦接至封裝基板108頂表面134。
晶片封裝組件100還包含設置在IC晶粒106上方的選用蓋板102。蓋板102的底表面144面向IC晶粒106頂表面142。熱介面材料(Thermal Interface Material，TIM)114設置在IC晶粒106的頂表面142與蓋板102的底表面144之間，用以增強其間的熱傳輸。於一範例中，TIM 114可為熱凝膠或熱環氧樹脂，例如，可向位於新澤西州Princeton Junction的AI Technology,Inc.購得的封裝構件貼附黏著劑。
於某些實行方式中，蓋板102係由剛性材料製成。於尤其是希望運用蓋板102接收來自IC晶粒106的熱量的其它實行方式中，蓋板102係由導熱材料製成，例如不鏽鋼、銅、鍍鎳的銅或鋁，而先不提其它合宜材料。散熱片(未顯示)可視情況安裝至蓋板102的頂表面146。
蓋板102可結構性耦接至封裝基板108，用以提高晶片封裝組件100的剛性。視情況，補強板120可被用來將蓋板102結構性耦接至封裝基板108。使用時，補強板120可由下面材料製成：陶瓷、金屬或其它各種無機材料，例如氧化鋁(Al2O3)、氮化鋁(AlN)、氮化矽(SiN)、矽(Si)、銅(Cu)、鋁(Al)、以及不鏽鋼，而先不提其它材料。補強板120亦可由有機材料製成，例如，敷銅層板。
如上討論，IC晶粒106的電路系統156經由焊接互連線118被連接至封裝基板108的電路系統170。封裝基板108的電路系統170同樣被連接至PCB 116的電路系統160。於圖1中所示範例中，封裝基板108的頂表面134包含接觸墊162，其電性與機械性耦接至形成在IC晶粒106之底表面140上的接觸墊154。接觸墊154被耦接至IC晶粒106的電路系統156，而接觸墊162被耦接至封裝基板108的電路系統170。
如上提及，晶片封裝組件100可被安裝至印刷電路板(PCB)116，用以形成電子裝置180。同樣地，形成在封裝基板108之底表面132上的接觸墊164藉由焊球122或其它合宜連接線以電性與機械性耦接至形成在PCB 116的頂表面130上的接觸墊158。接觸墊164被耦接至封裝基板108的電路系統170，接觸墊158被耦接至PCB 116的電路系統160。
介電填充層112設置在IC晶粒106之間的封裝基板108上。介電填充層112為晶片封裝組件100提供額外剛性，也保護焊接互連線118。介電填充層112可為基於環氧樹脂材料或其它合宜材料。介電填充層112可額外包含填充層，舉例來說，無機填充層，例如二氧化矽(SiO2)。於一範例中，介電填充層112可具有介於約20至約40ppm/攝氏度之間的CTE，介於約5至約20帕斯卡-秒之間的黏性，以及介於約6至約15帕斯卡(Pa)之間的楊氏模數。
於一範例中，固化前的介電填充層112的黏性適合流入並填充焊接互連線118周圍之介於IC晶粒106的底表面140和封裝基板108的頂表面134之間的間隙空間。或者，可使用分離的底層填充材料來填充焊接互連線118周圍之介於IC晶粒106的底表面140和封裝基板108的頂表面134之間的間隙空間，而介電填充層112則設置在底層填充材料上方並且填充在相鄰IC晶粒106之間的間隙空間。
如上述，封裝基板108具有高密度佈線區150和低密度佈線區 152。相較於構成低密度佈線區152的導體，高密度佈線區150包含以允許較高密度導體(也就是，通孔與佈線)的方式所製作的複數個互連層。低密度佈線區152亦包含複數個互連層。然而，低密度佈線區152的互連層通常厚於高密度佈線區150的互連層。當低密度佈線區152內的導體排列成資料-接地-資料-接地時，低密度佈線區152的較薄層會降低串音及訊雜比(Signal-to-Noise Ratio，SNR)。封裝基板108的範例於下文參考圖2進一步詳述。
圖2為圖1之晶片封裝組件100的一部分的概略部分剖視圖，詳述封裝基板108的結構。封裝基板108的低密度佈線區152包含佈線電路系統170所貫穿的第一累增區202、核心基板204、以及第二累增區206。於某些實施例中，核心基板204可能不存在，於此情況中，第一累增區202和第二累增區206彼此相鄰形成。
核心基板204由剛性介電材料製成。作為核心基板204的合宜材料包含無機材料，例如矽、陶瓷、或其它合宜剛性介電材料。核心基板204通常具有厚度254，於多數實施例中，厚於構成封裝基板108的其它層。核心基板204包含複數個通孔214(圖2中顯示其中一者)。所述通孔214被導電材料216(例如，銅)填充，其構成延伸貫穿封裝基板108的電路系統170的電佈線的一部分。
第一累增區202包含形成電佈線212所貫串的複數個非導體(舉例來說，介電)層208。電佈線212為封裝基板108的電路系統170的一部分，由銅或其它合宜導電材料形成。電佈線212通常包含通孔與線路，以形成金屬互連線。於圖2中所示的實施例中，電佈線212的多個部分設置在形成於介電層208中的孔洞210之中。孔洞210可藉由雷射鑽鑿或其它合宜方法形成。電佈線212被沉積在孔洞210之中，舉例來說，藉由鍍製。電佈線212被耦接至核心基板204的導電材料216，以作為電路系統170的一部分。
第二累增區206包含形成電佈線222所貫串的複數個介電層218。 電佈線222為封裝基板108的電路系統170的一部分，由銅或其它合宜導電材料形成。電佈線222通常包含通孔與線路，以形成金屬互連線。於圖2中所示的實施例中，電佈線222的多個部分設置在形成於介電層218中的孔洞220之中。孔洞220可藉由雷射鑽鑿或其它合宜方法形成。電佈線222被沉積在孔洞220之中，舉例來說，藉由鍍製。電佈線222藉由核心基板204的導電材料216被耦接至電佈線212，以作為電路系統170之一部分。電佈線222通常終止於接觸墊164。接觸墊164可藉由焊接遮罩224或其它介電材料橫向地分離。
介電層208、218由電絕緣材料形成。介電層208、218中每一者可由介電樹脂製成。介電層208、218中每一者具有厚度252。介電層208、218的厚度252通常小於核心基板204的厚度254。
高密度佈線區150設置在並且直接接觸第一累增區202。高密度佈線區150包含形成電佈線232所貫穿的複數個介電層228。於一範例中，於高密度佈線區150中運用至少3個介電層228。
作為封裝基板108的電路系統170的一部分的電佈線232由銅或其它合宜導電材料形成。電佈線232通常包含通孔與線路，以形成金屬互連線。於圖2中所示的實施例中，電佈線232的多個部分設置在形成於介電層228中的孔洞230之中，且因此設置在孔洞230之中的電佈線232的部分可稱為「導體柱」或「通孔」。如下進一步討論，孔洞230通常在形成導體柱之後被形成在導體柱周圍。電佈線232被耦接至電佈線212，並且藉由導電材料216與佈線222被耦接至封裝基板108的接觸墊162。於一範例中，電佈線232終止於接觸墊162。接觸墊162可藉由焊接遮罩224或其它介電材料橫向地分離。於其它範例中，接觸墊162可能是選用的，並且電佈線232可直接接觸焊接互連線118。
介電層228由電絕緣材料形成。於一範例中，形成介電層228的材料不同於用來形成介電層208、218的材料。用以形成介電層228的合宜材料包含 不可光成像材料，例如不可光成像的聚噁唑、不可光成像的聚醯亞胺、以及不可光成像的環氧樹脂，而先不提其它材料。介電層228中每一者具有厚度250。介電層228的厚度250通常小於介電層208、218的厚度252。因為介電層228包含不可光成像材料，因此相較於可光成像材料，介電層228較為維度穩定且比較不受收縮及翹曲影響。
圖3為圖2描繪之封裝基板108的高密度佈線區150的一部分的放大概略剖視圖。如上討論，高密度佈線區150包含電佈線232。圖3中所示範例的形式為通孔(也就是，導體柱)。構成電佈線232一部分的導體柱有間距306，從通孔中心線304至通孔中心線304的橫向量測小於250μm，例如，小於150μm。構成電佈線232一部分的導體柱可堆疊一導體柱於另一者頂端，使得已堆疊通孔的中心線304實質共線，舉例來說，落在正/負1.0μm內。構成電佈線232一部分的已堆疊的導體柱同樣有非常一致的剖面，舉例來說，具有落在正/負1.0μm內的直徑302。再者，所述非常共線且一致的通孔會使得接觸墊162有較小尺寸甚至被排除，因而進一步使得有較小的間距306，並且因而允許有高密度的導體柱。相較於習知通孔設計，所述非常共線且一致的導體柱亦非常抗破裂，因而產生非常強健的互連基板，且最終，產生強健且可靠的晶片封裝組件100。
圖4為製造互連基板之方法400的流程圖，其包含用於耦接至設置在低密度互連線區152上方之積體電路(IC)晶粒106的高密度佈線區150。圖5至13為根據圖4之方法的各種製造階段期間的互連基板、例如，封裝基板108、的概略剖視圖。
用於製造用於晶片封裝組件之互連基板的方法400始於形成低密度佈線區152的操作402。如圖5中所示，低密度佈線區152包含在核心基板204的兩側形成第一累增區202及第二累增區206。第一累增區202及第二累增區206包含佈線沉積電路系統170所貫穿的多個介電層208、218。介電層208、218可被旋 塗或藉由其它合宜方法沉積在核心基板204上。電路系統170處於通孔與線路的形式，其被鍍製在貫穿(舉例來說，藉由雷射鑽鑿)介電層208、218及核心基板204所形成的孔洞210、220、230中。
在操作404處，高密度佈線區150被形成在低密度佈線區152的頂表面502上。低密度佈線區152的頂表面502被配置成於在製造之後面向IC晶粒106，而底表面504被配置成面向印刷電路板116。在操作404處形成高密度佈線區150包含重複實施複數個子操作，用以形成金屬互連線，其構成佈線穿過高密度佈線區150的電路系統170的部分(也就是，電佈線232)。
形成高密度佈線區150始於沉積第一晶種層600於低密度佈線區152的頂表面502上的子操作406，如圖6中所示。第一晶種層600可為銅層或適合幫助於其上鍍製導電材料的其它金屬或金屬層。於圖6中所示範例中，第一晶種層600為藉由物理氣相沉積(Physical Vapor Deposition，PVD)或化學氣相沉積(Chemical Vapor Deposition，CVD)或其它合宜製程所沉積的銅。第一晶種層600接觸第一累增區202的電佈線212。
在子操作408處，第一遮罩層700被沉積在第一晶種層600上。第一遮罩層700為光阻材料，且於圖7中所示範例中，為旋塗在第一晶種層600上的聚合阻抗材料。
在子操作410處，第一遮罩層700被圖樣化以形成開口800。如圖8中所示，形成在第一遮罩層700中的開口800露出第一晶種層600的第一(也就是，裸露)部分802，此處的第一遮罩層700的材料已被移除。第一晶種層600的第二(也就是，覆蓋)部分804在子操作410的圖樣化之後仍被第一遮罩層700覆蓋。第一遮罩層700可藉由直接成像、雷射燒蝕、光微影術、或其它合宜技術被圖樣化。
在子操作412處，複數個第一導體柱902被形成在第一晶種層600的裸露部分802上，如圖9中所示。第一導體柱902可由銅、鎳、鈷、鎢、或適合 資料、接地及電力傳送的其它導電材料形成，以作為封裝基板108的電路系統170的一部分。於圖9中所示範例中，第一導體柱902被電鍍在第一晶種層600的裸露部分802上。
在子操作414處，裸露在所述複數個第一導體柱902之間的第一遮罩層700部分會被移除，如圖10中所示。第一遮罩層700可藉由灰化、蝕刻、或其它合宜技術移除。第一遮罩層700被移除後，先前被第一遮罩層700覆蓋的第一晶種層600的覆蓋部分804現在便裸露出並且能夠在子操作416處藉由蝕刻、雷射燒蝕、或其它合宜技術移除。第一晶種層600的覆蓋部分804被移除後，僅第一晶種層600的部分802殘留在第一導體柱902及電佈線232之間，從而變成封裝基板108的電路系統170的一部分，如圖11中所示。
在子操作418處，會變成介電層228其中之一的第一介電層1200被沉積在所述複數個第一導體柱902以及低密度佈線區152的介電層208的頂表面502的裸露部分上方。如圖12中所示，第一介電層1200的頂表面1202設置在第一導體柱902的頂表面1204之上。於一範例中，第一介電層1200被旋塗在介電層208及第一導體柱902的頂表面502、1204上。於另一範例中，第一介電層1200可藉由化學氣相沉積(CVD)或其它合宜技術來沉積。
在子操作420處，圖12中所示的第一介電層1200的頂表面1202被移除以薄化第一介電層1200，至少直到第一導體柱902的頂表面1204透過已薄化頂表面1202'而裸露出，如圖13中所示。舉例來說，第一介電層1200可藉由飛切、蝕刻、磨削、研磨或其它合宜技術來薄化。於一範例中，第一介電層1200的厚度可縮減至第一導體柱902的頂表面1204以下，如虛線1202"所示。於此範例中，第一導體柱902的高度同樣縮減，俾使虛線1202"所示的表面和第一導體柱902的頂端保持實質共面。
於一範例中，第一介電層1200薄化至小於約5μm的厚度250。於 另一範例中，第一介電層1200薄化至介於2μm與4μm之間的厚度250。第一導體柱902/第一晶種層600配對的堆疊高度實質等於第一介電層1200的厚度250。一旦第一介電層1200經薄化後，第一介電層1200便成為介電層228。薄之介電層228優點係讓被配置成耦接至接地的電佈線232和被配置成攜載電(資料)訊號的電佈線232密集分佈，特別的係，在訊號-接地-訊號配置上會大幅降低串音並且改良封裝基板108的訊雜比。在子操作420之後，堆疊的第一導體柱902/第一晶種層600配對會形成電佈線232的第一導體柱，其接觸電佈線212。
在子操作422處，子操作406至420重複一或更多次，用以建構電佈線232貫穿高密度佈線區150。一旦形成電佈線232貫穿高密度佈線區150的每一層介電層228以配置所希的電路徑，操作404便完成。於一範例中，子操作422重複至少兩次，俾便運用三層介電層228(也就是，第一介電層、第二介電層、以及第三介電層)形成高密度佈線區150。於另一範例中，子操作422在每一個介電層228中同軸堆疊由電佈線232所形成的至少三個通孔(如圖2中所示的堆疊電佈線232(也就是，第一導體柱、第二導體柱、以及第三導體柱)所示)。因為第一遮罩層700被圖樣化且挖開用以精確裸露第一導體柱的頂端，所以，當精確對齊且直徑匹配時第二導體柱會被精確鍍製於其上，這無法利用習知製造技術達成。
在完成子操作422之後，可實施選用的子操作424。在子操作424處，接觸墊162和焊接遮罩224被形成在最上方的介電層228上。接觸墊162形成在且電耦接至電佈線232。接觸墊162提供將封裝基板108連接至IC晶粒106之焊接的附接點。接觸墊162通常藉由焊接遮罩224來分離。如果焊接連接線(也就是，焊接微凸塊)直接沉積在經由離核心基板204最遠之最上方的介電層228而裸露出的最上方電佈線之表面上的話，則可省略子操作424。
圖14為製造具有互連基板(例如，封裝基板108)之晶片封裝組件100之方法1400的流程圖，其包含用於耦接至積體電路(IC)晶粒106的高密度佈線 區150以及用於耦接至封裝基板或印刷電路板(PCB)116的低密度互連線區152。方法1400始於操作1402，將至少一IC晶粒106附接至形成在互連基板(例如，封裝基板108)之低密度佈線區152上方的高密度佈線區150。IC晶粒106可運用焊接互連線118或其它合宜技術進行附接。在操作1404處，焊接互連線118被回焊，以便機械性及電性耦接IC晶粒106的電路系統156和封裝基板108的電路系統170。
於一範例中，操作1402和1404可被用來電性及機械性附接一或更多個記憶體晶粒106至封裝基板108的高密度佈線區150，以及電性及機械性附接一或更多個邏輯晶粒106(例如，FPGA晶粒)至封裝基板108的高密度佈線區150。因此，操作1402、1404可用來形成被配置作為高頻寬記憶體(HBM)裝置的晶片封裝組件100。
可運用上述圖解在圖1中之方法1400來形成的示範性晶片封裝組件100。晶片封裝組件100被視為可單獨販售的完整產品。晶片封裝組件100亦可作為較大型的電子裝置180的構件。因此，用於製造晶片封裝組件100之方法1400可擴及用以在操作1406處形成電子裝置180。
在操作1406處，晶片封裝組件100被安裝至PCB 116，用以形成電子裝置180。晶片封裝組件100運用焊接連接線(例如，焊球122或其它合宜連接線)被安裝至PCB 116。於圖1中所示範例中，封裝基板108的底表面132藉由焊球122被電性及機械性耦接至所述PCB的頂表面130。換言之，焊球122被用來將形成封裝基板108之電路系統160的一部分的第二累增區206的電佈線222機械性及電性耦接於PCB 116的電路系統。
因此，上述一種具有高密度佈線的改良互連基板，其提供相較於習知基板設計為低的串音及改良的訊雜比。所述改良互連基板運用設置於低密度佈線區上方的高密度佈線區。高密度佈線區包含不需要可光成像介電質的較薄層。構成高密度佈線區之電佈線的堆疊通孔精確對齊，且優點係，呈現相較 於具有不良對齊和不同直徑的習知已製造基板之堆疊通孔實質為低的應力誘發破裂傾向。再者，通孔的精確對齊不需要使用接觸墊便可視情況製作在基板與積體電路(IC)晶粒之間的焊接連接線，因而降低製造成本與複雜度，同時可因小尺寸要求而達到更大佈線密度。在消除基板上之接觸墊的範例中可達成更高佈線密度，允許基板的通孔直接焊接至晶粒。因為低密度佈線區可運用在高密度佈線區之下的基板中，所以，利用基板的印刷電路板側的低密度要求達到在基板的非關鍵區中使用低成本習知製造技術可進一步節省成本。優點係，高密度基板和具有其之晶片封裝組件以商業上運用習知製造技術所不可行的佈線密度來改良可靠度與效能。舉例來說，構成高密度佈線區的薄介電層可讓訊號線設置在數微米的接地線內，因而降低電容性耦接並降低串音，同時依所希改良訊號傳送的速度與可靠度。本文中所述的改良互連基板優點係可作為晶片封裝組件和電子裝置的構件，因而讓所述組件和裝置更強健且可靠。
前述內容雖然和特定範例有關；不過，仍可設計出其它與進一步範例，不脫離本發明之基本範疇，而本發明之範疇係取決於隨附申請專利範圍。

Claims (15)

  1. 一種製造用於晶片封裝組件之互連基板的方法，所述方法包括：形成低密度佈線區；以及於所述低密度佈線區的頂表面上形成高密度佈線區，其中，形成所述高密度佈線區包括：沉積第一晶種層於所述低密度佈線區的所述頂表面上；在所述第一晶種層上圖樣化第一遮罩層；在所述第一晶種層上形成複數個第一導體柱；移除裸露於所述複數個第一導體柱之間的所述第一遮罩層和所述第一晶種層；沉積第一介電層於所述複數個第一導體柱之間，其中，所述複數個第一導體柱中之至少一些第一導體柱被電耦接至構成所述低密度佈線區的導體佈線；沉積第二晶種層於所述複數個第一導體柱和所述第一介電層上；在所述第二晶種層上圖樣化第二遮罩層；在所述第二晶種層上形成複數個第二導體柱；移除裸露於所述複數個第二導體柱之間的所述第二遮罩層和所述第二晶種層；及沉積第二介電層於所述複數個第二導體柱之間，其中，所述複數個第二導體柱中之第一導體柱同軸地形成在所述複數個第一導體柱中之第二導體柱上。
  2. 如請求項1所述之方法，進一步包括：薄化所述第一介電層。
  3. 如請求項2所述之方法，其中，薄化進一步包括： 蝕刻、研磨、或磨削所述第一介電層。
  4. 如請求項2所述之方法，其中，薄化進一步包括：縮減所述第一介電層的厚度至小於約5μm。
  5. 如請求項2所述之方法，其中，薄化所述第一介電層進一步包括：縮減所述複數個第一導體柱的高度。
  6. 如請求項1所述之方法，進一步包括：沉積第三晶種層於所述複數個第二導體柱和所述第二介電層上；在所述第三晶種層上圖樣化第三遮罩層；於所述第三晶種層上形成複數個第三導體柱；移除裸露於所述複數個第三導體柱之間的所述第三遮罩層和所述第三晶種層；以及沉積第三介電層於所述複數個第三導體柱之間，其中，所述複數個第三導體柱之第三導體柱同軸地形成在所述複數個第一導體柱之第一導體柱上。
  7. 如請求項6所述之方法，其中，所述複數個第一導體柱、所述複數個第二導體柱、以及所述複數個第三導體柱的直徑彼此相距1μm以內。
  8. 如請求項6所述之方法，進一步包括：於沉積所述第三介電層之前先薄化所述第二介電層。
  9. 如請求項1所述之方法，其中，形成所述低密度佈線區進一步包括：形成所述低密度佈線區的第一非導體層；以及形成貫穿所述低密度佈線區的所述第一非導體層的通孔，所述通孔被耦接至形成在所述高密度佈線區中的所述複數個第一導體柱之第一導體柱。
  10. 如請求項9所述之方法，其中，形成所述通孔進一步包括：雷射鑽鑿所述第一非導體層。
  11. 如請求項9所述之方法，進一步包括：薄化所述第一介電層至厚度小於所述第一非導體層之厚度，所述第一介電層的厚度小於約5μm。
  12. 如請求項1所述之方法，其中，形成所述第一介電層進一步包括：沉積不可光成像材料於所述低密度佈線區的所述頂表面上。
  13. 如請求項12所述之方法，其中，沉積所述不可光成像材料進一步包括：沉積聚噁唑、聚醯亞胺、或環氧樹脂之至少一者於所述低密度佈線區的所述頂表面。
  14. 一種製造晶片封裝組件的方法，所述方法包括：附接IC晶粒至形成在低密度佈線區的頂表面上的高密度佈線區，所述高密度佈線區具有複數個介電層，每一介電層的厚度小於約5μm，所述高密度佈線區與所述低密度佈線區構成互連基板的一部分，其中，形成所述高密度佈線區包括：沉積第一晶種層於所述低密度佈線區的所述頂表面上；在所述第一晶種層上圖樣化第一遮罩層；在所述第一晶種層上形成複數個第一導體柱；移除裸露於所述複數個第一導體柱之間的所述第一遮罩層和所述第一晶種層；沉積第一介電層於所述複數個第一導體柱之間，其中，所述複數個第一導體柱中之至少一些第一導體柱被電耦接至構成所述低密度佈線區的導體佈線；沉積第二晶種層於所述複數個第一導體柱和所述第一介電層上；及在所述第二晶種層上形成複數個第二導體柱；以及 回焊被設置在所述IC晶粒與所述互連基板之間的焊接互連線，以便機械性及電性耦接所述IC晶粒的電路系統和所述互連基板的電路系統。
  15. 如請求項14所述之方法，進一步包括：運用所述焊接互連線以安裝印刷電路板至所述低密度佈線區，以便耦接封裝基板的電路系統至所述互連基板的所述電路系統。
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