CN112054006A - 半导体设备封装及其制造方法 - Google Patents

半导体设备封装及其制造方法 Download PDF

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Publication number
CN112054006A
CN112054006A CN201910927126.6A CN201910927126A CN112054006A CN 112054006 A CN112054006 A CN 112054006A CN 201910927126 A CN201910927126 A CN 201910927126A CN 112054006 A CN112054006 A CN 112054006A
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China
Prior art keywords
layer
conductive
conductive structure
electronic component
circuit layer
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CN201910927126.6A
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Inventor
黄茜楣
王仕宇
林仪婷
黄文宏
苏育贤
李志成
田兴国
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112054006A publication Critical patent/CN112054006A/zh
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Abstract

一种半导体设备封装包含第一导电结构、应力缓冲层和第二导电结构。所述第一导电结构包含衬底、嵌入于所述衬底中的至少一个第一电子组件，和安置在所述衬底上并电连接到所述第一电子组件的第一电路层。所述第一电路层包含导电布线图案。所述应力缓冲层安置在所述衬底上。所述第一电路层的所述导电布线图案延伸穿过所述应力缓冲层。所述第二导电结构安置在所述应力缓冲层和所述第一电路层上。

Description

半导体设备封装及其制造方法
技术领域
本公开涉及一种半导体设备封装及其制造方法，且涉及一种包含应力缓冲层或经图案化钝化层的半导体设备封装及其制造方法。
背景技术
随着电子行业的快速发展以及半导体处理技术的进步，半导体芯片与增加数目的电子组件集成，以实现改进的电气性能和额外功能。相应地，半导体芯片具备更多的输入/输出(I/O)连接。为了制造包含具有增大数目的I/O连接的半导体芯片的半导体封装，可用于运载半导体芯片的半导体衬底的电路层的大小可对应地增加。因此，半导体设备封装的厚度和翘曲可对应地增加，且半导体设备封装的良率可减小。
发明内容
在一些实施例中，半导体设备封装包含第一导电结构、应力缓冲层和第二导电结构。第一导电结构包含衬底、嵌入于衬底中的至少一个第一电子组件和安置在衬底上并电连接到第一电子组件的第一电路层。第一电路层包含导电布线图案。应力缓冲层安置在衬底上。第一电路层的导电布线图案延伸穿过应力缓冲层。第二导电结构安置在应力缓冲层和第一电路层上。
在一些实施例中，半导体设备封装包含第一导电结构、钝化层和第二导电结构。第一导电结构包含衬底、嵌入于衬底中的至少一个第一电子组件和安置在衬底上并电连接到第一电子组件的第一电路层。钝化层安置在第一电路层上。钝化层包含部分地暴露第一电路层的多个开口。第二导电结构安置在钝化层上。第二导电结构包含延伸到钝化层的开口中并电连接到第一电路层的多个第一导电凸块。
在一些实施例中，制造半导体设备封装的方法包含以下操作。形成第一导电结构。第一导电结构包含其中嵌入了至少一个第一电子组件的衬底，和安置在衬底上的电路层。应力缓冲层形成于第一电路层上，其中应力缓冲层包含多个开口。导电布线图案形成于应力缓冲层的开口中。第二导电结构形成于应力缓冲层上，且电连接到导电布线图案。
在一些实施例中，制造半导体设备封装的方法包含以下操作。形成第一导电结构。第一导电结构包含其中嵌入了至少一个第一电子组件的衬底，和安置在衬底上的第一电路层。具有多个开口的钝化层形成于第一电路层上。第二导电结构形成于载体上，且多个第一导电凸块形成于第二导电结构上。第二导电结构通过插入到钝化层的开口中并与第一电路层电连接的第一导电凸块结合到第一导电结构。从第二导电结构去除所述载体。
附图说明
当结合附图阅读时，从以下具体实施方式易于理解本公开的一些实施例的各方面。各种结构可能未按比例绘制，且各种结构的尺寸可出于论述的清楚起见任意增大或减小。
图1是根据本公开的一些实施例的半导体设备封装的横截面图。
图1A是图1中的半导体设备封装的放大视图。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K、图2L和图2M说明根据本公开的一些实施例的制造半导体设备封装的操作。
图3是根据本公开的一些实施例的半导体设备封装的横截面图。
图4A、图4B、图4C、图4D、图4E和图4F说明根据本公开的一些实施例的制造半导体设备封装的操作。
图5A、图5B、图5C、图5D和图5E说明根据本公开的一些实施例的制造半导体设备封装的子操作。
图6A、图6B、图6C、图6D和图6E说明根据本公开的一些实施例的制造半导体设备封装的子操作。
图7是根据本公开的一些实施例的半导体设备封装的横截面图。
图8A、图8B、图8C、图8D和图8E说明根据本公开的一些实施例的制造半导体设备封装的操作。
具体实施方式
以下公开内容提供用于实施所提供的主题的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例来阐释本公开的某些方面。当然，这些只是实例且并不意欲为限制性的。举例来说，在以下描述中，第一特征形成于第二特征上方或上可包含其中第一特征和第二特征形成或安置成直接接触的实施例，且也可包含其中额外特征形成或安置在第一特征与第二特征之间使得第一特征和第二特征并不直接接触的实施例。另外，本公开可能在各个实例中重复参考数字和/或字母。此重复是出于简单和清晰的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
如本文中所使用，为易于描述，本文中可以使用例如“下方”、“下面”、“下部”、“上方”、“上部”、“下部”、“左边”、“右边”等空间相对术语来描述一个元件或特征与另一(些)元件或特征的关系，如图中所说明。除了图中所描绘的定向之外，空间相对术语意图涵盖在使用或操作中的设备的不同定向。设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的空间相关描述词也可相应地进行解释。应理解，当元件被称为“连接到”或“耦合到”另一元件时，其可直接连接或耦合到另一元件，或可存在中间元件。
本公开提供集成例如导电衬底等低密度导电结构、例如电容器等无源电子组件、例如扇出电路等高密度导电结构和例如ASIC组件或存储器组件等有源电子组件的解决方案。无源电子组件嵌入于衬底中，这样可以减小半导体设备封装的整体厚度。有源电子组件竖直地堆叠于无源电子组件上，且因此无源电子组件与有源电子组件之间的信号发射路径可以缩短。半导体设备封装进一步包含安置于第一导电结构与第二导电结构之间的应力缓冲层。应力缓冲层的CTE在第一导电结构的CTE与第二导电的CTE之间，如此可以缓解翘曲和分层问题。应力缓冲层也可配置为用于第一导电结构的平坦层面，且因此第二导电结构可直接制造于第一导电结构上而不需要大尺寸的焊球。因此，可以改进电学性能。半导体设备封装进一步包含安置于第一导电结构与第二导电结构之间的经图案化钝化层。钝化层的开口允许第二导电结构的导电凸块插入，因此第二导电结构与第一导电结构之间的结合鲁棒性得以增强。钝化层可为光敏钝化层，所述光敏钝化层可以通过光刻操作进行图案化，因此开口的尺寸可以最小化至例如低于50微米。相应地，可以增加I/O连接的数目。
图1是根据本公开的一些实施例的半导体设备封装1的横截面图，且图1A是图1中的半导体设备封装1的放大视图。如图1所示，半导体设备封装1包含第一导电结构10、应力缓冲层30和第二导电结构40。第一导电结构10可包含具有上表面12A的衬底12，和与上表面12A相反的底表面12B。衬底12的材料可包含介电材料或绝缘材料。衬底12可为芯衬底、无芯衬底或其它合适的衬底。衬底12可界定至少一个穿孔12H。至少一个互连通孔13安置于穿孔12H中。互连通孔13可包含基底导电层131和绝缘材料132。基底导电层131安置或形成于穿孔12H的侧壁上，且界定中心穿孔。绝缘材料132填充由基底导电层131界定的中心穿孔。在一些实施例中，绝缘材料132可以省略，且块状导电材料可填充穿孔12H以形成互连通孔。在一些实施例中，互连通孔13可进一步包含分别安置在上表面12A和底表面12B上并电连接到基底导电层131的上部电极13a和底部电极13b。
衬底12可界定至少一个空腔12C。空腔12C可为穿过衬底12的贯通腔，或从上表面12A凹陷但不穿过衬底12的凹部。第一导电结构10包含嵌入于衬底12中的至少一个第一电子组件20。第一电子组件20可安置于空腔12C中，且低于衬底12的上表面12A。在一些其它实施例中，第一电子组件20可与衬底12的上表面12A齐平或比所述上表面更高。第一电子组件20可包含无源电子组件，例如电容器、电阻器、电感器或其组合。第一电子组件20可包含至少一个上部电极20a和至少一个底部电极20b。
第一导电结构10可包含空腔12C中囊封第一电子组件20的填充材料22。填充材料22可囊封第一电子组件20的侧壁。填充材料22可进一步囊封第一电子组件20的上表面和/或底表面。填充材料22可部分地囊封上部电极20a和底部电极20b。填充材料22的材料可包含树脂、油墨(例如，味之素堆积膜(ABF)油墨)或模制化合物。填充材料22可能没有填充剂。或者，填充材料22可能具有1～2微米大小或更小的填充剂。此外，填充材料22的薄膜损耗可小于0.4％，以抵抗化学蚀刻。
第一导电结构10进一步包含安置在衬底12的上表面12A上且通过上部电极20a电连接到第一电子组件20的至少一个上部电路层(也被称作第一电路层)14a。在一些实施例中，至少一个上部介电层15a可安置在上表面12A上。在一些实施例中，上部电路层14a可穿过上部介电层15a。上部电路层14a可安置在上部介电层15a上，与所述上部介电层相邻，或嵌入于所述上部介电层中并通过所述上部介电层暴露。在一些实施例中，上部电路层14a可包含衬底级电路层，所述衬底级电路层是具有较宽线宽/线距(L/S)的低密度电路层。举例来说，上部电路层14a的L/S可等于或大于约10μm/约10μm。
在一些实施例中，第一导电结构10可进一步包含安置在衬底12的底表面12B上且通过底部电极20b电连接到第一电子组件20的至少一个底部电路层14b在一些实施例中，至少一个底部介电层15b可安置在底表面12B上。在一些实施例中，底部电路层14b可穿过底部介电层15b。在一些实施例中，底部电路层14b可包含衬底级RDL，所述衬底级RDL是具有较宽L/S的低密度RDL。举例来说，底部RDL 16的L/S可等于或大于约10μm/约10μm。底部电路层14b的L/S可等于上部电路层14a的L/S。
在一些实施例中，底部重布层(RDL)16可安置在底表面12B上，且电连接到底部电路层14b。底部RDL 16可包含彼此堆叠的一或多个布线层16a和一或多个介电层16b。底部RDL 16的L/S可大体上等于或大于上部电路层14a或底部电路层14b的L/S。在一些实施例中，底部RDL 16包含衬底级RDL，所述衬底级RDL是具有较宽L/S的低密度RDL。举例来说，底部RDL 16的L/S可等于或大于约10μm/约10μm。在一些实施例中，例如焊球等一或多个电导体17可安置在底部RDL 16上并与其电连接以便于进行外部电连接。举例来说，电导体17可进一步结合到例如印刷电路板(PCB)等电路板。
在一些实施例中，上部电路层14a的最上部层可包含从上部介电层15a向外突出至少一个导电布线图案14a1。导电布线图案14a1的横截面形状可为倒梯形形状、矩形形状、筒形形状或其它几何形状。
应力缓冲层30安置在衬底12上。应力缓冲层30的材料可为绝缘的或介电的。应力缓冲层30的材料可包含有机材料、无机材料或混合材料。导电布线图案14a1延伸穿过应力缓冲层30，且导电布线图案14a1的至少一部分，例如上表面从应力缓冲层30中暴露。
第二导电结构40安置在应力缓冲层30和上部电路层14a的导电布线图案14a1上。第二导电结构40包含电连接到上部电路层14a的至少一个电路层(也被称作第二电路层)42。在一些实施例中，电路层42可包含彼此堆叠的至少一个导电布线图案421和至少一个介电层422。在一些实施例中，导电布线图案421可包含多个导电通孔42V。导电通孔42V可具有但不限于倒梯形横截面形状。最底部导电布线图案421可从最底部介电层422中暴露，且电连接到第一导电结构10的上部电路层14a的导电布线图案14a1。在一些实施例中，电路层42可逐层堆积在上部电路层14a上。举例来说，上部电路层14a可通过各种操作形成于上部电路层14a上，所述操作包含例如电镀等沉积、例如光刻和/或蚀刻等图案化、例如研磨等平坦化，及其类似者。在一些实施例中，导电布线图案421的材料可包含例如铜等金属，所述金属可通过电镀而形成。介电层422的材料可包含光敏材料，所述光敏材料可通过光刻进行图案化。上部电路层14a的导电布线图案14a1与电路层42的最底部导电布线图案421之间的接头可为无焊接头。举例来说，电路层42的最底部导电布线图案421可直接从上部电路层14a的导电布线图案14a1延伸。换句话说，一些实施例的电路层42并非结合到上部电路层14a的预成型电路层。最上部导电布线图案421可安置在最上部介电层422上，与所述最上部介电层相邻，或嵌入于所述最上部介电层中并通过所述最上部介电层暴露，以进行进一步电连接。在一些实施例中，第一导电结构10的边缘10E与第二导电结构40的边缘40E大体上对齐。第二导电结构40的电路层42的L/S可低于第一导电结构10的上部电路层14a的L/S。电路层42可包含凸块级电路层，所述凸块级电路层为具有较窄L/S的高密度电路层。举例来说，电路层42的L/S可介于约2μm/约2μm与约10μm/约10μm之间，或低于约2μm/约2μm。举例来说，第二导电结构40可为扇出(FO)结构。
半导体设备封装1可进一步包含安置在第二导电结构40上并通过例如最上部导电布线图案421电连接到所述第二导电结构的至少一个第二电子组件50。在一些实施例中，第二电子组件50可包含有源电子组件。举例来说，有源电子组件可包含集成电路(IC)组件，例如专用IC(ASIC)、存储器组件或其组合。导电凸块52可安置于第二电子组件50与第二导电结构40之间，以将第二电子组件50电连接到电路层42。导电凸块52可包含焊料凸块或其它合适的导体。在一些实施例中，底部填充层53可围绕导电凸块52安置于第二电子组件50与第二导电结构40之间。例如第二电子组件50等有源电子组件竖直地堆叠于例如第一电子组件20等无源电子组件上。因此，无源电子组件与有源电子组件之间的信号发射路径可以缩短，且在信号发射期间的能量损耗可以减小。此外，功率消耗可以降低，且性能可以改进。
囊封层54可安置在第二导电结构40上以囊封第二电子组件50。在一些实施例中，囊封层54可囊封第二电子组件50的侧壁，且暴露第二电子组件50的上表面。或者，囊封层54可囊封第二电子组件50的侧壁和上表面。
在一些实施例中，第一导电结构10可也被称作“低密度导电结构”或“低密度堆叠结构”，且第二导电结构40也可被称作“高密度导电结构”或“高密度堆叠结构”。第二导电结构40的电路层42的线宽/线距(L/S)可小于第一导电结构10的上部电路层14a的L/S。举例来说，电路层42的L/S可介于约2μm/约2μm与约10μm/约10μm之间，且上部电路层14a的L/S可等于或大于约10μm/约10μm。高密度第二导电结构40可以配置成扇出电路，以将第二电子组件50与更多I/O连接电连接，且将I/O连接重新分布到低密度第一导电结构10。低密度第一导电结构10可配置成将重布的I/O连接从第二导电结构40发射到PCB。
应力缓冲层30安置于第一导电结构10与第二导电结构40之间以帮助平衡应力变化。应力缓冲层30的热膨胀系数(CTE)被选择在第一导电结构10的CTE与第二导电结构40的CTE之间，以帮助平衡第一导电结构10与第二导电结构40之间的应力变化，从而减轻半导体设备封装1的翘曲。举例来说，应力缓冲层30的CTE约为20ppm/℃，第一导电结构10的CTE约为15ppm/℃，且第二导电结构40的CTE约为40ppm/℃。应力缓冲层30也可以配置成平坦层面以用于改进堆积电路层42的良率。在一些实施例中，应力缓冲层30的上表面30U与导电布线图案14a1的上表面14U大体上共面。由于工艺限制或其它出人意料的原因，导电布线图案14a1的上表面14U可稍微低于应力缓冲层30的上表面30U，如图1A所示。当上表面14U的凹陷程度可以接受，即不会影响电路层42的形成时，应力缓冲层30的上表面30U和导电布线图案14a1的上表面14U可被视为共面的。举例来说，应力缓冲层30的上表面30U与导电布线图案14a1的上表面14U之间的高度差“g”小于约5微米，使得第二导电结构40的电路层42可易于堆积在导电布线图案14a1和应力缓冲层30上。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K、图2L和图2M说明根据本公开的一些实施例的制造半导体设备封装1的操作。如图2A所示，接收衬底12。在一些实施例中，上部铜箔121和底部铜箔122可分别形成于上表面12A和底表面12B上。形成穿过衬底12的穿孔12H。如图2B所示，互连通孔13形成于穿孔12H中。互连通孔13可包含基底导电层131和绝缘材料132。基底导电层131安置或形成于穿孔12H的侧壁上。绝缘材料132填充于穿孔12H中。在一些实施例中，互连通孔13可进一步包含分别安置在上表面12A和底表面12B上并电连接到基底导电层131的上部电极13a和底部电极13b。
如图2C所示，空腔12C形成于衬底10中。在一些实施例中，空腔12C是穿过衬底12的贯通腔。在一些替代实施例中，空腔12C可为从上表面12A凹陷但不穿过衬底12的凹部。如图2D所示，衬底12结合到例如条带等临时衬底19。至少一个第一电子组件20放置在空腔12C中。在一些实施例中，多个第一电子组件20用胶固定，例如在放置在空腔12C中之前。如图2E所示，填充材料22填充于空腔12C中以囊封第一电子组件20。
如图2F所示，临时衬底19从衬底12脱离。如图2G所示，至少一个上部电路层(也被称作第一电路层)14a和至少一个上部介电层15a形成于衬底12的上表面12A上。在一些实施例中，至少一个底部电路层14b和至少一个底部介电层15b形成于衬底12的底表面12B上。如图2H所示，底部重布层(RDL)16形成于底表面12B上，且电连接到底部电路层14b。底部RDL16可包含彼此堆叠的一或多个布线层16a和一或多个介电层16b。在一些实施例中，布线层16a可安置在介电层16b上，与所述介电层相邻，或嵌入于所述介电层中并通过所述介电层暴露。在一些实施例中，上部电路层14a、底部电路层14b和底部RDL 16各自可包含衬底级电路层，所述衬底级电路层是具有较宽L/S的低密度电路层。因此，制造成本可以减小。上部电路层14a、底部电路层14b和底部RDL 16各自可通过各种操作形成，所述操作包含例如电镀等沉积、例如光刻和/或蚀刻等图案化、例如研磨等平坦化，及其类似者。
如图2I所示，应力缓冲层30形成于衬底12上。多个开口30H可例如但不限于由激光钻孔形成。如图2J所示，导电层31形成于应力缓冲层30上和开口30H中。导电层31的材料可包含例如铜等金属，但不限于此。导电层31可例如由电镀形成。如图2K所示，通过蚀刻、研磨等来去除应力缓冲层30的开口30H外部的导电层31，以形成与应力缓冲层30大体上共面的导电布线图案14a1。如图2J和图2K所示，在应力缓冲层30上形成导电层31以填充开口30H，且接着蚀刻掉应力缓冲层30上的导电层31。因此，制造操作得以简化，且表面均匀性可以增加。在一些实施例中，导电层31可以稍微过度蚀刻，且导电布线图案14a1的上表面可稍微低于应力缓冲层30的上表面，如图1A所示。
如图2L所示，第二导电结构40形成于应力缓冲层30和上部电路层14a的导电布线图案14a1上。第二导电结构40包含电连接到上部电路层14a的至少一个电路层(也被称作第二电路层)42。在一些实施例中，电路层42可包含彼此堆叠的至少一个导电布线图案421和至少一个介电层422。在一些实施例中，电路层42直接堆积在上部电路层14a上，且上部电路层14a的导电布线图案14a1与电路层42的最底部导电布线图案421之间的接头可为无焊接头。电路层42可包含凸块级电路层，所述凸块级电路层是具有较窄L/S的高密度电路层。高密度第二导电结构40可以配置成扇出电路，以将待形成的第二电子组件50与更多I/O连接电连接，且将I/O连接重新分布到低密度第一导电结构10。凸块级电路层是具有较窄L/S的高密度电路，因此底层的表面均匀性对于凸块级电路层的良率和可靠性很关键。应力缓冲层30和导电布线图案14a1共同地形成均匀平面表面，因此帮助形成电路层42。
如图2M所示，至少一个第二电子组件50结合到第二导电结构40。在一些实施例中，例如焊料凸块等导电凸块52用以将第二电子组件50结合到第二导电结构40。在一些实施例中，底部填充层53可围绕导电凸块52形成于第二电子组件50与第二导电结构40之间。囊封层54形成于第二导电结构40上以囊封第二电子组件50。在一些实施例中，囊封层54可囊封第二电子组件50的侧壁和上表面。可对囊封层54进行研磨以暴露第二电子组件50的上表面。例如焊球等电导体17形成于底部RDL 16上以形成半导体设备封装1，如图1中所说明。预期第二电子组件50在第二导电结构40结合到第一导电结构10之后结合到第二导电结构40，这是芯片最后的操作。因此，损坏第二电子组件50的风险可以降低。
本公开的半导体设备封装和制造方法不限于上文描述的实施例，且可根据其它实施例实施。为了简化本说明书以及为了便于在本公开的各种实施例之间进行比较，以下实施例中的类似组件标记有相同数字，且可以不用过多地进行描述。
图3是根据本公开的一些实施例的半导体设备封装2的横截面图。如图3所示，半导体设备封装2包含第一导电结构10、钝化层32和第二导电结构40。钝化层32安置在第一导电结构10的上部电路层14a上。钝化层32包含部分地暴露上部电路层14a的多个开口32H。第二导电结构40进一步包含电连接到上部电路层14a的多个导电凸块46。导电凸块46延伸到钝化层32的开口32H中以增强第二导电结构40与第一导电结构10之间的结合鲁棒性。导电凸块46可包含例如焊球或焊膏等焊料、例如金属支柱等金属连接器，或其它合适的导电凸块。在一些实施例中，电路层42的导电布线图案421可包含多个导电通孔42V。导电通孔42V可具有但不限于梯形横截面形状。
在一些实施例中，钝化层32的材料包含固化光敏材料，使得开口32H可以通过曝光和显影操作进行图案化，且开口32H的宽度和间距可最小化。举例来说，开口32H的宽度可减小到小于80微米、50微米或更小。在一些替代实施例中，钝化层32的材料可包含防焊罩或其它可以图案化的材料。在一些实施例中，第二导电结构40在结合到第一导电结构10之前形成并进行单分，因此第一导电结构10的边缘10E可从第二导电结构40的边缘40E伸出。半导体设备封装2可进一步包含安置于钝化层32与第二导电结构40之间并围绕导电凸块46的底部填充层48。在一些实施例中，底部填充层48的边缘可与第二电子组件40的边缘40E大体上对齐。
图4A、图4B、图4C、图4D、图4E和图4F说明根据本公开的一些实施例的制造半导体设备封装2的操作。半导体设备封装2的制造操作可在图2H中说明的制造操作之后执行。如图4A所示，钝化层32执行于第一导电结构10上，且多个开口32H形成于钝化层32中以暴露上部电路层14a。在一些实施例中，钝化层32的材料包含固化光敏材料，且开口32H可通过曝光和显影操作进行图案化。因此，开口32H的宽度和间距可最小化。
如图4B所示，多个第二导电结构40形成于载体80上。第二传导结构40可包含至少一个电路层42，所述电路层包含多个导电布线图案421和多个介电层422。导电布线图案421和介电层422可通过在载体80上交替地形成介电材料层和导电层而形成。在一些实施例中，导电布线图案421可包含多个导电通孔42V。导电通孔42V可具有但不限于倒梯形横截面形状。在一些实施例中，多个导电凸块46形成于电路层42上以电连接电路层42。
如图4C所示，对第二导电结构40进行单分。如图4D所示，由经单分载体80支撑的经单分第二导电结构40翻转并通过插入到钝化层32的开口32H中且电连接上部电路层14a的导电凸块46结合到第一导电结构10。当第二导电结构40翻转并结合到第一导电结构10时，导电布线图案421可包含具有梯形横截面形状的多个导电通孔。底部填充层48接着形成于钝化层32与第二导电结构40之间，且围绕导电凸块46。在一些实施例中，可执行修整操作以修整第二导电结构40和底部填充层48，从而去除爬上第二导电结构40的边缘40E和载体80的边缘的过量底部填充材料。调整操作可以通过激光L、刀片等等进行。
如图4E所示，从第二导电结构40去除载体80。因为去除了溢出的底部填充材料，所以载体80可易于从第二导电结构40去除，且底部填充层48的边缘48E与第二电子组件40的边缘40E大体上对齐。此外，第一导电结构10的边缘10E可从第二导电结构40的边缘40E伸出。
如图4F所示，至少一个第二电子组件50结合到第二导电结构40。在一些实施例中，例如焊料凸块等导电凸块52用以将第二电子组件50结合到第二导电结构40。在一些实施例中，底部填充层53可围绕导电凸块52形成于第二电子组件50与第二导电结构40之间。囊封层54形成于第二导电结构40上以囊封第二电子组件50。在一些实施例中，囊封层54可囊封第二电子组件50的侧壁和上表面。可对囊封层54进行研磨以暴露第二电子组件50的上表面。囊封层54可进一步覆盖第二导电结构40的边缘40E和底部填充层48的边缘48E。例如焊球等电导体17形成于底部RDL 16上以形成半导体设备封装2，如图3中所说明。预期第二电子组件50在第二导电结构40结合到第一导电结构10之后结合到第二导电结构40，这是芯片最后的操作。因此，损坏第二电子组件50的风险可以降低。
图5A、图5B、图5C、图5D和图5E说明根据本公开的一些实施例的制造半导体设备封装2的子操作。在一些实施例中，导电布线图案421和介电层422的制造操作可包含如图5A、图5B、图5C、图5D和图5E中所说明的子操作。如图5A所示，基底层82形成于载体80上。基底层82可以配置成晶种层和/或结合增强层。在一些实施例中，基底层82可包含能够较佳地粘着到载体80的结合增强材料和晶种层的堆叠。举例来说，结合增强层可包含由物理气相沉积(PVD)形成的钛层，且晶种层可包含铜。介电层422形成于基底层82上，且开口422H形成于介电层422中以暴露基底层82。在一些实施例中，介电层422的材料可包含例如聚酰亚胺(PI)等光敏材料，且开口422H可通过曝光和显影操作形成。
如图5B所示，第一导电材料411形成于开口422H的底部中。如图5C所示，第二导电材料412形成于介电层422和第一导电材料411上。第三导电材料413形成于第二导电材料412上。选择第二导电材料412的材料以提供介电层422与第三导电材料413之间的较佳粘着，从而避免分层。在一些实施例中，第一导电材料411的材料可包含例如铜，且第二导电材料412的材料可包含例如由PVD形成的钛，且第三导电材料413的材料可包含例如铜。
如图5D所示，接着在电路层42完成并如图4D所示结合到第一导电结构10之后从介电层422去除载体80。例如通过蚀刻来去除基底层82以暴露第一导电材料411。在一些实施例中，导电材料411可部分地去除并从介电层422凹陷，使得开口422H的一部分被暴露。如图5E和图4F所示，第二电子组件50形成于介电层422上，且通过导电凸块52电连接到导电布线图案421。导电凸块52插入到开口422H中以增强第二电子组件50与导电布线图案421之间的结合。开口422H可部分或完全充满导电凸块52。
图6A、图6B、图6C、图6D和图6E说明根据本公开的一些实施例的制造半导体设备封装2的子操作。在一些实施例中，导电布线图案421和介电层422的制造操作可包含如图6A、图6B、图6C、图6D和图6E中所说明的子操作。如图6A所示，基底层82形成于载体80上。基底层82可以配置成晶种层和/或结合增强层。在一些实施例中，基底层82可包含能够较佳地粘着到载体80的结合增强材料和晶种层的堆叠。举例来说，结合增强层可包含由物理气相沉积(PVD)形成的钛层，且晶种层可包含铜。介电层422的第一子层4221形成于基底层82上。如图6B所示，介电层422的第二子层4222形成于第一子层4221上。第二子层4222接着例如通过蚀刻进行图案化以暴露第一子层4221。第四导电材料414和第五导电材料415形成于第二子层4222和暴露的第一子层4221上。在一些实施例中，第四导电材料414的材料可包含例如由PVD形成的钛以用于增强粘着性，且第五导电材料413的材料可包含例如铜。
如图6C所示，接着在电路层42完成并如图4D所示结合到第一导电结构10之后从介电层422去除载体80。接着例如通过蚀刻来去除基底层82以暴露第一子层4221。如
图6D所示，开口4221H例如通过蚀刻形成于第一子层4221中。接着去除从开口4221H中暴露的第四导电材料414。如图6E和图4F所示，第二电子组件50形成于介电层422上，且通过导电凸块52电连接到导电布线图案421。在一些实施例中，导电凸块52插入到开口4221H中以增强第二电子组件50与导电布线图案421之间的结合。开口4221H可部分或完全充满导电凸块52。
图7是根据本公开的一些实施例的半导体设备封装3的横截面图。如图7所示，半导体设备封装3包含第一导电结构10、钝化层32和第二导电结构40。钝化层32安置在第一导电结构10的上部电路层14a上。钝化层32包含部分地暴露上部电路层14a的多个开口32H。第二导电结构40进一步包含电连接到上部电路层14a的多个导电凸块46。导电凸块46延伸到钝化层32的开口32H中以增强第二导电结构40与第一导电结构10之间的结合鲁棒性。导电凸块46可包含例如焊球或焊膏等焊料、例如金属支柱等金属连接器，或其它合适的导电凸块导电凸块。与图3的半导体设备封装2相对比，半导体设备封装3的底部填充层48的边缘48E可从第二导电结构40的边缘40E伸出。在一些实施例中，导电通孔42V可具有但不限于倒梯形横截面形状。
图8A、图8B、图8C、图8D和图8E说明根据本公开的一些实施例的制造半导体设备封装3的操作。半导体设备封装3的制造操作可在图4A中说明的制造操作之后执行。如图8A所示，多个第二导电结构40形成于载体80上。第二导电结构40可包含至少一个电路层42，所述电路层包含多个导电布线图案421和多个介电层422。导电布线图案421和介电层422可通过在载体80上交替地形成介电材料层和导电层而形成。
如图8B所示，多个第二电子组件50结合到第二导电结构40。在一些实施例中，例如焊料凸块等导电凸块52用以将第二电子组件50结合到第二导电结构40。在一些实施例中，底部填充层53可围绕导电凸块52形成于第二电子组件50与第二导电结构40之间。囊封层54形成于第二导电结构40上以囊封第二电子组件50。在一些实施例中，囊封层54可囊封第二电子组件50的侧壁和上表面。可对囊封层54进行研磨以暴露第二电子组件50的上表面。囊封层54可进一步覆盖第二导电结构40的边缘40E和底部填充层48的边缘48E。
如图8C所示，去除载体80。多个导电凸块46形成于第二导电结构40的电路层42上。如图8D所示，第二导电结构40和第二电子组件50经单分。如图8E所示，经单分第二导电结构40通过插入到钝化层32的开口32H中并电连接上部电路层14a的导电凸块46结合到第一导电结构10。底部填充层48接着形成于钝化层32与第二导电结构40之间，且围绕导电凸块46。例如焊球等电导体17形成于底部RDL 16上以形成半导体设备封装3，如图7中所说明。
在本公开的一些实施例中，半导体设备封装包含嵌入于衬底中的无源电子组件，所述无源电子组件可减小半导体设备封装的总厚度。有源电子组件竖直地堆叠于无源电子组件上。因此，无源电子组件与有源电子组件之间的信号发射路径可缩短，且信号发射期间的能量损耗可减小。此外，功率消耗可降低，且性能可以改进。半导体设备封装进一步包含安置于第一导电结构与第二导电结构之间的应力缓冲层。应力缓冲层的CTE在第一导电结构的CTE与第二导电的CTE之间，如此可以缓解翘曲和分层问题。应力缓冲层也可配置为用于第一导电结构的平坦层面，且因此第二导电结构可直接制造于第一导电结构上而不需要大尺寸的焊球。因此，可以改进电学性能。半导体设备封装进一步包含安置于第一导电结构与第二导电结构之间的经图案化钝化层。钝化层的开口允许第二导电结构的导电凸块插入，因此第二导电结构与第一导电结构之间的结合鲁棒性得以增强。钝化层可为光敏钝化层，所述光敏钝化层可通过光刻操作进行图案化，因此开口的尺寸可以最小化至例如低于50微米。相应地，可以增加I/O连接的数目。总之，本公开的半导体设备封装是混合设备封装，提供了集成例如导电衬底等低密度导电结构、例如电容器等无源电子组件、例如扇出电路等高密度导电结构和例如ASIC组件或存储器组件等有源电子组件的解决方案。
除非上下文另外明确规定，否则如本文所用，单数术语“一(a/an)”和“所述”可包含多个指示物。
如本文中所使用，术语“大致”、“大体上”、“实质”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％)，那么可认为所述两个数值“大体上”相同或相等。举例来说，“大体上”平行可以指代相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。举例来说，“大体上”垂直可能是指相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或者小于或等于±0.05°。
此外，有时在本文中以范围格式呈现量、比率和其它数值。应理解，此范围格式是为了便利和简洁而使用，且应灵活地理解，不仅包含明确地规定为范围极限的数值，而且包含涵盖于那个范围内的所有个体数值或子范围，如同明确地规定每个数值和子范围一般。
尽管已参考本公开的特定实施例描述并说明本公开，但这些描述和说明并不限制本公开。所属领域的技术人员应理解，可在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下，作出各种改变且取代等效物。说明可能未必按比例绘制。归因于制造过程和公差，本发明中的艺术再现与实际装置之间可能存在区别。可存在未特定说明的本公开的其它实施例。应将本说明书和图式视为说明性而非限制性的。可进行修改，以使特定情形、材料、物质组成、方法或工艺适宜于本发明的目标、精神和范围。所有此些修改都打算属于在此所附权利要求书的范围内。虽然本文中所公开的方法是参考按特定次序执行的特定操作描述的，但是应理解，这些操作可组合、细分或重新排序以形成等效方法而不脱离本公开的教示内容。因此，除非本文中特别指示，否则操作的次序和分组不是对本公开的限制。

Claims (20)

1.一种半导体设备封装，其包括：
第一导电结构，其包括：
衬底；
嵌入于所述衬底中的至少一个第一电子组件；以及
安置在所述衬底上并电连接到所述第一电子组件的第一电路层，其中所述第一电路层包括导电布线图案；
安置在所述衬底上的应力缓冲层，其中所述第一电路层的所述导电布线图案延伸穿过所述应力缓冲层；以及
安置在所述应力缓冲层和所述第一电路层上的第二导电结构。
2.根据权利要求1所述的半导体设备封装，其中所述应力缓冲层的热膨胀系数CTE在所述第一导电结构的CTE与所述第二导电结构的CTE之间。
3.根据权利要求1所述的半导体设备封装，其中所述应力缓冲层的上表面与所述导电布线图案的上表面大体上共面。
4.根据权利要求1所述的半导体设备封装，其中所述导电布线图案的所述上表面稍微低于所述应力缓冲层的所述上表面。
5.根据权利要求1所述的半导体设备封装，其中所述第一电路层包括衬底级电路层。
6.根据权利要求1所述的半导体设备封装，其中所述第二导电结构包括电连接到所述第一电路层的第二电路层。
7.根据权利要求6所述的半导体设备封装，其中所述第二电路层包括凸块级电路层。
8.根据权利要求6所述的半导体设备封装，其中所述第一电路层与所述第二电路层之间的接头是无焊接头。
9.根据权利要求1所述的半导体设备封装，其中所述第一导电结构的边缘与所述第二导电结构的边缘大体上对齐。
10.根据权利要求1所述的半导体设备封装，其进一步包括：
安置在所述第二导电结构上并电连接到所述第二导电结构的至少一个第二电子组件，其中所述第一电子组件包括无源电子组件，且所述第二电子组件包括有源电子组件；以及
囊封所述第二电子组件的囊封层。
11.根据权利要求10所述的半导体设备封装，其中所述有源电子组件包括集成电路IC组件、存储器组件或其组合。
12.一种半导体设备封装，其包括：
第一导电结构，其包括：
衬底；
嵌入于所述衬底中的至少一个第一电子组件；以及
安置在所述衬底上并电连接到所述第一电子组件的第一电路层；
安置在所述第一电路层上的钝化层，其中所述钝化层包含部分地暴露所述第一电路层的多个开口；以及
安置在所述钝化层上的第二导电结构，其中所述第二导电结构包括延伸到所述钝化层的所述开口中并电连接到所述第一电路层的多个第一导电凸块。
13.根据权利要求12所述的半导体设备封装，其中所述钝化层的材料包括固化光敏材料。
14.根据权利要求12所述的半导体设备封装，其进一步包括安置于所述钝化层与所述第二导电结构之间的底部填充层，其中所述底部填充层的边缘与所述第二电子组件的边缘大体上对齐。
15.根据权利要求12所述的半导体设备封装，其中所述第二导电结构包括电连接到所述第一电路层的第二电路层。
16.根据权利要求15所述的半导体设备封装，其中所述第一电路层包括衬底级电路层，且所述第二电路层包括凸块级电路层。
17.根据权利要求12所述的半导体设备封装，其进一步包括：
安置在所述第二导电结构上的至少一个第二电子组件，其中所述第一电子组件包括无源电子组件，且所述第二电子组件包括有源电子组件；
安置于所述第二电子组件与所述第二导电结构之间且电连接到所述第二电子组件和所述第二导电结构的多个第二导电凸块；以及
囊封所述第二电子组件的囊封层。
18.一种制造半导体设备封装的方法，其包括：
形成第一导电结构，所述第一导电结构包含其中嵌入了至少一个第一电子组件的衬底，和安置在所述衬底上的电路层；
在所述第一电路层上形成应力缓冲层，其中所述应力缓冲层包含多个开口；
在所述应力缓冲层的所述开口中形成导电布线图案；以及
在所述应力缓冲层上形成电连接到所述导电布线图案的第二导电结构。
19.根据权利要求18所述的方法，其中所述应力缓冲层的热膨胀系数CTE被选择在所述第一导电结构的CTE与所述第二导电结构的CTE之间以平衡应力变化。
20.根据权利要求18所述的方法，其中所述在所述应力缓冲层的所述开口中形成所述导电布线图案包括：
在所述应力缓冲层上和所述应力缓冲层的所述开口中形成导电材料；以及
去除在所述应力缓冲层的所述开口外部的所述导电材料，使得所述应力缓冲层的上表面与所述导电布线图案的上表面大体上共面。
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