TWI489612B - 三維積體電路內連結的製造方法 - Google Patents

三維積體電路內連結的製造方法 Download PDF

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TWI489612B
TWI489612B TW102114131A TW102114131A TWI489612B TW I489612 B TWI489612 B TW I489612B TW 102114131 A TW102114131 A TW 102114131A TW 102114131 A TW102114131 A TW 102114131A TW I489612 B TWI489612 B TW I489612B
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layer
package unit
metal
integrated circuit
carrier substrate
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TW201349446A (zh
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Chun Hui Yu
Kuo Chung Yee
Chen Hua Yu
Yeong Jyh Lin
Chia Hsiang Lin
Liang Ju Yen
Lawrence Chiang Sheu
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Taiwan Semiconductor Mfg Co Ltd
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

三維積體電路內連結的製造方法
本發明係關於一種三維積體電路的製造方法，更特別關於一種三維積體電路內連結的製造方法。
從積體電路的發明以來，由於各種電子元件(例如電晶體，二極體，電阻器等等)之整合密度連續的提升，使得半導體產業連續快速地成長。對大多數元件而言，整合密度之提升來自於不斷地降低特徵尺寸，以允許更多的元件整合於既定面積之中。由於對具有更小體積電子設備之需求不斷的成長，半導體工業需要更小以及更富有創造性的半導體晶片的封裝技術。
為了解決上述之限制，三維(3D)積體電路被發展出來提供一更有效率地途徑來降低半導體晶片的尺寸。在三維(3D)積體電路中，主動電路(例如邏輯、記憶、處理電路等)係在不同晶圓上製造而成，且每一晶圓切割所得之晶粒係使用拾取及置放技術來加以堆疊至等以及每個晶圓模具使用拾取和放置技術的包裝組件的頂部上堆疊至封裝單元之上。如此一來，可形成三維積體電路增加主動電路的集積密度。總而言之，三維積體電路具有更小尺寸、更高成本效益、更高性能、以及更低功耗等優點。
一般來說，三維積體電路可包含三維積體電路晶片、中介層(interposer)、以及封裝基板。尤其，該三維積體電路晶片經由複數的銲料凸塊以接合至該中介層(interposer)的第一側。銲料凸塊係用來提供該三維積體電路晶片與該中介層(interposer)間的電性連結。此外，該封裝基板係藉由複數的互連凸塊接合至該中介層(interposer)的第二側。互連凸塊(例如銲球)提供該中介層(interposer)與該封裝基板間的電性連結，其中該封裝基板可藉由複數的封裝引線(package leads)來與一印刷電路板達到電性連結。
為降低由熱應力所引起的三維積體電路晶片與封裝基板間的焊料連接故障可能性(potential solder failure)，所使用的中介層(interposer)其熱膨脹係數必需與三維積體電路晶片的熱膨脹係數接近。該中介層(interposer)係用來轉接三維積體電路晶片上具有較小間距的小接觸墊與封裝基板上具有較大間距的大接觸墊。此外，該中介層(interposer)可更包含各種不同的電路元件，例如主動元件、被動元件、或主動與被動元件的組合。三維積體電路有許多優點。採用垂直封裝半導體晶片的優點之一係可降低製造成本。此外，三維積體電路另一優點係藉由該互連凸塊可降低寄生損失(parasitic losses)。
本發明一實施例提供一種三維積體電路內連結的製造方法，包含：形成一金屬層於一第一承載基板；將一封裝單元與該金屬層接合，其中該封裝單元的一第一側係與該金屬層接觸，且該封裝單元包含複數貫孔；藉由電化學電鍍製程將 一金屬材料填入該複數貫孔中，其中在該電化學電鍍製程中該金屬層係作為一電極；將一第二承載基板與該封裝單元接合，其中該封裝單元的一第一側係與該第二承載基板接觸；將該第一承載基板由該封裝單元上移除；以及，移除該金屬層露出的部份，以形成一重佈線層於該封裝單元的該第一側。
本發明另一實施例提供一種三維積體電路內連結的製造方法，包含形成一金屬箔層於一第一承載基板之上；將一封裝單元接合至該金屬箔層之上，其中該封裝單元的一第一側係與該金屬箔層接觸，其中該封裝單元包含複數貫孔；以及，對該封裝單元施以一電化學電鍍製程，使得一金屬材料填入該複數貫孔形成複數金屬連線，其中在該電化學電鍍製程中該金屬箔層係作為一電極。
此外，本發明其他實施例提供一種三維積體電路內連結的製造方法，包含：形成一重佈線層於一封裝單元之一第一側，其中形成該重佈線層的方法包含：形成一金屬層於一第一承載基板之上；將一封裝單元形成於該金屬層之上，其中該封裝單元的一第一側係與該金屬層接觸，且該封裝單元包含複數貫孔；以電化學電鍍製程將一金屬材料填入該複數貫孔中，其中在該電化學電鍍製程中該金屬箔層係作為一電極；將一第二承載基板接合至該封裝單元的一第二側；將該第一承載基板由該封裝單元上移除；形成一光阻層於該金屬層之上；圖案化該光阻層；以及，對該金屬層露出部份進行蝕刻，形成該重佈線層於該封裝單元的該第一側；形成一凸塊底層金屬結構於該重佈線層之上；以及，形成一互連凸塊於該凸塊底層金屬 結構之上。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧三維積體電路
102‧‧‧三維積體電路晶片
104‧‧‧封裝層
106‧‧‧封裝單元
108‧‧‧絕緣層
110‧‧‧互連凸塊
112‧‧‧凸塊底層金屬結構
114‧‧‧重佈線層
116‧‧‧貫孔
120‧‧‧銲球
122‧‧‧金屬柱凸塊
124‧‧‧重佈線層
202‧‧‧第一承載基板
204‧‧‧介電層
206‧‧‧銅箔層
208‧‧‧貫孔
502‧‧‧第二承載基板
702‧‧‧圖案化光阻層
704、802‧‧‧開口
第1圖係一剖面結構示意圖，說明本發明一實施例所述之三維積體電路；第2圖係一剖面結構示意圖，說明本發明一實施例所述將一中介層(interposer)配置於一第一承載基板之上；第3圖係一剖面結構示意圖，說明將第2圖所示結構之部份介電層移除；第4圖係一剖面結構示意圖，說明形成導電連結於第2圖所示結構之中介層(interposer)的複數貫孔中；第5圖係一剖面結構示意圖，說明將一第二承載基板接合至第4圖所示結構之中介層(interposer)的第二側之上；第6圖係一剖面結構示意圖，說明將第一承載基板由第5圖所示結構移除；第7圖係一剖面結構示意圖，說明在第6圖所示結構之銅箔層上形成一圖案化光阻層；第8圖係一剖面結構示意圖，說明以該圖案化光阻層作為罩幕來移除第7圖所示結構之部份銅箔層；第9圖係一剖面結構示意圖，說明將第8圖所示結構之圖案化光阻層移除的步驟，得到本發明一實施例所述之三維積體電 路內連結。
較佳實施例的製造與應用將詳細討論如下。然而，本發明提供許多可應用的創新概念，這些創新概念可在各種特定背景中加以體現。所討論之特定實施例僅係用以舉例說明製造與應用本發明之特定方式，並非用以限制本發明之範圍。
本發明將以三維積體電路之特定實施例來作描述。然而，本發明亦可應用在其他的半導體裝置。為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：第1圖係一剖面結構示意圖，說明本發明一實施例所述之三維積體電路。該三維積體電路100可包含一三維積體電路晶片102堆疊於該封裝元件106之上。請參照第1圖，該三維積體電路晶片102係經由複數內連結單元(例如包含金屬柱凸塊122、微凸塊120、以及重佈線層(redistribution layer)124)接合至該封裝元件106之第一側。此外，一封裝層104可形成於該封裝單元106之上。尤其，該積體電路102以及該內連結單元(例如微凸塊120、以及重佈線層(redistribution layer)124)係嵌入該封裝層104中。
根據本發明一實施例，該封裝單元106可以是一中介層(interposer)。換言之，該封裝單元106可被視為一中介層(interposer)106)。該中介層(interposer)106之材質可為矽、或是玻璃等。請參照第1圖，該中介層(interposer)106可包含複數 貫孔116嵌入該中介層(interposer)106中。該中介層(interposer)106可更包一第一重佈線層(redistribution layer)124形成於該中介層(interposer)106之第一側。在將該三維積體電路晶片102接合於該中介層(interposer)106之上後，該三維積體電路晶片102之主動電路可藉由該重佈線層(redistribution layer)124、微凸塊120、以及該金屬柱凸塊122耦接至該中介層(interposer)106。一封裝基板(未圖示)可藉由複數互連凸塊110接合至該中介層(interposer)106之第二側。根據本發明一實施例，該互連凸塊110可例如為銲球。請參照第1圖，該重佈線層(redistribution layer)124係與填入其對應貫孔116內之金屬電性連結。此外，填入貫孔116內的金屬導線係藉由一重佈線層(redistribution layer)114以及一凸塊底層金屬結構(under bump metallization structure)112與對應之互連凸塊110達到電性連結。該封裝層104係配置於一絕緣層108內。如此一來，該金屬柱凸塊(metal pillar bump)122、銲球120、重佈線層(redistribution layer)124、填入貫孔116的金屬導線、重佈線層(redistribution layer)114、凸塊底層金屬結構(under bump metallization structure)112、以及該互連凸塊110構成一位於該三維積體電路晶片102之主動電路與該封裝基板(未圖示)間的導電途徑，使得之後可藉由複數封裝引線(package leads)以與一印刷電路板達到電性連結。
第2至9圖係為一系列剖面結構示意圖，用以說明本發明一實施例所述的三維積體電路的製造方法。請參照第2圖，係為一剖面結構示意圖，用以說明本發明一實施例所述將 一中介層(interposer)配置於一第一承載基板之上。該第一承載基板202之材質並無限定，可為玻璃、矽、或陶瓷等。仍請參照第2圖，一金屬層206形成於該第一承載基板202之上。根據本發明一實施例，該金屬層206可為一銅箔層。根據本發明另一實施例，該金屬層206亦可為其他適合的導電材料，例如銅合金、鋁、鎢、銀、或其組合。在此，該金屬層206可視為一銅箔層206。該銅箔層206係配置於該承載基板202之上。詳細地說，該銅箔層206可以藉由一第一黏著層(未圖示)以黏貼的方式配置於該第一承載基板202之上。根據本發明一實施例，該第一黏著層之材質可例如為環氧樹脂。
一介電層204形成於該銅箔層206之上。該介電層204可以是一光阻材料或是一非光阻材料。根據本發明一實施例，該介電層204之材質可為一光阻材料，例如聚苯噁唑(polybenzoxazole,PBO)、化學增幅型光敏環氧樹脂(商品名SU-8)、或薄膜型高分子材料等。
該中介層(interposer)106之材質可為矽、或玻璃。該中介層(interposer)106可具有複數的貫孔208貫穿該中介層(interposer)106。根據本發明一實施例，該中介層(interposer)106可具有一厚度介於50至800μm。該中介層(interposer)106係接合於該第一承載基板202之上。詳細地說，該中介層(interposer)106可以藉由該介電層204以黏貼的方式配置於該銅箔層206之上。
第3圖係一剖面結構示意圖，用以說明將第2圖所示結構之部份介電層移除。該介電層204未被該中介層 (interposer)106所覆蓋的部份可使用任何合適的方法來加以移除，例如化學顯影、雷射剝離、或乾蝕刻。
第4圖係一剖面結構示意圖，用以說明形成導電連結於該中介層(interposer)的複數貫孔中。請參照第4圖，可對該中介層(interposer)施以一電化學電鍍製程，以使得導電材料填入該中介層(interposer)106的複數之貫孔208中，形成複數之導電連結116。該導電材料可以為銅，亦可為任何合適的導電材料，例如銅合金、鋁、鎢、銀、或其組合。在上述電化學電鍍製程中，該銅箔層係作為一電極以促進該電化學電鍍製程。
在傳統矽導通孔(TSV)的製程中，可包含以下步驟：形成一晶種層、電鍍導電材料於該晶種層之上、施以一化學機械研磨製程以及一磨化製程以露出導電連結。本發明第4圖所述之導電連結的形成方式與傳統矽導通孔(TSV)的製程相比之下，不需要額外形成一晶種層。取而代之的，係對該銅箔層206進行一由下往上的電化學電鍍製程。本發明所述由該銅箔層206之優點之一係該下往上的電化學電鍍製程可避免製程缺陷(defect)例如空洞形成於該導電連結中。若空洞形成於導電連結中會使得該三維積體電路的信賴性(reliability)降低。此外，對該銅箔層進行以由下往上的電化學電鍍製程可不需要形成晶種層，如此一來可降低製程成本以及改善製程效率。此外，該由下往上的電化學電鍍製程可提供額外的好處，例如不會被貫孔側壁表面粗糙度所影響、以及較不會受貫孔高寬比的限制。
第5圖係一剖面結構示意圖，用以說明將一第二承 載基板502接合至第4圖所示結構之該中介層(interposer)的第二側之上。所使用的第二承載基板502可與該第一承載基板202相同，故在此不再贅述。一第二黏著層(未圖示)可用來將該第二承載基板502黏貼至該中介層(interposer)106之上。根據本發明一實施例，該第二黏著層之材質可例如環氧樹脂。
第6圖係一剖面結構示意圖，用以說明將第一承載基板由第5圖所示結構移除。根據本發明一實施例，該第一承載基板202可由該中介層(interposer)106之上分離。換言之，一分離製程(detaching processes)可被用來施於該中介層(interposer)106以移除該第一承載基板202。舉例來說，該分離製程(detaching processes)可例如為使用一化學溶劑或是紫外線曝光來移除該第一黏著層。
第7圖係一剖面結構示意圖，用以說明在第6圖所示結構之銅箔層上形成一圖案化光阻層。將一圖案化光阻層702形成於該銅箔層206之上。該光阻層702之材質可包含化學增幅型光敏環氧樹脂(商品名SU-8)、或薄膜型高分子材料等。該圖案化光阻層702具有複數之開口704形成於其中。該圖案化光阻層702可例如以一微影蝕刻製程來加以形成。
第8圖係一剖面結構示意圖，用以說明以該圖案化光阻層作為罩幕來移除第7圖所示結構之部份銅箔層，得到開口802。根據本發明一實施例，以該圖案化光阻層702作為罩幕來移除銅箔層206的方法可例如為濕蝕刻、或乾蝕刻。因此，露出的銅箔層206(即未被該圖案化光阻層702所覆蓋銅箔層206)在此步驟中被移除，得到一重佈線層(redistribution layer)114。
第9圖係一剖面結構示意圖，用以說明將第8圖所示結構之圖案化光阻層移除的步驟。移除該圖案化光阻層702的方法不無限制，可為習知之任何合適的光阻剝除製程，例如化學溶劑清洗法、電漿灰化法、或乾式剝離法等。值得說明的是，雖然第9圖繪示該中介層(interposer)106僅具有一單層的重佈線層(redistribution layer)114，不過本發明並不限定該中介層上重佈線層的層數。根據本發明其他實施例，該中介層(interposer)106上亦可具有多層的重佈線層(redistribution layer)。本發明所述三維積體電路的製造方法的優點之一可藉由對銅箔層施以一蝕刻製程，得到一重佈線層(redistribution layer)，如此一來不需要額外形成一晶種層及額外的電化學電鍍製程，因此降低製程成本以及改善製程效率。
前述已揭露了本發明數個具體實施方式的特徵，使此領域中具有通常技藝者得更加瞭解本發明細節的描述。此領域中具有通常技藝者應能完全明白且能使用所揭露之技術特徵，做為設計或改良其他製程和結構的基礎，以實現和達成在此所介紹實施態樣之相同的目的和優點。此領域中具有通常技藝者應也能瞭解這些對應的說明，並沒有偏離本發明所揭露之精神和範圍，且可在不偏離本發明所揭露之精神和範圍下進行各種改變、替換及修改。
100‧‧‧三維積體電路
102‧‧‧三維積體電路晶片
104‧‧‧封裝層
106‧‧‧封裝單元
108‧‧‧絕緣層
110‧‧‧互連凸塊
112‧‧‧凸塊底層金屬結構
114‧‧‧重佈線層
116‧‧‧貫孔
120‧‧‧銲球
122‧‧‧金屬柱凸塊
124‧‧‧重佈線層

Claims (10)

  1. 一種三維積體電路內連結的製造方法，包含：形成一金屬層於一第一承載基板；將一封裝單元與該金屬層接合，其中該封裝單元的一第一側係與該金屬層接觸，且該封裝單元包含複數貫孔；藉由電化學電鍍製程將一金屬材料填入該複數貫孔中，其中在該電化學電鍍製程中該金屬層係作為一電極；將一第二承載基板與該封裝單元接合，其中該封裝單元的一第一側係與該第二承載基板接觸；將該第一承載基板由該封裝單元上移除；以及移除該金屬層露出的部份，以形成一重佈線層於該封裝單元的該第一側。
  2. 如申請專利範圍第1項所述之三維積體電路內連結的製造方法，更包含：形成一第一黏著層於該第一承載基板之上；以及將該金屬層接合至該第一黏著層之上。
  3. 如申請專利範圍第1項所述之三維積體電路內連結的製造方法，更包含：形成一介電層於該金屬層之上；以及將該封裝單元接合至該介電層之上。
  4. 如申請專利範圍第3項所述之三維積體電路內連結的製造方法，更包含：移除該介電層露出的部份。
  5. 如申請專利範圍第1項所述之三維積體電路內連結的製造 方法，更包含：形成一高分子黏著層於該金屬層之上；以及圖形化該高分子黏著層。
  6. 一種三維積體電路內連結的製造方法，包含：形成一金屬箔層於一第一承載基板之上；將一封裝單元接合至該金屬箔層之上，其中該封裝單元的一第一側係與該金屬箔層接觸，其中該封裝單元包含複數貫孔；以及對該封裝單元施以一電化學電鍍製程，使得一金屬材料填入該複數貫孔形成複數金屬連線，其中在該電化學電鍍製程中該金屬箔層係作為一電極。
  7. 如申請專利範圍第6項所述之三維積體電路內連結的製造方法，更包含：將該封裝單元接合至一第二承載基板，其中該封裝單元的一第二側係與該第二承載基板接觸；以及將該第一承載基板由該封裝單元上移除。
  8. 如申請專利範圍第6項所述之三維積體電路內連結的製造方法，更包含：形成一光阻層於該金屬層之上；圖案化該光阻層；以該圖案化光阻層作為蝕刻罩幕對該金屬箔層進行蝕刻，形成一重佈線層；以及利用一光阻剝除製程移除該圖案化光阻層。
  9. 一種三維積體電路內連結的製造方法，包含： 形成一重佈線層於一封裝單元之一第一側，其中形成該重佈線層的方法包含：形成一金屬層於一第一承載基板之上；將一封裝單元形成於該金屬層之上，其中該封裝單元的一第一側係與該金屬層接觸，且該封裝單元包含複數貫孔；以電化學電鍍製程將一金屬材料填入該複數貫孔中，其中在該電化學電鍍製程中該金屬箔層係作為一電極；將一第二承載基板接合至該封裝單元的一第二側；將該第一承載基板由該封裝單元上移除；形成一光阻層於該金屬層之上；圖案化該光阻層；以及，對該金屬層露出部份進行蝕刻，形成該重佈線層於該封裝單元的該第一側；形成一凸塊底層金屬結構於該重佈線層之上；以及形成一互連凸塊於該凸塊底層金屬結構之上。
  10. 如申請專利範圍第9項所述之三維積體電路內連結的製造方法，更包含：形成一第二重佈線層形成於該封裝單元之該第二側；經由該互連凸塊將一半導體晶片接合至該封裝單元之該第二側；以及形成一封裝層 於該封裝單元之上。
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