TW201712828A - 半導體封裝結構及形成該半導體封裝結構的方法 - Google Patents

半導體封裝結構及形成該半導體封裝結構的方法 Download PDF

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TW201712828A
TW201712828A TW105126198A TW105126198A TW201712828A TW 201712828 A TW201712828 A TW 201712828A TW 105126198 A TW105126198 A TW 105126198A TW 105126198 A TW105126198 A TW 105126198A TW 201712828 A TW201712828 A TW 201712828A
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semiconductor
semiconductor die
package structure
semiconductor package
conductive
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TW105126198A
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TWI587467B (zh
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郭哲宏
周哲雅
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聯發科技股份有限公司
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Abstract

提供了一種半導體封裝結構。該半導體封裝結構包括第一半導體晶粒，具有第一活性表面和第一非活性表面；第二半導體晶粒，具有第二活性表面和第二非活性表面，該第二半導體晶粒堆疊在該第一半導體晶粒上，以及，該第一非活性表面面向該第二非活性表面；第一重佈線層結構，其中，該第一活性表面面向該第一重佈線層結構；以及第二重佈線層結構，其中，該第二活性表面面向該第二重佈線層結構。相應地，還提供了一種用於形成半導體封裝結構的方法。該半導體裝結構可以減少封裝尺寸。

Description

半導體封裝結構及形成該半導體封裝結構的方法
本發明涉及一種半導體封裝結構，以及更特別地，涉及一種多晶粒(multi-die)的半導體封裝結構及形成該半導體封裝結構的方法。
隨著如與3C(電腦(Computer)、通訊(Communication)以及消費電子(Consumer electronic)有關的這些電子產業的持續發展，消費者對多功能、更便捷以及更小的設備需求迅速增加。該需求驅動了積體電路(integrated circuit，IC)密度增大的必要。輸入/輸出(input-output，I/O)引腳數量的增加以及對積體電路密度的增大需求已帶來多晶粒封裝的發展。隨著對高性能和高集成度的需求，雙晶粒扇出式(fan-out)晶圓級晶片級封裝(wafer level chip scale package，WLCSP)、矽通孔(through silicon via，TSV)技術以及三維封裝體疊層(three-dimensional package on package，3D PoP)結構已被接受為一些替代選擇。
然而，雙晶粒扇出式晶圓級晶片級封裝(WLCSP)包括兩個並排(side by side)設置的晶粒。因此，封裝尺寸太大，且翹曲變形(warpage)是需要關心的問題。矽通孔(TSV) 技術包括形成貫穿(penetrating)複數個晶粒的矽通孔(TSV)。因此，製造成本高，以及浪費晶粒的面積。三維封裝體疊層(3D PoP)結構在底部封裝上堆疊頂部封裝。因此，這甚至難以進一步減少三維封裝體疊層(3D PoP)結構的厚度。
因此，需求一種新穎的半導體封裝結構以及形成該半導體封裝結構的方法。
有鑑於此，本發明的目的之一在於提供一種半導體封裝結構以及形成該半導體封裝結構的方法，以解決上述問題。
第一方面，本發明的示例性實施例提供了一種半導體封裝結構，該半導體封裝結構包括一第一半導體晶粒，該第一半導體晶粒包括第一活性表面和第一非活性表面。該半導體封裝結構還包括一第二半導體晶粒，該第二半導體晶粒包括第二活性表面和第二非活性表面。其中，該第二半導體晶粒堆疊在該第一半導體晶粒上，以及，第一非活性表面面向第二非活性表面。該半導體封裝結構還包括一第一重佈線層結構，第一活性表面面向該第一重佈線層結構。此外，該半導體封裝結構還包括一第二重佈線層結構，第二活性表面面向該第二重佈線層結構。
第二方面，本發明的另一示例性實施例提供了一種半導體封裝結構，該半導體封裝結構包括一第一半導體晶粒，該第一半導體晶粒包括第一導電墊，其中，該第一半導體晶粒具有第一表面和與該第一表面相對的第二表面，該第一導 電墊位於該第一表面上；一第二半導體晶粒，包括第二導電墊，其中，該第二半導體晶粒垂直地堆疊在該第一半導體晶粒上，該第二半導體晶粒具有第三表面和與該第三表面相對的第四表面，該第一導電墊位於該第三表面上，該第二表面面向該第四表面；以及模塑膠，圍繞該第一半導體晶粒和該第二半導體晶粒。
第三方面，本發明的示例性實施例提供了一種用於形成半導體封裝結構的方法，包括：提供一第一半導體晶粒，該第一半導體晶粒包括第一非活性表面。該方法還包括：將一第二半導體晶粒堆疊在該第一半導體晶粒上；其中，該第一半導體晶粒的第一非活性表面面向該第二半導體晶粒的第二非活性表面。該方法還包括：形成圍繞該第一半導體晶粒和該第二半導體晶粒的模塑膠。
在上述技術方案中，本發明提供了一種新穎的半導體封裝結構及形成該半導體封裝結構的方法，該半導體封裝結構包括以背靠背方式堆疊的兩個半導體晶粒，可以減小封裝尺寸。
本領域技術人員在閱讀附圖所示優選實施例的下述詳細描述之後，可以毫無疑義地理解本發明的這些目的及其它目的。
110‧‧‧導電孔
200c、400c‧‧‧側壁
410、210、2410、2310‧‧‧導電墊
420、220‧‧‧鈍化層
400、200、2300、2400‧‧‧半導體晶粒
430、230‧‧‧導電結構
440、240‧‧‧底部填充層
400a、200a‧‧‧活性表面
400b、200b‧‧‧非活性表面
100‧‧‧載體基板
500、2600‧‧‧模塑膠
600、800‧‧‧重佈線層結構
610、810‧‧‧第一子介電層
620‧‧‧導電跡線
630、830‧‧‧第二子介電層
700‧‧‧支撐基板
820‧‧‧第一導電跡線
840‧‧‧第二導電跡線
850‧‧‧第三子介電層
900、2100‧‧‧導電組件
910‧‧‧凸塊下金屬層
300‧‧‧粘接層
1000A、1000B、1000C、1000D、2000‧‧‧半導體封裝
660‧‧‧開孔
650‧‧‧阻焊層
2500‧‧‧接合引線
2200‧‧‧基座
通過閱讀後續的詳細描述和實施例可以更全面地理解本發明，該實施例參照附圖給出，其中：第1A圖至第1E圖係根據本發明一些實施例的一種用於形 成半導體封裝結構的各個階段的剖視圖；第2圖係根據本發明一些實施例的一種半導體封裝結構的剖視圖；第3圖係根據本發明一些實施例的一種半導體封裝結構的剖視圖；第4圖係根據本發明一些實施例的一種半導體封裝結構的剖視圖；第5圖係根據本發明一些實施例的一種半導體封裝結構的剖視圖。
為使本發明之上述目的、特徵和優點能更明顯易懂，下面特舉實施例並配合所附圖式，作詳細說明如下。
以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及所附的申請專利範圍當中使用了某些詞彙來指稱特定的組件。所屬領域技術人員應可理解，製造商可能會用不同的名詞來稱呼同樣的組件。本說明書及申請專利範圍並不以名稱的差異來作為區別組件的方式，而是以組件在功能上的差異來作為區別的基準。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於…”的意思。在附圖中，為了說明目的，一些組件的尺寸可能被誇大而不是按比例繪製。附圖中的尺寸和相對尺寸可以或可以不對應于本發明實踐中的實際尺寸。
第1A圖至第1E圖係根據本發明一些實施例的一 種用於形成半導體封裝結構的各個階段的剖視圖。在第1A圖至第1E圖所描述的各階段之前、期間和/或之後均可以提供附加的操作。對於不同的實施例，所描述的一些階段可以被替換或消除。附加的特徵可以被添加至該半導體封裝結構。對於不同的實施例，以下描述的一些特徵可以被替換或消除。為了簡化附圖，第1A圖至第1E圖中僅示出半導體封裝結構的一部分。
如第1A圖所示，提供載體基板(carrier substrate)100。載體基板100是臨時性(temporary)基板，以及，將在後續的步驟中被移除。在一些實施例中，載體基板100為晶圓(wafer)或面板(panel)。在一些實施例中，載體基板100包括玻璃、矽，或其它合適的載體材質。
如第1A圖所示，一個或複數個導電孔(conductive via)110被形成在載體基板100上。導電孔110為封裝通孔(through package vias，TPV)。在一些實施例中，導電孔110包括銅或其它合適的導電材質。
如第1A圖所示，半導體晶粒200被提供在載體基板100上。在一些實施例中，半導體晶粒200是翻轉的，以及通過粘接層(adhesive layer)(未示出，該粘接層將在後續的步驟中被移除)附著於(attached to)載體基板100。在另一些實施例中，複數個半導體晶粒200被提供在載體基板100上。為方便描述，第1A圖至第1E圖所示的實施例以一個半導體晶粒200被直接提供在載體基板100上為例。但應當說明的是，本發明並不限於此示例情形。
在一些實施例中，半導體晶粒200可以為系統級 晶片(system-on-chip，SOC)、記憶體晶粒(memory die)、邏輯晶粒(logic die)、類比處理器(analog processor，AP)、數位處理器(digital processor，DP)、基帶(baseband，BB)組件、射頻(radio-frequency，RF)組件，或者其它合適的被动(active)電子組件。記憶體晶粒可以是動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒。邏輯晶粒可以是中央處理單元(central processing unit，CPU)、影像處理單元(graphics processing unit，GPU)或動態隨機存取記憶體(DRAM)控制器。半導體晶粒200具有活性表面(active surface)200a、非活性表面(non-active surface)200b和側壁(sidewall)200c。側壁200c基本上垂直於活性表面200a和非活性表面200b。
如第1A圖所示，半導體晶粒200包括一個或複數個導電墊(conductive pad)210，導電墊210位於活性表面200a上。導電墊210面向載體基板100。導電墊210可以位於半導體晶粒200的互連結構中的最頂層中。在一些實施例中，導電墊210可被包括為該互連結構的導電跡線(conductive trace)。為簡化附圖，此處僅描述導電墊210。在一些實施例中，導電墊210可以通過電鍍工藝(electroplating process)、接合工藝(bonding process)或另一適用的工藝形成。
鈍化層(passivation layer)220被設置在活性表面200a上，以及，部分覆蓋導電墊210。鈍化層220包括一個或複數個開孔(opening)。每個開孔露出相應的導電墊210的一部分。如第1A圖所示，每個導電墊210的周圍部分可以被 鈍化層覆蓋，而導電墊210的中央部分從鈍化層露出。
一個或複數個導電結構(conductive structure)230被形成在鈍化層220上，以及，填充鈍化層220的開孔。因此，每一個導電結構230電連接於相應的導電墊210。在一些實施例中，導電結構230可以是導電層的複數個部分。在一些實施例中，導電結構230可以是導電凸塊(conductive bump)(如微凸塊，micro bump)，導電球(ball)或導電柱(pillar)。在另一些實施例中，導電結構230未被形成。
底部填充層(underfill layer)240被形成在鈍化層220上，以及，圍繞導電結構230的上部。在另一些實施例中，底部填充層240未被形成。
在一些實施例中，半導體晶粒200的構造(formation)包括依次形成的導電墊210、鈍化層220、導電結構230以及位於半導體晶圓或面板上的底部填充層240。此後，半導體晶圓或面板被切割為複數個半導體晶粒。半導體晶粒200是已知合格的(即半導體晶粒200為已知合格晶片(known-good die，KGD))，且被提供在載體基板100上。
在一些實施例中，形成導電孔110之後，將半導體晶粒200設置在載體基板100上。在另一些實施例中，形成導電孔110之前，將半導體晶粒200設置在載體基板100上。在一些實施例中，導電孔110比半導體晶粒200厚。
如第1B圖所示，根據本發明的一些實施例，半導體晶粒400被垂直堆疊在半導體晶粒200上。因此，導電孔110、半導體晶粒200和400並排設置。在一些實施例中，導 電孔110比半導體晶粒400厚。
在一些實施例中，半導體晶粒400通過粘接層300附著於半導體晶粒200。粘接層300夾在半導體晶粒200和半導體晶粒400之間。在另一些實施例中，複數個半導體晶粒400被堆疊在半導體晶粒200上。為方便描述，本實施例中以一個半導體晶粒400堆疊在一個半導體晶粒200上為例。但應當說明的是，本發明並不限於此，具體實現中，可以是複數個半導體晶粒400堆疊在一個半導體晶粒200上，也可以是複數個半導體晶粒400被堆疊在複數個半導體晶粒200上，還可以是一個半導體晶粒400堆疊在複數個半導體晶粒200上，具體地，本發明不做限制。
在一些實施例中，半導體晶粒400可以為系統級晶片(SOC)、記憶體晶粒、邏輯晶粒、類比處理器(AP)、數位處理器(DP)、基帶(BB)組件、射頻(RF)組件，或者其它合適的被动電子組件。半導體晶粒400包括活性表面400a、非活性表面400b和側壁400c。側壁400c基本上垂直於活性表面400a和非活性表面400b。
根據本發明的一些實施例，非活性表面400b面向非活性表面200b。在一些實施例中，粘接層300直接接觸非活性表面400b和200b，以及，被夾在非活性表面400b和200b之間。
如第1B圖所示，半導體晶粒400包括一個或複數個導電墊410，導電墊410位於活性表面400a上。導電墊410的面向遠離半導體晶粒200和載體基板100。因此，導電墊210 和410彼此遠離面向。在一些實施例中，導電墊410可以通過電鍍工藝、接合工藝或其它適用的工藝形成。在一些實施例中，半導體晶粒400的結構與構造類似于或相同於半導體晶粒200的結構與構造。因此，為簡潔起見，此處不再贅述關於鈍化層420、導電結構430以及底部填充層440的類似描述。
半導體晶粒200和400可以具有不同的功能。舉例來說，在一些實施例中，半導體晶粒200和400之一為系統級晶片(SOC)，而半導體晶粒200和400之另一為記憶體晶粒。在另一些實施例中，半導體晶粒200和400之一為類比處理器(AP)，而半導體晶粒200和400之另一為數位處理器(DP)。在一些實施例中，半導體晶粒200和400之一為基帶(BB)組件，而半導體晶粒200和400之另一為射頻(RF)組件。在另一些實施例中，半導體晶粒200和400可以具有相同的功能。
在一些實施例中，如第1B圖所示，半導體晶粒200和400具有相同的尺寸。在另一些實施例中，半導體晶粒200和400可以具有不同的尺寸。半導體晶粒200和400可以彼此對齊(align)或不對齊(misalign)。在一些實施例中，半導體晶粒400完全地垂直地堆疊在半導體晶粒200上。因此，側壁400c與側壁200c基本共面(coplanar)。在另一些實施例中，半導體晶粒400部分地垂直堆疊在半導體晶粒200上(例如，對於半導體晶粒400窄於半導體晶粒200的情形)。因此，側壁400c與側壁200c不共面。
如第1B圖所示，模塑膠(molding compound)500 被形成在載體基板100上。模塑膠500圍繞導電孔110、半導體晶粒200和400，以及粘接層300。模塑膠500鄰接(adjoin)側壁200c和400c。
在一些實施例中，模塑膠500的一部分被夾在其中一個導電孔110與半導體晶粒200之間。在一些實施例中，模塑膠500的一部分被夾在其中一個導電孔110與半導體晶粒400之間。
在一些實施例中，半導體晶粒400窄於半導體晶粒200，或者，半導體晶粒200和400不完全堆疊於彼此之上。因此，模塑膠500的一部分延伸在半導體晶粒200上。模塑膠500的一部分可以直接接觸到非活性表面200b。在一些實施例中，半導體晶粒400寬於半導體晶粒200，或者，半導體晶粒200和400彼此不完全重疊。因此，模塑膠500的一部分延伸在半導體晶粒400之下。模塑膠500的一部分可以直接接觸到粘接層300。
在一些實施例中，模塑膠500包括非導電材質，如環氧樹脂(epoxy)、樹脂(resin)、可模塑的聚合物(moldable polymer)，或其它合適的模塑材質。在一些實施例中，模塑膠500作為實質性的液體，然後通過化學反應固化。在另一些實施例中，模塑膠500是作為凝膠(gel)或可塑固體(malleable solid)的紫外線(ultraviolet，UV)或熱固化的聚合物，然後通過紫外線(UV)或熱固化工藝進行固化。可以利用模具(mold)來固化模塑膠500。
在一些實施例中，沉積後的模塑膠500覆蓋導電 孔110和導電結構430的頂部表面。此後，進行減薄工藝(thinning process)(如蝕刻工藝，碾磨工藝，磨削工藝或拋光工藝)，以使該沉積後的模塑膠500變薄。因此，減薄後的模塑膠500露出導電孔110和導電結構430的頂部表面。在一些實施例中，模塑膠500的頂部表面與導電孔110、導電結構430的頂部表面基本上共面。
如第1C圖所示，重佈線層(redistribution layer，RDL)結構600(也被稱之為扇出式結構)被形成在模塑膠500、導電孔100和半導體晶粒400上。在一些實施例中，重佈線層(RDL)結構600可以包括設置在金屬間介電(inter-metal dielectric，IMD)層中的一個或複數個導電跡線。該金屬間介電(IMD)層可以包括複數個子介電層(sub-dielectric layer)，該複數個子介電層依次堆疊在模塑膠500上。
舉例來說，複數個導電跡線620設置在第一子介電層610上，且被第二子介電層630覆蓋。複數個導電跡線620中的至少一個(如與半導體晶粒400相鄰的其中兩個導電跡線)電耦接于導電孔110以及半導體晶粒400。導電墊410通過導電結構430電連接於重佈線層(RDL)結構600的導電跡線620。在另一些實施例中，導電結構430未被形成，以及，導電墊410直接電連接於導電跡線620。應當注意的是，附圖中所示的重佈線層(RDL)結構600的導電跡線與子介電層的數量和安排僅為一種示例，而並不是本發明的限制。
在一些實施例中，金屬間介電(IMD)層可由有機材質(organic material)(如包括聚合物基體材質)或非有機 材質(non-organic material)(如包括氮化矽(SiNx)、氧化矽(SiOx)、石墨烯等等)組成。舉例來說，第一子介電層610和第二子介電層630由聚合物基體材質製成。在一些實施例中，金屬間介電(IMD)層為高k介電層(k為介電層的介電常數)。在另一些實施例中，金屬間介電(IMD)層可以由感光材質(包括幹膜抗蝕劑(dry film photoresist)或者包帶薄膜(taping film))製成。
如第1C圖所示，支撐基板(supporting substrate)700被提供在重佈線層(RDL)結構600上。支撐基板700是臨時性基板，以及，將在後續的步驟中被移除。在一些實施例中，支撐基板700包括玻璃、矽，或者其它合適的支撐材質。
本發明並不限於所描述的實施例。在另一些實施例中，重佈線層(RDL)結構600被預先形成在支撐基板700上。此後，具有重佈線層(RDL)結構600的支撐基板700被接合到模塑材質500、導電孔110和半導體晶粒400上。在另一些實施例中，重佈線層(RDL)結構600也可以不預先形成在支撐基板700上而直接被接合到模塑材質500、導電孔110和半導體晶粒400上。
如第1D圖所示，載體基板100被移除。在一些實施例中，如前所述，粘接層(未示出)可以被夾在半導體晶粒200和載體基板100之間。在移除載體基板100之後，該粘接層也被移除。舉例來說，進行減薄工藝(如磨削工藝)，以移除粘接層。在移除粘接層的期間，可以部分地移除導電孔110和模塑膠500。
此後，利用支撐基板700作為載體，重佈線層(RDL)結構800被形成。重佈線層(RDL)結構600和800位於模塑膠500的相對的兩側上。換言之，半導體晶粒200位於重佈線層(RDL)結構800與半導體晶粒400之間，而半導體晶粒400位於重佈線層(RDL)結構600與半導體晶粒200之間。重佈線層(RDL)結構600和800還位於貫穿模塑膠500的導電孔110的相對的兩側上。活性表面200a面向重佈線層(RDL)結構800，而活性表面400a面向重佈線層(RDL)結構600。
在一些實施例中，重佈線層(RDL)結構800可以包括一個或複數個導電跡線，該一個或複數個導電跡線設置在金屬間介電(IMD)層中。金屬間介電(IMD)層可以包括複數個子介電層，該複數個子介電層依次堆疊在模塑膠500上。
舉例來說，複數個第一導電跡線820位於第一子介電層810上，以及被第二子介電層830覆蓋。複數個第一導電跡線820中的至少一個電耦接于導電孔110和半導體晶粒200。導電墊210通過導電結構230電連接於重佈線層(RDL)結構800的第一導電跡線820。在另一些實施例中，導電結構230未被形成，以及，導電墊210直接電連接於第一導電跡線820。複數個第二導電跡線840位於第二子介電層830上，且被第三子介電層850覆蓋。應當注意的是，附圖中所示的重佈線層(RDL)結構800的導電跡線與子介電層的數量和安排僅為一種示例，而並不是本發明的限制。
導電跡線的導電墊部分從重佈線層(RDL)結構 800的頂部暴露出來。舉例來說，第二導電跡線840的導電墊部分從第三子介電層850的開孔暴露出來，以及連接至後續形成的導電組件。
本發明並不限於所描述的實施例。在另一些實施例中，重佈線層(RDL)結構800被預先形成在載體基板100上。其後，導電孔110、半導體晶粒200和400、模塑膠500以及重佈線層(RDL)結構600被形成在位於載體基板100上的重佈線層(RDL)結構800上。在該情形中，半導體晶粒200被接合至重佈線層(RDL)結構800，以及通過導電結構230電連接於重佈線層(RDL)結構800。在支撐基板700被提供在重佈線層(RDL)結構600上之後，移除載體基板100，以及，重佈線層(RDL)結構800露出。
如第1D圖所示，利用支撐基板700作為載體，一個或複數個導電組件900被形成在重佈線層(RDL)結構800上。導電組件900電連接於第二導電跡線840的導電墊部分。在一些實施例中，導電組件900是導電柱、導電凸塊(如微凸塊)、導電膠結構(conductive paste structure)，或者其它合適的導電組件。導電組件900可以包括銅、焊料，或者其它合適的導電材質。
在一些實施例中，其中一個導電組件900與第二導電跡線的其中一個焊片部分之間具有凸塊下金屬(under-bump metallurgy，UBM)層910。凸塊下金屬(UBM)層910可以包括一層或多層，如阻擋層(barrier layer)以及種晶層(seed layer)。此處作為一種示例描述了具有單個層的凸 塊下金屬(UBM)層910。
如第1E圖所示，支撐基板700被移除。因此，重佈線層(RDL)結構600露出。在一些實施例中，移除支撐基板700之後執行切單工藝(singulation process)。舉例來說，重佈線層(RDL)結構600和800，以及模塑膠500可以被切割。因此，複數個半導體封裝1000A被形成。在一些實施例中，半導體封裝1000A可以被直接接合至印刷電路板(printed circuit board，PCB)。在第1E圖所示的情形中，沒有半導體器件(如半導體晶粒或半導體封裝)被堆疊在半導體封裝1000A上。
如第1E圖所示，每一個半導體封裝1000A包括垂直堆疊的半導體晶粒200和400。特別地，半導體晶粒200的非活性表面200b面向半導體晶粒400的非活性表面400b。半導體晶粒200和400通過上面的(overlying)重佈線層(RDL)結構600、下面的(underlying)重佈線層(RDL)結構800以及其附近的導電孔110彼此電連接。因此，複數個半導體晶粒可以被集成在一個半導體封裝中，而無需增大半導體封裝的水準尺寸(面積)。此外，從半導體晶粒至印刷電路板(PCB)的導電路徑的長度短，以及具有大數量的導電路徑。因此，本發明提供了一種具有小尺寸和良好的電氣性能的多晶粒半導體封裝。
可以對本發明實施例做出許多變型和/或修改。例如，在一些變型實施例中，導電孔和模塑膠是可選的。例如，半導體封裝結構可以包括第一半導體晶粒(如200)、第二半 導體晶粒(如400)、第一重佈線層結構(如800)和第二重佈線層結構(如600)。第二半導體晶粒堆疊在第一半導體晶粒上，第一半導體晶粒的第一非活性表面面向第二半導體晶粒的第二非活性表面，以及，第一半導體晶粒的第一活性表面面向第一重佈線層結構，第二半導體晶粒的第二活性表面面向第二重佈線層結構。再例如，第一半導體晶粒可以包括第一導電墊，第一導電墊電連接於第一重佈線層結構；以及，第二半導體晶粒可以包括第二導電墊，第二導電墊可以電連接於第二重佈線層結構。此外，該半導體封裝結構還可以包括導電孔，從而，第一半導體晶粒可以通過第一導電墊、第一重佈線層結構、導電孔、第二重佈線層結構、第二導電墊電連接於第二半導體晶粒。
第2圖是根據本發明一些實施例的一種半導體封裝結構的剖視圖。在第2圖中，與第1A圖至第1E圖相同的組件採用與第1A圖至第1E圖相同的參考標號來標注，因此，為簡潔起見，此處不再描述這些相同的組件。
第2圖所示的半導體封裝1000B的結構與第1E圖所示的半導體封裝1000A的結構類似。兩者之間的差異是，半導體封裝1000B的重佈線層(RDL)結構600上具有阻焊層(solder mask layer)650。一個或複數個開孔660形成在阻焊層650中，以及延伸到重佈線層(RDL)結構600，以露出重佈線層(RDL)結構600中的導電跡線的導電墊部分。舉例來說，開孔660延伸到第二子介電層630中。因此，導電跡線620的導電墊部分從開孔660露出。在一些實施例中，第二子介電 層630可以直接作為阻焊層650使用，具體地，本發明實施例不做限制。
構造具有複數個開孔660的阻焊層650的目的是為了進一步地電連接。舉例來說，一晶粒/晶粒可以被接合到阻焊層650上，以及，通過開孔660電連接至重佈線層(RDL)結構600。或者，一封裝可以被堆疊在半導體封裝1000B上，以及通過開孔660電連接於重佈線層(RDL)結構600。舉例來說，該封裝可以是記憶體封裝(如DRAM封裝)或另一合適的封裝。因此，可以形成包括複數個半導體封裝的半導體封裝結構(assembly)。該半導體封裝組件的示例將在以後進行更加詳細的描述。
本發明並不限於前述實施例。兩個以上的半導體晶粒可被集成在一個半導體封裝中。第3圖和第4圖是根據本發明一些實施例的半導體封裝結構的剖視圖。在第3圖和第4圖中，與第1A圖至第1E圖以及第2圖相同的組件採用與第1A圖至第1E圖以及第2圖相同的參考標號來標注，因此，為簡潔起見，此處不再描述這些相同的組件。
第3圖所示的半導體封裝1000C的結構與第2圖所示的半導體封裝1000B的結構類似。兩者之間的差異是，半導體封裝1000C中具有複數個半導體晶粒200和複數個半導體晶粒400。
在一些實施例中，如第3圖所示，複數個半導體晶粒400(如左部所示的兩個半導體晶粒400)垂直堆疊在一個半導體晶粒200上。在一些實施例中，一個半導體晶粒400 (如右部所示的一個半導體晶粒400)垂直堆疊在複數個半導體晶粒200上。在一些實施例中，複數個半導體晶粒400中的其中一個與複數個半導體晶粒200中的其中一個彼此未完全地垂直重疊。在一些實施例中，複數個半導體晶粒200具有不同的尺寸。在另一些實施例中，複數個半導體晶粒200具有相同的尺寸。在一些實施例中，複數個半導體晶粒400具有不同的尺寸。在另一些實施例中，複數個半導體晶粒400具有相同的尺寸。在一些實施例中，如第3圖所示，模塑膠500的一些部分延伸在半導體晶粒200與半導體晶粒200之間，以及，半導體晶粒400與半導體晶粒400之間。
第4圖所示的半導體封裝1000D的結構與半導體封裝1000B和1000C的結構類似。它們之間的差異是，半導體封裝1000D中具有垂直堆疊在複數個半導體晶粒200上的複數個半導體晶粒400。複數個半導體晶粒200可以具有不同的尺寸或相同的尺寸。複數個半導體晶粒400可以具有不同的尺寸或相同的尺寸。如第4圖所示，在一些實施例中，模塑膠500的一些部分延伸在半導體晶粒200與半導體晶粒200之間，以及半導體晶粒400與半導體晶粒400之間。
儘管半導體封裝1000B、1000C或1000D在重佈線層(RDL)結構600上包括具有開孔660的阻焊層650，但本發明並不限於此。在一些實施例中，部分地露出重佈線層(RDL)結構600的開孔660未被形成。在一些實施例中，未在重佈線層(RDL)結構600上形成阻焊層650。在這些情形中，沒有半導體器件(如半導體晶粒或半導體封裝)堆疊在半 導體封裝1000B、1000C或1000D上。
根據本發明的一些實施例，半導體封裝結構和用於形成該半導體封裝結構的方法提供了多種優勢。垂直堆疊的複數個半導體晶粒被集成在半導體封裝1000A、1000B、1000C或1000D中。與具有兩個並排設置的晶粒的雙晶粒扇出式封裝相比，半導體封裝1000A、1000B、1000C或1000D的水準尺寸(面積)非常小。還可以避免翹曲變形的問題。與具有垂直堆疊封裝的三維封裝體疊層(3D PoP)結構相比，半導體封裝1000A、1000B、1000C或1000D的垂直尺寸(厚度)非常小。因此，具有複數個半導體晶粒的半導體封裝的尺寸被大大地減少。此外，與矽通孔(TSV)技術相比，半導體封裝1000A、1000B、1000C或1000D的構造簡單，以及，必要的製造成本和時間要少得多。
如以上所描述的，各種各樣的半導體封裝還可以被堆疊在半導體封裝1000B、1000C或1000D上。舉例來說，如第5圖所示，半導體封裝2000垂直堆疊在半導體封裝1000B上。第5圖係根據本發明一些實施例的一種半導體封裝結構的剖視圖。在第5圖中，與第1A圖至第1E圖以及第2圖相同的組件採用相同的參考標號，因此，為簡潔起見，此處不再描述這些相同的組件。應當注意的是，第5圖所示的半導體封裝2000的結構僅是一種示例，以及，本發明並不限於此。
半導體封裝2000與半導體封裝1000B被安裝在一起，以及，通過導電組件2100彼此電連接。導電組件2100位於開孔660中，以及從阻焊層650突出。在一些實施例中，導 電組件2100是導電凸塊(如微凸塊)、導電柱、導電膠結構或其它合適的導電組件。導電組件2100可以包括銅、焊料或者其它合適的導電材質。在另一些實施例中，導電組件2100被底部填充材質圍繞。
在一些實施例中，半導體封裝2000包括基座(base)2200、至少一個半導體晶粒(如兩個垂直堆疊的半導體晶粒2300和2400)、接合引線(bonding wire)2500以及模塑膠2600。在一些實施例中，基座2200為基板(substrate)，以及，可以由聚丙烯(propathene，PP)或其它合適的材質組成。基座2200通過導電組件2100電連接至重佈線層(RDL)結構600。
半導體晶粒2300通過粘接層(如膠水(glue)或其它合適的粘附材質)附著於基座2200上。半導體晶粒2300通過其導電墊2310以及接合引線2500電連接於基座2200。在一些實施例中，半導體晶粒2300為記憶體晶粒或另一合適的半導體晶粒。半導體晶粒2400通過粘接層(如膠水或另一合適的粘附材質)附著於半導體晶粒2300上。半導體晶粒2400通過其導電墊2410以及接合引線2500電連接於基座2200。在一些實施例中，半導體晶粒2400是記憶體晶粒或另一合適的半導體晶粒。在一些實施例中，半導體晶粒2300和2400是DRAM晶粒。在一些實施例中，導電墊2300和/或2400可以通過電鍍工藝、接合工藝或其它適用的工藝形成。
模塑膠2600覆蓋基座2200以及圍繞半導體晶粒2300和2400。接合引線2500被嵌入在模塑膠2600中。在一 些實施例中，模塑膠2600由非導電材質(如環氧樹脂、樹脂、可模塑的聚合物，或者其它合適的模塑材質)組成。
如第5圖中所示，小尺寸的半導體封裝1000B和半導體封裝2000被垂直地堆疊以及被集成在半導體封裝結構/組件中。因此，本發明提供了一種具有兩個以上半導體晶粒的封裝體疊層(PoP)結構，以及，其尺寸被大大減少。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本發明所屬技術領域中普通技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
1000A‧‧‧半導體封裝
600、800‧‧‧重佈線層結構
610‧‧‧第一子介電層
620‧‧‧導電跡線
630‧‧‧第二子介電層
110‧‧‧導電孔
400a、200a‧‧‧活性表面
400b、200b‧‧‧非活性表面
400、200‧‧‧半導體晶粒
410、210‧‧‧導電墊
420、220‧‧‧鈍化層
430、230‧‧‧導電結構
440、240‧‧‧底部填充層
500‧‧‧模塑膠
300‧‧‧粘接層
910‧‧‧凸塊下金屬層
900‧‧‧導電組件

Claims (23)

  1. 一種半導體封裝結構，包括：一第一半導體晶粒，具有第一活性表面和第一非活性表面；一第二半導體晶粒，具有第二活性表面和第二非活性表面，其中，該第二半導體晶粒堆疊在該第一半導體晶粒上，以及，該第一非活性表面面向該第二非活性表面；一第一重佈線層結構，其中，該第一活性表面面向該第一重佈線層結構；以及一第二重佈線層結構，其中，該第二活性表面面向該第二重佈線層結構。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中，該半導體封裝結構還包括：一粘接層，直接接觸該第一非活性表面和該第二非活性表面。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中，該半導體封裝結構還包括：一導電孔，設置在該第一半導體晶粒和該第二半導體晶粒的周圍。
  4. 如申請專利範圍第3項所述之半導體封裝結構，其中，該半導體封裝結構還包括：一模塑膠，圍繞該導電孔、該第一半導體晶粒和該第二半導體晶粒。
  5. 如申請專利範圍第4項所述之半導體封裝結構，其中，該第一重佈線層結構和該第二重佈線層結構位於該模塑膠的 相對的兩側上。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中，該第一半導體晶粒的側壁與該第二半導體晶粒的側壁基本上共面。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中，該半導體封裝結構包括複數個第二半導體晶粒，該複數個第二半導體晶粒堆疊在該第一半導體晶粒上。
  8. 如申請專利範圍第1項所述之半導體封裝結構，其中，該半導體晶粒封裝結構包括複數個第一半導體晶粒和複數個第二半導體晶粒，其中，該複數個第二半導體晶粒堆疊在該複數個第一半導體晶粒上。
  9. 如申請專利範圍第8項所述之半導體封裝結構，其中，該半導體晶粒封裝結構還包括：一模塑膠，位於該複數個第二半導體晶粒的兩者之間和/或該複數個第一半導體晶粒的兩者之間。
  10. 一種半導體封裝結構，其中，包括：一第一半導體晶粒，包括一第一導電墊，其中，該第一半導體晶粒具有第一表面和與該第一表面相對的第二表面，該第一導電墊位於該第一表面上；一第二半導體晶粒，包括一第二導電墊，其中，該第二半導體晶粒垂直地堆疊在該第一半導體晶粒上，該第二半導體晶粒具有第三表面和與該第三表面相對的第四表面，該第一導電墊位於該第三表面上，該第二表面面向該第四表面；以及 一模塑膠，圍繞該第一半導體晶粒和該第二半導體晶粒。
  11. 如申請專利範圍第10項所述之半導體封裝結構，其中，該半導體封裝結構還包括：貫穿該模塑膠的一導電孔，其中，該第一導電墊通過該導電孔電連接於該第二導電墊。
  12. 如申請專利範圍第11項所述之半導體封裝結構，其中，該模塑膠的一部分被夾在該導電孔和該第一半導體晶粒之間，以及該導電孔與該第二半導體晶粒之間。
  13. 如申請專利範圍第11項所述之半導體封裝結構，其中，該導電孔厚於該第一半導體晶粒和該第二半導體晶粒之一者或兩者。
  14. 如申請專利範圍第10項所述之半導體封裝結構，其中，該半導體封裝結構還包括：一粘接層，位於該第一半導體晶粒和該第二半導體晶粒之間，以及被該模塑膠圍繞。
  15. 如申請專利範圍第10項所述之半導體封裝結構，其中，該半導體封裝結構還包括：一第一重佈線層結構和一第二重佈線層結構，位於該模塑膠的相對的兩側上；其中，該第一導電墊面向該第一重佈線層結構，以及，該第二導電墊面向該第二重佈線層結構。
  16. 如申請專利範圍第15項所述之半導體封裝結構，其中，該半導體封裝結構還包括：一導電組件，連接於該第一重佈線層結構。
  17. 如申請專利範圍第15或16項所述之半導體封裝結構，其 中，該半導體封裝結構還包括：一阻焊層，位於該第二重佈線層結構上，其中，該阻焊層包括一開孔，該開孔使該第二重佈線層結構的一部分露出。
  18. 一種形成半導體封裝結構的方法，其中，包括：提供一第一半導體晶粒；將一第二半導體晶粒堆疊在該第一半導體晶粒上；其中，該第一半導體晶粒的第一非活性表面面向該第二半導體晶粒的第二非活性表面；以及形成圍繞該第一半導體晶粒和該第二半導體晶粒的一模塑膠。
  19. 如申請專利範圍第18項所述之形成半導體封裝結構的方法，其中，該方法還包括：形成一第一重佈線層結構，其中，該第二非活性表面面向該第一重佈線層結構；以及形成一第二重佈線層結構，其中，該第一非活性表面面向該第二重佈線層結構；該第一重佈線層結構和該第二重佈線層結構位於該模塑膠的相對的兩側上。
  20. 如申請專利範圍第19項所述之形成半導體封裝結構的方法，其中，該方法還包括：形成一導電孔，其中，該導電孔設置在該第一半導體晶粒和該第二半導體晶粒的周圍。
  21. 如申請專利範圍第20項所述之形成半導體封裝結構的方法，其中，該第一半導體晶粒被提供在一載體基板上，以 及，該導電孔被形成在該載體基板上；以及，該方法還包括：在形成該第二重佈線層結構之後移除該載體基板。
  22. 如申請專利範圍第21項所述之形成半導體封裝結構的方法，其中，該方法還包括：在移除該載體基板之前，提供一支撐基板到該第二重佈線層結構上；以及在形成該第一重佈線層結構之後，移除該支撐基板。
  23. 如申請專利範圍第18項所述之形成半導體封裝結構的方法，其中，該第二非活性表面通過一粘接層附著於該第一非活性表面。
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