CN103296014A - 扇出晶圆级半导体芯片三维堆叠封装结构及工艺 - Google Patents

扇出晶圆级半导体芯片三维堆叠封装结构及工艺 Download PDF

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CN103296014A
CN103296014A CN2012100484299A CN201210048429A CN103296014A CN 103296014 A CN103296014 A CN 103296014A CN 2012100484299 A CN2012100484299 A CN 2012100484299A CN 201210048429 A CN201210048429 A CN 201210048429A CN 103296014 A CN103296014 A CN 103296014A
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semiconductor chip
fan
wafer level
out wafer
moulding compound
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刘胜
陈照辉
陈润
汪学方
刘孝刚
李超
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刘胜
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Priority to CN2012100484299A priority Critical patent/CN103296014A/zh
Priority to PCT/CN2012/000611 priority patent/WO2013127035A1/zh
Publication of CN103296014A publication Critical patent/CN103296014A/zh
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Abstract

一种扇出晶圆级半导体芯片三维堆叠封装结构，包括数个扇出晶圆级半导体芯片封装体，及封装体之间的凸点阵列及高分子保护材料，其特征在于所述的扇出晶圆级半导体芯片封装体的第一半导体芯片背面及第二半导体芯片背面由贴片材料键合一起，通过模塑料密封成一个整体，在封装体的模塑料上设有垂直通孔并填充导电材料，在模塑料密封体的上下表面分别制作再分布层，在再分布层上设有凸点，通过再分布层的导电金属层连接半导体芯片、通孔中的导电材料以及凸点，实现各半导体芯片之间的电互联，通过堆叠工艺将数个扇出晶圆级半导体芯片封装体进行堆叠。本发明的优点是能有效提高三维封装的密度，减小封装体的厚度，且工艺流程简单，成本低，可靠性高。

Description

扇出晶圆级半导体芯片三维堆叠封装结构及工艺
技术领域
本发明涉及一种半导体封装技术，特别涉及一种扇出晶圆级半导体芯片三维堆叠封装结构及工艺。
背景技术
由于人们对于电子封装产品高密度、多功能、小型化、轻型化的需求日益迫切，三维系统级封装顺应了这种潮流，目前、三维电子封装技术取得了突飞猛进的发展。利用硅通孔(Through Silicon Via)技术实现半导体芯片的三维堆叠，实现了在三维方向堆叠的密度最大，外形尺寸最小，并且大大改善芯片速度和低功耗的性能，但也存在着工艺成本相对较高的缺点。
晶圆级封装(Wafer Level Packaging；WLP)是在整片晶圆上完成，直接在晶圆上进行封装测试，完成之后才切割制成单颗半导体芯片。传统的WLP封装多采用扇入(Fan in)型态，但是随I/O数目增加，对球距要求趋于严格，因此变化衍生出扇出(Fan out)、扇入(Fan in)及Fan out相互运用等各式新型，其概念已跳脱传统WLP封装。
发明内容
本发明的目的是针对已有技术中存在的缺陷，提供一种扇出晶圆级半导体芯片三维堆叠封装结构。本发明包含数个扇出晶圆级半导体芯片封装体，多个封装体之间的凸点阵列及高分子保护材料，每个扇出晶圆级半导体芯片封装体包括：数个半导体芯片、载片、贴片材料、模塑料、数个再分布层、通孔、填充导电材料、凸点，其特征在于所述的扇出晶圆级半导体芯片封装体的第一半导体芯片背面及第二半导体芯片背面通过键合工艺经由贴片材料键合一起，并通过模塑料密封成一个整体，第一半导体芯片正面的有源面及第二半导体芯片正面的有源面暴露在模塑料之外，并与模塑料的上下表面在同一平面上，在半导体芯片区域之外的模塑料上制作垂直通孔，并在通孔内填充导电材料，在模塑料密封体的上下表面分别制作第一再分布层与第二再分布层，分别在第一再分布层与第二再分布层上制作凸点，通过再分布层的导电金属层连接第一半导体芯片、第二半导体芯片、通孔中的导电材料以及凸点，实现第一半导体芯片与第二半导体芯片之间的电互联，通过堆叠工艺将多个扇出晶圆级半导体芯片封装体进行堆叠，在多个扇出晶圆级半导体芯片封装体之间填充高分子胶，保护凸点阵列，通过凸点阵列及通孔内导电材料实现不同扇出晶圆级半导体芯片封装体之间的电互连。
所述第一半导体芯片及第二半导体芯片，两个半导体芯片的尺寸相同或不同，第一半导体芯片背面及第二半导体芯片背面通过键合工艺经由贴片材料键合在一起，或第一半导体芯片背面及第二半导体芯片背面分别通过键合工艺经由贴片材料键合到载片上，载片的尺寸比半导体芯片大或比半导体芯片小，载片的材料为硅材料或金属，载片上设有用于增强固定作用的固定通孔，其形状为方形或圆形，贴片材料为有铅焊料或无铅焊料、金锡焊料或金硅焊料或高分子贴片材料。
所述数个扇出晶圆级半导体芯片封装体中的第二半导体芯片及第三半导体芯片的尺寸比第一半导体芯片小，通过键合工艺将第二半导体芯片及第三半导体芯片的背面与第一半导体芯片背面键合一起。
所述第一半导体芯片及第二半导体芯片经键合或不经键合，直接通过夹具的辅助由模塑料密封成一个整体，第一半导体芯片及第二半导体芯片的有源面露出模塑料密封体，且与模塑料密封体上下表面在同一个平面上。
所述模塑料密封体上制作有垂直通孔，通孔的形状为圆孔或方孔，其直径在5um～300um，深宽比在1∶1～1∶15之间，通孔的间距在30um～500um，通孔的排布为单圈分布或多圈分布。
所述通孔内通过沉积工艺或电镀工艺填充有导电填充材料，其材料为导电胶或有铅焊料或无铅焊料或金属铜或铝或钨。
所述第一再分布层与第二再分布层分别经光刻或刻蚀或沉积或溅射或电镀工艺制作在第一半导体芯片及第二半导体芯片的模塑料密封体的正反表面上，再分布层包含了绝缘层，金属导电层，绝缘层的材料为高分子材料，金属导电层的材料为：金或铝或镍或铜或钛，第一再分布层与第二再分布层为两层结构或多层结构。
所述凸点阵列经植球或丝网印刷工艺制作在模塑料密封体上下表面的第一再分布层与第二再分布层上，其材料为有铅焊料凸点或无铅焊料凸点或金凸点或铜柱或焊料凸点。
扇出晶圆级半导体芯片三维堆叠封装结构的工艺，依次包含以下步骤：
A.利用键合工艺将第一半导体芯片及第二半导体芯片背对背的经由贴片材料键合成一体；
B.利用注塑工艺将第一半导体芯片及第二半导体芯片键合体经由模塑料密封成一个整体，露出第一半导体芯片及第二半导体芯片有源面，且与模塑料密封体上下表面在同一个平面上；
C.利用机械钻孔，激光打孔在模塑料密封体上制作垂直通孔，或采用模具直接在注塑工艺中形成通孔；
D.利用沉积、电镀等工艺，在模塑料密封的通孔内填充导电填充材料；
E.利用光刻、刻蚀、沉积、溅射、电镀等工艺在包含第一半导体芯片及第二半导体芯片的模塑料密封体的正反表面上制作第一再分布层与第二再分布层；
F.利用植球、丝网印刷、沉积、键合等工艺在模塑料密封体上下表面的第一再分布层与第二再分布层上制作凸点阵列；
G.利用切割工艺将完成再分布层及凸点制作的封装体切割分离成单个的扇出晶圆级半导体芯片封装体；
H.利用回流、键合工艺将两个或多个扇出晶圆级半导体芯片封装体进行堆叠，并填充高分子保护材料，或再次利用注塑工艺的模塑料进行密封。
本发明的优点是能有效提高三维封装的密度，减小封装体的厚度，且工艺流程简单，成本低，可靠性高。
附图说明
图1扇出晶圆级半导体芯片三维堆叠封装结构示意图；
图2实施例一的结构示意图；
图3实施例一第一半导体芯片与第二半导体芯片背对背键合示意图；
图4实施例一注塑工艺实现第一半导体芯片与第二半导体芯片密封示意图；
图5实施例一注塑工艺完成后第一半导体芯片与第二半导体芯片塑封体结构示意图；
图6实施例一在塑封体上制作垂直通孔示意图；
图7实施例一在垂直通孔内填充导电材料示意图；
图8实施例一在塑封体正反面制作第一再分布层与第二再分布层示意图；
图9实施例一切割分离塑封体成扇出晶圆级半导体芯片封装体示意图；
图10实施例二利用载片进行第一半导体芯片与第二半导体芯片背对背键合示意图；
图11、图11a实施例二带有固定通孔结构的载片结构示意图和A-A剖视图；
图12实施例二利用尺寸小于半导体芯片的载片进行第一半导体芯片与第二半导体芯片背对背键合示意图；
图13实施例三第二半导体芯片尺寸比第一半导体芯片小的扇出晶圆级半导体芯片封装体示意图；
图14实施例四通过夹具辅助直接将第一半导体芯片与第二半导体芯片背对背塑封结构示意图；
图15实施例五第一再分布层与第一再分布层有两层导电金属层结构示意图；
图16实施例六具有多圈垂直通孔分布的扇出晶圆级半导体芯片封装体结构示意图；
图17实施例七具有三个半导体芯片的扇出晶圆级半导体芯片封装体结构示意图；
图18实施例八利用模塑料二次密封扇出晶圆级半导体芯片三维堆叠封装结构示意图；
图19实施例九第一半导体芯片与第二半导体芯片为多层芯片堆叠体的扇出晶圆级半导体芯片三维堆叠封装结构示意图。
图中：10扇出晶圆级半导体芯片封装体、20扇出晶圆级半导体芯片封装体、30扇出晶圆级半导体芯片封装体、10A第一再分布层、10B第二再分布层、101第一半导体芯片、101-1第一半导体芯片堆叠体、101-2第一半导体芯片堆叠体、102第二半导体芯片、102-1第二半导体芯片堆叠体、102-2第二半导体芯片堆叠体、103贴片材料、104载片、104a载片上贴片区域、104b载片上的固定通孔、105模塑料、106a垂直通孔、106通孔内导电填充材料、106b通孔内导电填充材料、107绝缘胶、108金属导电层、109凸点、110凸点、111高分子填充材料、112凸点、113第三半导体芯片、114模塑料、115高分子填充材料、116，导电填充材料、120注塑模具。
具体实施方式
下面结合附图进一步说明本发明的实施例：
实施例一
本发明提供了一种扇出晶圆级半导体芯片三维堆叠封装结构，包括三个扇出晶圆级半导体芯片封装体10、20、30，由于封装体10、20、30结构相同，以封装体10为图解，封装体20、30以此类推，各封装体之间设有凸点阵列110及高分子保护材料111。每个扇出晶圆级半导体芯片封装体10、20、30包括：第一半导体芯片101、第二半导体芯片102、贴片材料103、模塑料105、第一再分布层10A、第二再分布层10B、垂直通孔106a、通孔内填充导电材料106、凸点109。所述的扇出晶圆级半导体芯片封装体10的第一半导体芯片101背面及第二半导体芯片102背面通过键合工艺经由贴片材料103键合，并通过模塑料105密封成一个整体，并确保第一半导体芯片正面101a及第二半导体芯片正面102a暴露在模塑料105之外。在半导体芯片区域之外的模塑料105上制作垂直通孔106a，并在通孔内填充导电材料106。在模塑料密封体的上下表面分别制作第一再分布层10A、第二再分布层10B，分别在再分布层上制作凸点109、112，通过再分布层的导电金属层108连接第一半导体芯片101、第二半导体芯片102、通孔106a中的导电材料106以及凸点109、112，实现第一半导体芯片101与第二半导体芯片102之间的电互联，如图2所示。通过键合工艺将三个扇出晶圆级半导体芯片封装体10、20、30进行堆叠，在三个扇出晶圆级半导体芯片封装体之间填充高分子111胶保护凸点阵列110，通过凸点阵列110及通孔导电材料106实现不同扇出晶圆级半导体芯片封装体10、20、30之间的电互连，如图1所示。
扇出晶圆级半导体芯片封装体包含两个半导体芯片：第一半导体芯片101及第二半导体芯片102，第一半导体芯片101背面及第二半导体芯片102背面通过键合工艺经由贴片材料103键合，将多组芯片键合体并按一定的间距排列在注塑模具120上，如图3所示。贴片材料103可以为高分子贴片材料，有铅焊料或无铅焊料或金锡焊料或金硅焊料。扇出晶圆级半导体芯片封装体的第一半导体芯片102及第二半导体芯片103键合体通过注塑工艺经由模塑料106密封成一个整体，如图4所示。第一半导体芯片及第二半导体芯片的有源面101a、102a露出模塑料105密封体，且与模塑料105密封体上下表面在同一个平面上，如图5所示。
扇出晶圆级半导体芯片封装体的模塑料105密封体上制作有垂直通孔106a，其制作工艺可采用机械钻孔，激光打孔，或采用模具直接在注塑工艺中形成通孔106a。通孔的形状可以为圆孔，也可以为方孔，其直径在50um～300um，深宽比在1∶1～1∶15之间。通孔的间距在30um～500um，如图6所示。
模塑料密封的垂直通孔106a内填充有导电填充材料106，可采用沉积工艺或电镀工艺，其材料可以为导电胶，有铅焊料、无铅焊料、金属铜、铝、钨等，导电填充材料的填充工艺包括沉积、电镀等工艺，如图7所示。
第一再分布层10A、第二再分布层10B分别制作在第一半导体芯片101及第二半导体芯片102的模塑料密封体的正反表面上，第一再分布层10A、第二再分布层10B包含了绝缘层107，金属导电层108。绝缘层107的材料可以为高分子材料，金属导电层108的材料包括：金、铝、镍、铜、钛等。再分布层的制作工艺包括光刻、刻蚀、沉积、溅射、电镀等工艺，如图8所示。
凸点阵列109制作在模塑料密封体上下表面的第一再分布层10A、第二再分布层10B上，其制作工艺包括植球、丝网印刷、沉积、键合等。其材料可以为有铅焊料凸点或无铅焊料凸点或金凸点或铜柱或焊料凸点等，如图8所示。
利用切割工艺将完成再分布层及凸点制作的封装体切割分离成单个的扇出晶圆级半导体芯片封装体10、20、30，如图9所示。
扇出晶圆级半导体芯片三维堆叠封装结构包括了两个或多个扇出晶圆级半导体芯片封装体10、20、30，其间用凸点阵列110实现互连，并填充高分子保护材料111，其材料可以为下底填充料，如图1所示。
扇出晶圆级半导体芯片三维堆叠封装结构的工艺，依次包含以下步骤：
A.利用键合工艺将第一半导体芯片101及第二半导体芯片102背对背的经由贴片材料103键合成一体；
B.利用注塑工艺将第一半导体芯片101及第二半导体芯片102键合体经由模塑料105密封成一个整体，露出第一半导体芯片及第二半导体芯片有源面101a、102a；
C.利用机械钻孔，激光打孔在模塑料105密封体上制作垂直通孔106a，或采用模具直接在注塑工艺中形成垂直通孔106a；
D.利用沉积或电镀工艺，在模塑料105密封体的通孔106a内填充导电填充材料106；
E.利用光刻、沉积、溅射、电镀等工艺在包含第一半导体芯片101及第二半导体芯片102的模塑料密封体的正反表面上制作第一再分布层10A、第二再分布层10B；
F.利用植球、丝网印刷、沉积、键合等工艺在模塑料105密封体上下表面的第一再分布层10A、第二再分布层10B上制作凸点阵列109、110；
G.利用切割工艺将完成再分布层及凸点制作的封装体切割分离成单个的扇出晶圆级半导体芯片封装体10、20、30；
H.利用回流、键合工艺将两个或多个扇出晶圆级半导体芯片封装体10、20、30进行堆叠，并填充高分子保护材料111。
实施例二
实施例二与实施例一相同，所不同的是本实施例用载片104进行第一半导体芯片101与第二半导体芯片102背对背键合，载片的材料可以为硅或金属，载片104的尺寸大于一半导体芯片101与第二半导体芯片102的尺寸，利用载片加强模塑料105密封体的固定，如图10所示。可以在载片104芯片贴片区域104a以外的区域制作固定通孔104b，其形状可以为方形或圆形，如图11所示。载片104的尺寸也可以小于第一半导体芯片101与第二半导体芯片102的尺寸，利用半导体芯片的背部空出的面积加强模塑料105密封体的固定，如图12所示。
实施例三
实施例三与实施例一相同，所不同的是本实施例第二半导体芯片102尺寸比第一半导体芯片101小；第二半导体芯片102背面键合到第一半导体芯片101与背面上，利用第一半导体芯片101背部多出的面积加强模塑料105密封体的固定，如图13所示。
实施例四
实施例四与实施例一相同，所不同的是本实施例扇出晶圆级半导体芯片封装体的第一半导体芯片101及第二半导体芯片102不需要经过键合，利用夹具的辅助直接将第一半导体芯片101与第二半导体芯片102背对背塑封成一个整体，第一半导体芯片101及第二半导体芯片102的有源面露101a、102a出模塑料密封体，且与模塑料105密封体上下表面在同一个平面上，如图14所示。
实施例五
实施例五与实施例一相同，所不同的是本实施例的第一再分布层10A与第二再分布层10B具有多层导电金属层108结构，再分布层的制作工艺包括光刻、刻蚀、沉积、溅射、电镀等工艺，如图15所示。
实施例六
实施例六与实施例一相同，所不同的是本实施例模塑料105塑封体中制作有具有多圈分布的通孔结构106及106a，以增加互连的I/O数目，如图16所示。
实施例七
实施例七与实施例一相同，所不同的是本实施例具有三个以上半导体芯片，包括第一半导体芯片101、第二半导体芯片102，第三半导体芯片113，第二半导体芯片102及第三半导体芯片113的尺寸比第一半导体芯片101小，通过键合工艺将第二半导体芯片102及第三半导体芯片113的背面与第一半导体芯片背面键合一起，如图17所示；
实施例八
实施例八与实施例一相同，所不同的是本实施例也可以将整个堆叠封装体通过模塑料105再次密封，以起到保护扇出晶圆级半导体芯片封装体10、20、30层间凸点阵列110的作用，如图18所示。
实施例九
实施例九与实施例一相同，所不同的是本实施例的第一半导体芯片101与第二半导体芯片102为利用通孔硅技术完成堆叠的多层芯片堆叠体。第一半导体芯片101包括多个半导体堆叠芯片101-1、101-2，第二半导体芯片102包括多个半导体堆叠芯片102-1、102-2，半导体堆叠芯片101-1与101-2之间，102-1与102-2之间通过通孔导电填充材料116互连，并且填充保护高分子材料115，通过这种方式提高封装的密度，如图19所示。

Claims (9)

1.一种扇出晶圆级半导体芯片三维堆叠封装结构，包括数个扇出晶圆级半导体芯片封装体，多个封装体之间的凸点阵列及高分子保护材料，每个扇出晶圆级半导体芯片封装体包括数个半导体芯片、载片、贴片材料、模塑料、数个再分布层、通孔、填充导电材料、凸点，其特征在于所述的扇出晶圆级半导体芯片封装体的第一半导体芯片背面及第二半导体芯片背面通过键合工艺经由贴片材料键合一起，并通过模塑料密封成一个整体，第一半导体芯片正面的有源面及第二半导体芯片正面的有源面暴露在模塑料之外，并与模塑料的上下表面在同一平面上，在半导体芯片区域之外的模塑料上制作垂直通孔，并在通孔内填充导电材料，在模塑料密封体的上下表面分别制作第一再分布层与第二再分布层，分别在第一再分布层与第二再分布层上制作凸点，通过再分布层的导电金属层连接第一半导体芯片、第二半导体芯片、通孔中的导电材料以及凸点，实现第一半导体芯片与第二半导体芯片之间的电互联，通过堆叠工艺将多个扇出晶圆级半导体芯片封装体进行堆叠，在多个扇出晶圆级半导体芯片封装体之间填充高分子胶，保护凸点阵列，通过凸点阵列及通孔内导电材料实现不同扇出晶圆级半导体芯片封装体之间的电互连。
2.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述第一半导体芯片及第二半导体芯片，两个半导体芯片的尺寸相同或不同，第一半导体芯片背面及第二半导体芯片背面通过键合工艺经由贴片材料键合在一起，或第一半导体芯片背面及第二半导体芯片背面分别通过键合工艺经由贴片材料键合到载片上，载片的尺寸比半导体芯片大或比半导体芯片小，载片的材料为硅材料或金属，载片上设有固定通孔，其形状为方形或圆形，贴片材料为有铅焊料或无铅焊料或金锡焊料或金硅焊料或高分子贴片材料。
3.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述数个扇出晶圆级半导体芯片封装体中的第二半导体芯片及第三半导体芯片的尺寸比第一半导体芯片小，通过键合工艺将第二半导体芯片及第三半导体芯片的背面与第一半导体芯片背面键合一起。
4.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述第一半导体芯片及第二半导体芯片经键合，或不经键合直接通过夹具的辅助由模塑料密封成一个整体，第一半导体芯片及第二半导体芯片的有源面露出模塑料密封体，且与模塑料密封体上下表面在同一个平面上。
5.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述模塑料密封体上制作有垂直通孔，通孔的形状为圆孔或方孔，其直径在5um～300um，深宽比在1∶1～1∶15之间，通孔的间距在30um～500um，通孔的排布为单圈分布或多圈分布。
6.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述通孔内通过沉积工艺或电镀工艺填充有导电填充材料，其材料为导电胶或有铅焊料或无铅焊料或金属铜或铝或钨。
7.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述第一再分布层与第二再分布层分别经光刻或刻蚀或沉积或溅射或电镀工艺制作在第一半导体芯片及第二半导体芯片的模塑料密封体的正反表面上，再分布层包含了绝缘层，金属导电层，绝缘层的材料为高分子材料，金属导电层的材料为：金或铝或镍或铜或钛，第一再分布层与第二再分布层为两层结构或多层结构。
8.根据权利要求1所述的扇出晶圆级半导体芯片三维堆叠封装结构，其特征在于所述凸点阵列经植球或丝网印刷工艺制作在模塑料密封体上下表面的第一再分布层与第二再分布层上，其材料为有铅焊料凸点或无铅焊料凸点或金凸点或铜柱或焊料凸点。
9.一种扇出晶圆级半导体芯片三维堆叠封装结构的工艺，其特征在于依次包含以下步骤：
A.利用键合工艺将第一半导体芯片背面及第二半导体芯片背面经由贴片材料键合成一体；
B.利用注塑工艺将第一半导体芯片及第二半导体芯片键合体经由模塑料密封成一个整体，露出第一半导体芯片及第二半导体芯片有源面，且与模塑料密封体上下表面在同一个平面上；
C.利用机械钻孔，激光打孔在模塑料密封体上制作垂直通孔，或采用模具直接在注塑工艺中形成通孔；
D.利用沉积、电镀等工艺，在模塑料密封的通孔内填充导电填充材料；
E.利用光刻、刻蚀、沉积、溅射、电镀等工艺在包含第一半导体芯片及第二半导体芯片的模塑料密封体的正反表面上制作第一再分布层与第二再分布层；
F.利用植球、丝网印刷、沉积、键合等工艺在模塑料密封体上下表面的第一再分布层与第二再分布层上制作凸点阵列；
G.利用切割工艺将完成再分布层及凸点制作的封装体切割分离成单个的扇出晶圆级半导体芯片封装体；
H.利用回流、键合工艺将数个扇出晶圆级半导体芯片封装体进行堆叠，并填充高分子保护材料或再次利用注塑工艺的模塑料进行密封。
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