TWI758150B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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TWI758150B
TWI758150B TW110112115A TW110112115A TWI758150B TW I758150 B TWI758150 B TW I758150B TW 110112115 A TW110112115 A TW 110112115A TW 110112115 A TW110112115 A TW 110112115A TW I758150 B TWI758150 B TW I758150B
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Taiwan
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semiconductor component
conductive
semiconductor
redistribution layer
package structure
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TW110112115A
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English (en)
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TW202139397A (zh
Inventor
蔡宜霖
許文松
彭逸軒
林儀柔
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聯發科技股份有限公司
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Priority claimed from US17/208,198 external-priority patent/US11830851B2/en
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW202139397A publication Critical patent/TW202139397A/zh
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Abstract

本發明公開一種半導體封裝結構，包括：基板；重分佈層，在該基板的上方；第一半導體部件，在該重分佈層的上方；導電柱，與該第一半導體部件相鄰，其中該第一半導體部件和該導電柱由該模製材料圍繞；以及第二半導體部件，在該模製材料上，其中該第二半導體部件透過該導電柱電耦接到該重分佈層。

Description

半導體封裝結構
本發明半導體技術領域，尤其涉及一種半導體封裝結構。
由於半導體工業的進步，業界需要比上一代封裝結構佔用更小的空間的更小的封裝結構。一種技術解決方案是異構整合(heterogeneous integration)，即在同一封裝中整合複數個半導體晶粒。這樣，可以降低製造成本，同時仍然能夠提供高性能和高密度。
儘管現有的半導體封裝結構通常對於它們的預期目的是足夠的，但是它們在所有方面都不令人滿意。例如，在一些封裝結構中，銅-銅(Cu-Cu)接合技術被用於提供半導體晶粒之間的互連。在這種情況下，需要高溫和足夠的時間用於兩個Cu(銅)層之間的相互擴散，這增加了成本並導致製造過程中的困難。因此，需要進一步改善半導體封裝結構以降低生產成本並提高產量(yield)。
有鑑於此，本發明提供一種半導體封裝結構，以解決上述問題。
根據本發明的第一方面，公開一種半導體封裝結構，包括：基板；重分佈層，在該基板的上方； 第一半導體部件，在該重分佈層的上方；導電柱，與該第一半導體部件相鄰，其中該第一半導體部件和該導電柱由該模製材料圍繞；以及第二半導體部件，在該模製材料上，其中該第二半導體部件透過該導電柱電耦接到該重分佈層。
根據本發明的第二方面，公開一種半導體封裝結構，包括：基板；重分佈層，在該基板的上方；第一半導體部件，在該重分佈層的上方，並具有第一表面和與該第一表面相對的第二表面；通孔，在該第一半導體部件中，該通孔從該第一半導體部件的該第一表面延伸到該第一半導體部件的該第二表面；以及第二半導體部件，在該第一半導體部件的上方，其中該第二半導體部件透過該複數個凸塊結構電耦接至該第一半導體部件，並透過該複數個凸塊結構和該通孔電耦接至該重分佈層。
根據本發明的第三方面，公開一種半導體封裝結構，包括：基板；重分佈層，位於該基板上，並具有第一表面和與該第一表面相對的第二表面；複數個第一凸塊結構，位於該重分佈層的該第一表面上，並且將該重分佈層電耦接至該基板的佈線結構；第一半導體部件，位於該重分佈層的該第一表面上，並與該複數個第一凸塊結構相鄰；以及第二半導體部件，在該重分佈層的該第二表面上，其中該第二半導體部件 透過該重分佈層電耦接到該第一半導體部件，並透過該複數個第一凸塊結構電耦接到該基板的該佈線結構。
本發明的半導體封裝結構由於包括：第一半導體部件，在該重分佈層的上方；導電柱，與該第一半導體部件相鄰，其中該第一半導體部件和該導電柱由該模製材料圍繞；以及第二半導體部件，在該模製材料上，其中該第二半導體部件透過該導電柱電耦接到該重分佈層。本發明中採用導電柱與導電通孔連接，可以用於提供足夠的接合力的關鍵製程，無雜質的清潔表面以及平坦的表面，因此，可以降低製造難度，並且可以提高產量，也可以提供低成本的好處。
100,200,300,400,500:半導體封裝結構
102:基板
104:導電結構
106:底部填充材料
108:重分佈層
110:第一半導體部件
110a,128a:第一表面
110b,128b:第二表面
112,124,204:導電通孔
114,126,206:鈍化層
116,502:凸塊結構
118,504:底部填充材料
120:導電柱
122:模製材料
128:第二半導體部件
130:導電端子
202:通孔
302:粘合層
透過閱讀後續的詳細描述和實施例可以更全面地理解本發明，本實施例參照附圖給出，其中：
圖1-5是根據一些實施例的半導體封裝結構的截面圖。
以下描述是出於說明本發明的一般原理的目的，並且不應以限制意義來理解。本發明的範圍最好透過參考所附的申請專利範圍書來確定。
將針對特定實施例並參考某些附圖來描述本發明，但是本發明不限於此，而是僅由申請專利範圍書來限制。所描述的附圖僅是示意性的而非限制性的。在附圖中，出於說明的目的，一些元件的尺寸可能被放大並且未按比例繪製。在本發明的實踐中，尺寸和相對尺寸不對應於實際尺寸。
根據本發明的一些實施例描述了半導體封裝結構。每個半導體封裝結構都包括半導體部件，該半導體部件透過凸塊結構和/或透過重分佈層堆疊 而不是Cu-Cu(銅-銅)接合技術，從而可以降低製造難度，並且可以降低製造成本。
圖1是根據一些實施例的半導體封裝結構100的截面圖。可以將附加特徵添加到半導體封裝結構100。對於不同的實施例，可以替換或消除以下描述的一些特徵。為了簡化該圖，僅示出了半導體封裝結構100的一部分。
如圖1所示，根據一些實施例，半導體封裝結構100包括基板102。在一些實施例中，基板102包括絕緣芯(insulating core)，例如玻璃纖維增強樹脂芯(fiberglass reinforced resin core)，以防止基板102翹曲。基板102可在其中具有佈線結構。在一些實施例中，基板102的佈線結構包括導電層、導電通孔、導電柱等或其組合。基板102的佈線結構可以由諸如銅、鈦、鎢、鋁等的金屬或其組合形成。
基板102的佈線結構可以設置在金屬間介電(inter-metal dielectric，IMD)層中。在一些實施例中，IMD層可以由有機材料(例如，聚合物基礎材料)、非有機材料(例如，氮化矽、氧化矽、氮氧化矽等)或其組合形成。應當注意，附圖中所示的基板102的配置僅是示例性的，並且不旨在限制本發明。任何期望的半導體部件都可以形成在基板102之中和之上。然而，為了簡化該圖，僅示出了平坦基板102。
在一些實施例中，半導體封裝結構100包括重分佈層108。重分佈層108可以透過複數個導電結構104結合到基板102(或者可稱為載體基板)上。重分佈層108和重分佈層108以及基板102之間可以相互電耦接，並且可以將重分佈層108電耦接到基板102上。在一些實施例中，導電結構104包括諸如金屬的導電材料。例如，導電結構104可以由銅、鈦、鎢、鋁等或其組合製成。導電結構104可以是微凸塊、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、球柵陣列(ball grid array，BGA)球等、或它們的組合。
導電結構104可以由底部填充材料106圍繞。在一些實施例中，底部填充材料106設置在基板102和重分佈層108之間，並填充導電結構104之間的間隙以提供結構支撐。在一些實施例中，在基板102和重分佈層108之間形成導電結構104之後，可以用毛細作用力分配底部填充材料106。然後，底部填充材料106可以使用合適的固化過程來固化，諸如熱固化製程、紫外線(ultra-violet，UV)固化過程等。底部填充材料106可以由諸如環氧樹脂的聚合物形成。
如圖1所示，底部填充材料106可以覆蓋基板102的頂表面的一部分，並且基板102的頂表面的另一部分可以暴露。底部填充材料106可以延伸到重分佈層108的側壁，並且可以覆蓋重分佈層108的側壁的一部分。
重分佈層108可以包括一個或複數個導電層和鈍化層，其中一個或複數個導電層可以設置在一個或複數個鈍化層中。導電層可以包括金屬，例如銅、鈦、鎢、鋁等或其組合。在一些實施例中，鈍化層是聚合物層，例如，聚醯亞胺(polyimide，PI)、聚苯並惡唑(polybenzoxazole，PBO)、苯並環丁烯(benzocyclobutene，BCB)、環氧樹脂等或其組合。可選地，鈍化層可以是介電層，例如氧化矽、氮化矽、氮氧化矽等或其組合。
如圖1所示，根據一些實施例，半導體封裝結構100包括在重分佈層108上方的第一半導體部件110。在一些實施例中，第一半導體部件110是有源器件(active component)。例如，第一半導體部件110可以包括系統單晶片(system-on-chip，SoC)設備、邏輯裝置、記憶體裝置、射頻(radio frequency，RF)設備等或其任意組合。例如，第一半導體部件110可以包括微控制器(microcontroller，MCU)，微處理器(microprocessor，MPU)、電源管理積體電路(power management integrated circuit，PMIC)、全球定位系統(global positioning system，GPS)設備、中央處理單元(central processing unit，CPU)、 圖形處理單元(graphics processing unit，GPU)、動態隨機存取記憶體(dynamic random access memory，DRAM)控制器、靜態隨機存取記憶體(static random-access memory，SRAM)、高頻寬記憶體(high bandwidth memory，HBM)等或其任意組合。在一些其他實施例中，第一半導體部件110包括無源器件，諸如電阻器，電容器，電感器等或其組合。
第一半導體部件110可以具有第一表面110a和與第一表面110a相對的第二表面110b。第一表面110a可以比第二表面110b更靠近重分佈層108。如圖1所示，在一些實施例中，第一半導體部件110的第一表面110a可以與重分佈層108接觸(例如直接接觸)。替代地，在一些其他實施例中，第一半導體部件110的第一表面110a可以與重分佈層108間隔開間隙。重分佈層108可以橫向地延伸超過第一半導體部件110的側壁。
複數個導電通孔112和鈍化層114可以佈置在第一半導體部件110的第二表面110b上。導電通孔112可以佈置在鈍化層114中並且可以被電耦接到第一半導體導電通孔112可以包括金屬，例如銅、鈦、鎢、鋁等或其組合。在一些實施例中，鈍化層114是聚合物層，例如，聚醯亞胺(polyimide，PI)、聚苯並惡唑(polybenzoxazole，PBO)、苯並環丁烯(benzocyclobutene，BCB)、環氧樹脂等或其組合。替代地，鈍化層114可以是介電層，諸如氧化矽、氮化矽、氮氧化矽等或其組合。
如圖1所示，根據一些實施例，半導體封裝結構100包括在導電通孔112上方的複數個凸塊結構116。凸塊結構116可以電耦接到第一半導體部件110。在一些實施例中，凸塊結構116包括諸如金屬的導電材料。例如，凸塊結構116可以由銅、鈦、鎢、鋁等或其組合製成。凸塊結構116可以是焊球、微凸塊、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、球柵陣列(ball grid array，BGA)球等或它們的組合。
凸塊結構116可以由底部填充材料118圍繞。在一些實施例中，底部填充材料118填充凸塊結構116之間的間隙以提供結構支撐。底部填充材料118可以包括不導電膏(non-conductive paste，NCP)、不導電膜(non-conductive film，NCF)等或它們的組合，並且可以由諸如環氧樹脂的聚合物形成。
如圖1所示，根據一些實施例，半導體封裝結構100包括在重分佈層108上方的一個或複數個導電柱120。導電柱120可以與第一半導體部件110相鄰並且可以佈置在第一半導體部件110的相對側上。導電柱120可以電耦接到重分佈層108。在一些實施例中，導電柱120包括金屬，例如銅、鈦、鎢、鋁等或其組合。導電柱120可以透過電鍍製程或任何其他合適的製程形成。
如圖1所示，根據一些實施例，導電柱120的高度大於第一半導體部件110的高度。另外，導電柱120的高度可以基本等於第一半導體部件110、導電通孔112和凸塊結構116的總高度。如圖所示，導電柱120可以具有基本垂直的側壁。圖中所示的導電柱120的構造僅是示例性的，並不旨在限制本發明。每個導電柱120可以具有不同的形狀。
如圖1所示，第一半導體部件110設置在重分佈層108的頂表面的中心，並且導電柱120的數量在第一半導體部件110的相對側上相等，但是本發明不限於此。例如，導電柱120的數量可以在第一半導體部件110的相對側上不同。可選地，導電柱120可以設置在第一半導體部件110的一側上。
如圖1所示，根據一些實施例，模製材料122設置在重分佈層108上並且圍繞第一半導體部件110和每個導電柱120。模製材料122可以防止第一半導體部件110和導電柱120由於例如應力、化學物質和/或濕氣而損壞。
在一些實施例中，模製材料122包括非導電材料，例如可模製的聚合物、環氧樹脂、樹脂等或其組合。在一些實施例中，以液體或半液體形式施加模製材料122，然後使用合適的固化製程(例如熱固化製程、UV固化製程 等)或其組合來固化。模製材料122可以用模具(未示出)成形或模製。
模製材料122可以填充第一半導體部件110和導電柱120之間的間隙。模製材料122可以鄰接第一半導體部件110和導電柱120的側壁。模製材料122的側壁半導體層110可以與重分佈層108的側壁基本共面。如前所述，第一半導體部件110可以與重分佈層108間隔一定的距離。在這種情況下，模製材料122也可以填充在第一半導體部件110和重分佈層108之間的間隙中。
如圖1所示，根據一些實施例，半導體封裝結構100包括在模製材料122上方的第二半導體部件128。在一些實施例中，第二半導體部件128是有源器件。例如，第二半導體部件128可以包括系統單晶片(SoC)晶粒，邏輯裝置、記憶體裝置、射頻(RF)設備等或其任意組合。例如，第二半導體部件128可以包括微控制器(MCU)、微處理器(MPU)、電源管理積體電路(PMIC)、全球定位系統(GPS)設備、中央處理單元(CPU)、圖形處理單元(GPU)、動態隨機存取記憶體(DRAM)控制器、靜態隨機存取記憶體(SRAM)、高頻寬記憶體(HBM)等或其任意組合。在一些其他實施例中，第二半導體部件128包括無源器件，例如電阻器、電容器、電感器等或其組合。
第一半導體部件110和第二半導體部件128可以包括相同或不同的器件。例如，第一半導體部件110可以是無源器件，第二半導體部件128可以是有源器件。替代地，第一半導體部件110和第二半導體部件128可以是具有不同功能和/或不同世代晶片的有源器件。
在一些其他實施例中，一個或複數個無源器件也被佈置在重分佈層108之上，諸如電阻器、電容器、電感器等或其組合。儘管在圖1中示出了兩個半導體部件，即第一半導體部件110和第二半導體部件128，但是半導體部件的數量可以大於兩個。
如圖1所示，第二半導體部件128的側壁可以與模製材料122 的側壁基本上共面，並且可以與重分佈層108的側壁基本上共面。第二半導體部件128可以具有第一表面128a和與第一表面128a相對的第二表面128b。第二半導體部件128的第一表面128a可以比第二半導體部件128的第二表面128b更靠近第一半導體部件110的第二表面110b。
在一些實施例中，第二半導體部件128的第二表面128b如圖所示地暴露。因此，可以解決散熱問題。本發明不限於此。在一些其他實施例中，第二半導體部件128的第二表面128b可以不暴露。例如，第二半導體部件128的第二表面128b可以由模製材料覆蓋。
仍參考圖1，根據一些實施例，複數個導電通孔124和鈍化層126可以設置在第二半導體部件128的第一表面128a上。導電通孔124可以設置在鈍化層126中並且可以電耦接至第二半導體部件128。導電通孔124可以包括金屬，諸如銅、鈦、鎢、鋁等或其組合。在一些實施例中，鈍化層126是聚合物層，例如，聚醯亞胺(PI)、聚苯並惡唑(PBO)、苯並環丁烯(BCB)、環氧樹脂等或其組合。替代地，鈍化層126可以是介電層，諸如氧化矽、氮化矽、氮氧化矽等或它們的組合。
凸塊結構116可以設置在導電通孔112和導電通孔124之間，並且可以將導電通孔112電耦接到導電通孔124。即，導電通孔112和導電通孔124透過以下方式連接：凸塊結構116代替透過Cu-Cu接合技術連接。本實施例中採用凸塊結構116來將導電通孔112和導電通孔124進行連接，可以避免與Cu-Cu接合技術有關的問題，例如用於提供足夠的接合力的關鍵製程，無雜質的清潔表面以及平坦的表面。因此，可以降低製造難度，並且可以提高產量。也可以提供低成本的好處。此外，當導電通孔112和導電通孔124之間的直徑或尺寸差距較大時，採用凸塊結構116可以更加準確和穩定的將導電通孔112和導電通孔124進行連接，而不必擔心錯位等問題，因此可以實現對不同晶片尺 寸的靈活性以及與不同世代晶片的異構整合。
導電通孔124可以電耦接到凸塊結構116和導電柱120。第二半導體部件128可以透過導電通孔124和導電柱120被電耦接到重分佈層108。部件128可以透過導電通孔112、、凸塊結構116和導電通孔124電耦接到第一半導體部件110。第一半導體部件110可以透過導電通孔112、凸點結構116和導電通孔124和導電柱120電耦接到重分佈層108。本實施例中採用導電柱120與導電通孔124連接(直接連接)，兩者之間沒有銅柱等結構，可以用於提供足夠的接合力的關鍵製程，無雜質的清潔表面以及平坦的表面，因此，可以降低製造難度，並且可以提高產量。也可以提供低成本的好處。此外本實施例中可以在形成導電柱120之後形成模製材料122圍繞導電柱120，因此先形成的導電柱120可以更好地與導電通孔124連接。
如圖1所示，根據一些實施例，半導體封裝結構100包括在基板102下方的複數個導電端子130。導電端子130可以電耦接到基板102的佈線結構。導電端子130可以包括諸如金屬的導電材料。例如，導電端子130可以由銅、鈦、鎢、鋁等或其組合製成。導電端子130可以是微凸塊、受控塌陷晶片連接(C4)凸塊、球柵陣列(BGA)球等或它們的組合。
圖2是根據本發明的一些其他實施例的半導體封裝結構200的截面圖。應當注意，半導體封裝結構200可以包括與圖1所示的半導體封裝結構100相同或相似的部件，並且為了簡單起見，將不再詳細討論那些部件。在以下實施例中，第一半導體部件110包括一個或複數個用於雙面連接的通孔202。即，第一半導體部件110的相對表面可以用於連接。
第一半導體部件110可以具有第一表面110a和與第一表面110a相對的第二表面110b。第一表面110a可以比第二表面110b更靠近重分佈層108。如圖2所示，第一半導體部件110包括一個或複數個從第一表面110a延 伸到第二表面110b並具有基本垂直的側壁的通孔202，但是本發明不限於此。通孔202可以具有其他構造。通孔202可以用於半導體所需的不同用途的連接，增加電性連接設計的靈活性，保留設計彈性，以適應不同的電性連接需求。
通孔202可以由諸如金屬的任何導電材料形成。例如，通孔202可以由銅、鈦、鎢、鋁等或其組合形成。通孔202可以透過複數個導電通孔124電耦接到第二半導體部件128，並且可以透過複數個導電通孔204電耦接到重分佈層108。導電通孔204和鈍化層206可以是設置在第一半導體部件110的第一表面110a上。導電通孔204可以設置在鈍化層206中，並可以電連接到通孔202和重分佈層108。
導電通孔204可以包括金屬，例如銅、鈦、鎢、鋁等或其組合。在一些實施例中，鈍化層206是聚合物層，例如，聚醯亞胺(PI)、聚苯並惡唑(PBO)、苯並環丁烯(BCB)、環氧樹脂等或其組合。可選地，鈍化層206可以是介電層，諸如氧化矽、氮化矽、氮氧化矽等或其組合。
第一半導體部件110可以透過導電通孔204電耦接到重分佈層108。第二半導體部件128可以透過導電通孔124、凸點結構116、導電通孔112、通孔202、導電通孔204和導電柱120電耦接到重分佈層108。
圖3是根據本發明的一些其他實施例的半導體封裝結構300的截面圖。應當注意，半導體封裝結構300可以包括與圖1所示的半導體封裝結構100相同或相似的部件，並且為了簡單起見，將不再詳細討論那些部件。與其中透過凸塊結構連接半導體部件的圖1和圖2的實施例相比，在以下實施例中，透過重分佈層連接半導體部件。
第一半導體部件110可以透過導電通孔204電耦接到重分佈層108，第二半導體部件128可以透過導電通孔124和導電柱120電耦接到重分佈層108。特別地，重分佈層108可以整合來自第一半導體部件110和第二半導體 部件128的訊號。即，根據一些實施例，第一半導體部件110透過導電通孔204、重分佈層108、導電柱120和導電通孔124電耦接到第二半導體部件128。由於第一半導體部件110和第二半導體部件128沒有透過Cu-Cu接合技術連接，所以可以防止相關問題。需要注意的是，本實施例中重分佈層108是在具有第一半導體部件110和導電通孔204之後再形成的。本實施例中第一半導體部件110和第二半導體部件128透過重分佈層108的佈線進行電連接；此外，在第一半導體部件110的導電通孔204上(圖中為下表面)形成的重分佈層108的佈線是繞線(例如經過蝕刻等製程形成)。
如圖3所示，粘合層302可以形成在第一半導體部件110的第二表面110b上。粘合層302可以是晶粒附著膜(die attach film，DAF)、背面塗布帶(backside coating tape，LC)膠帶、半固化片材料等或其組合。粘合層302可以由環氧樹脂或任何合適的材料製成。本實施例中第一半導體部件110和第二半導體部件128的主動面均朝向基板102，因此本實施例中提供了另一種半導體封裝結構的實現方式，也提供了另一種製造過程，這樣可以滿足各種所需的製程要求。
圖4是根據本發明的一些其他實施例的半導體封裝結構400的截面圖。應當注意，半導體封裝結構400可以包括與圖2所示的半導體封裝結構200相同或相似的部件，並且為了簡單起見，將不再詳細討論那些部件。在以下實施例中，第一半導體部件110和第二半導體部件128具有相似的尺寸。可以去除導電柱(例如，如圖2所示的導電柱120)。本實施例中第一半導體部件110和第二半導體部件128可以具有相同的尺寸，以滿足不同的封裝需求。通孔202可以用於所需的電連接，以滿足不同的設計要求，增加設計的彈性。
如圖4所示，第一半導體部件110包括一個或複數個用於雙面連接的通孔202。即，第一半導體部件110的相對表面可以用於連接。第一半導體 部件110可以具有第一表面110a和與第一表面110a相對的第二表面110b。第一表面110a可以比第二表面110b更靠近重分佈層108。如圖4所示，第一半導體部件110包括一個或複數個通孔202，其從第一半導體部件110的第一表面110a延伸到第一半導體部件110的第二表面110b，並具有基本垂直的側壁，但是本發明不限於此。通孔202可以具有其他構造。
通孔202可以由諸如金屬的任何導電材料形成。例如，通孔202可以由銅、鈦、鎢、鋁等或其組合形成。第一半導體部件110可以在第一表面110a上具有複數個導電通孔204，並且在第二表面110b上具有複數個導電通孔112。通孔202可以電耦接到導電通孔112和導電通孔204，並且可以透過導電通孔204電耦接到重分佈層108。
第二半導體部件128可以在第一表面128a上具有複數個導電通孔124，並且第二半導體部件128的第二表面128b可以暴露。複數個凸塊結構116可以設置在導電通孔124和導電通孔112之間並且電耦接到導電通孔124和導電通孔112。因此，第二半導體部件128可以透過導電通孔124、凸塊結構116、導電通孔112、通孔202和導電通孔204電耦接到重分佈層108。
由於導電通孔112和導電通孔124透過凸塊結構116連接，因此可以消除Cu-Cu接合技術。因此，降低了製造難度，並且可以提高成品率。製造成本也可以降低。凸塊結構116可以用於連接具有不同尺寸的半導體部件(例如，在半導體封裝結構100、200和300中)，並且可以用於連接具有相似尺寸的半導體部件(例如，在半導體封裝結構400中)。
圖5是根據本發明的一些其他實施例的半導體封裝結構500的截面圖。應當注意，半導體封裝結構500可以包括與圖1所示的半導體封裝結構100相同或相似的部件，並且為了簡單起見，將不再詳細討論那些部件。在以下實施例中，第一半導體部件110設置在基板102和重分佈層108之間。
如圖5所示，重分佈層108可以具有第一表面108a和與第一表面108b相對的第二表面108b。第一表面108a可以比第二表面108b更靠近基板102。第一半導體部件110可以設置在重分佈層108的第一表面108a上。重分佈層108可以橫向地延伸超過第一半導體部件110的側壁。複數個凸塊結構116和複數個導電通孔112可以可以將第一半導體部件110設置在第一半導體部件110和重分佈層108之間，並且可以將第一半導體部件110電耦接到重分佈層108。
根據一些實施例，半導體封裝結構500包括在重分佈層108的第一表面108a上的複數個凸塊結構502。凸塊結構502可以形成在重分佈層108和基板102之間，並且可以將重分佈層108電耦接到基板102。也就是說，訊號從凸塊結構502輸出到基板102。凸塊結構502包括諸如金屬的導電材料。例如，凸塊結構502可以由銅、鈦、鎢、鋁等或其組合製成。凸塊結構502可以是微凸塊，受控塌陷晶片連接(C4)凸塊、球柵陣列(BGA)球等或其組合。
凸塊結構502可以與第一半導體部件110相鄰。凸塊結構502可以設置在第一半導體部件110的相對側，並且凸塊結構502的數量可以相同或不同。另外，凸塊結構502的高度可以基本等於第一半導體部件110、導電通孔112和凸塊結構116的總高度。
第一半導體部件110和凸塊結構502可以由底部填充材料504包圍。導電通孔112和凸塊結構116也可以由底部填充材料504包圍。在一些實施例中，底部填充材料504是底部填充材料504。在基板102和重分佈層108之間形成間隙，並填充第一半導體部件110和凸塊結構502之間的間隙以提供結構支撐。
在一些實施例中，可以在第一半導體部件110和凸塊結構502在基板102和重分佈層108之間形成之後，用毛細力來分配底部填充材料504。 然後，底部填充材料504可以使用合適的固化過程來固化，例如熱固化過程、紫外線(UV)固化過程等。底部填充材料504可以由諸如環氧樹脂的聚合物形成。
底部填充材料504可以覆蓋基板102的頂表面的一部分，並且基板102的頂表面的另一部分可以暴露。底部填充材料504可以延伸到重分佈層108的側壁，並且可以覆蓋重分佈層108的側壁的一部分。
第二半導體部件128可以佈置在重分佈層108的第二表面108b上。複數個導電通孔124可以佈置在第二半導體部件128和重分佈層108之間，並且可以將第二半導體電耦接。第二半導體部件128可以透過導電通孔124、重分佈層108和凸塊結構502電耦接到基板102的佈線結構。
根據一些實施例，第一半導體部件110透過導電通孔112、凸塊結構116、重分佈層108和導電通孔124電耦接到第二半導體部件128。特別地，重分佈層108可以整合來自第一半導體部件110和第二半導體部件128的訊號。因此，可以防止與Cu-Cu接合技術有關的問題。本實施例中，在形成重分佈層108之後，再安裝第一半導體部件110，因此使用了凸塊結構116電連接重分佈層108的佈線與第一半導體部件110的導電通孔112。本實施例中第一半導體部件110還可以使無源器件或被動器件等等。本實施例中第一半導體部件110和第二半導體部件128均透過凸塊結構502連接到基板102。第一半導體部件110和第二半導體部件128主動面相互面對。
總而言之，本發明提供了具有透過凸塊結構和/或透過重分佈層堆疊的半導體部件的半導體封裝結構。在一些實施例中，半導體部件透過凸塊結構連接。在一些其他實施例中，來自半導體部件的訊號可以透過再分配層整合。因此，可以消除由於Cu-Cu接合技術而導致的關鍵製程。即，可以降低製造難度，從而可以提高成品率。製造成本也可以降低。而且，可以實現對不同 晶片尺寸的靈活性以及與不同代晶片的異構整合。在一些實施例中，散熱問題也可以解決。
儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。本領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。
100:半導體封裝結構
102:基板
104:導電結構
106:底部填充材料
108:重分佈層
110:第一半導體部件
110a,128a:第一表面
110b,128b:第二表面
112,124:導電通孔
114,126:鈍化層
116:凸塊結構
118:底部填充材料
120:導電柱
122:模製材料
128:第二半導體部件

Claims (18)

  1. 一種半導體封裝結構，包括：基板；重分佈層，在該基板的上方；第一半導體部件，在該重分佈層的上方；導電柱，與該第一半導體部件相鄰，其中該第一半導體部件和該導電柱由該模製材料圍繞；以及第二半導體部件，在該模製材料上，其中該第二半導體部件透過該導電柱電耦接到該重分佈層；第一鈍化層，設置在該第一半導體部件上；第一導電通孔，設置在該第一鈍化層中並連接到該第一半導體部件；第二鈍化層，設置在該第二半導體部件上；第二導電通孔，設置在該第二鈍化層中並連接到該第二半導體部件；複數個凸塊結構，設置在該第一導電通孔與該第二導電通孔之間，並直接連接該第一導電通孔和對應的該第二導電通孔。
  2. 如請求項1之半導體封裝結構，其中，該第一半導體部件透過複數個凸塊結構電耦接至該第二半導體部件。
  3. 如請求項2之半導體封裝結構，其中，該第一半導體部件透過該複數個凸塊結構、該第二半導體部件和該導電柱電耦接至該重分佈層。
  4. 如請求項1之半導體封裝結構，其中，該第一半導體部件包括通孔，並且該通孔電耦接至該重分佈層。
  5. 如請求項4之半導體封裝結構，其中，該第二半導體部件透過該複數個凸塊結構和該通孔電耦接到該重分佈層。
  6. 如請求項1之半導體封裝結構，其中，該模製材料的側壁與 該重分佈層的側壁共面。
  7. 如請求項6之半導體封裝結構，其中，該模製材料的側壁與該第二半導體部件的側壁共面。
  8. 一種半導體封裝結構，包括：基板；重分佈層，在該基板的上方；第一半導體部件，在該重分佈層的上方；導電柱，與該第一半導體部件相鄰，其中該第一半導體部件和該導電柱由該模製材料圍繞；以及第二半導體部件，在該模製材料上，其中該第二半導體部件透過該導電柱電耦接到該重分佈層；粘合層，在該第一半導體部件和該第二半導體部件之間；鈍化層，設置在該第二半導體部件上；導電通孔，設置在該第二鈍化層中並連接到該第二半導體部件；其中，該導電柱直接與對應的該導電通孔連接。
  9. 如請求項8之半導體封裝結構，其中，該第一半導體部件透過該導電柱和該重分佈層與該第二半導體部件電連接。
  10. 一種半導體封裝結構，包括：基板；重分佈層，在該基板的上方；第一半導體部件，在該重分佈層的上方，並具有第一表面和與該第一表面相對的第二表面；通孔，在該第一半導體部件中，該通孔從該第一半導體部件的該第一表面延伸到該第一半導體部件的該第二表面；以及 第二半導體部件，在該第一半導體部件的上方，其中該第二半導體部件透過複數個凸塊結構電耦接至該第一半導體部件，並透過該複數個凸塊結構和該通孔電耦接至該重分佈層；第一鈍化層，設置在該第一半導體部件上；第一導電通孔，設置在該第一鈍化層中並連接到該第一半導體部件；第二鈍化層，設置在該第二半導體部件上；第二導電通孔，設置在該第二鈍化層中並連接到該第二半導體部件；其中，該複數個凸塊結構直接連接該第一導電通孔和該第二導電通孔。
  11. 如請求項10之半導體封裝結構，其中，還包括位於該重分佈層與該基板之間的複數個導電結構，其中，該複數個導電結構電耦接至該重分佈層與該基板的佈線結構。
  12. 如請求項10之半導體封裝結構，還包括在該基板下方的複數個導電端子，其中，該複數個導電端子電耦接至該基板的佈線結構。
  13. 一種半導體封裝結構，包括：基板；重分佈層，位於該基板上，並具有第一表面和與該第一表面相對的第二表面；複數個第一凸塊結構，位於該重分佈層的該第一表面上，並且將該重分佈層電耦接至該基板的佈線結構；第一半導體部件，位於該重分佈層的該第一表面上，並與該複數個第一凸塊結構相鄰；以及第二半導體部件，在該重分佈層的該第二表面上，其中該第二半導體部件透過該重分佈層電耦接到該第一半導體部件，並透過該複數個第一凸塊結構電耦接到該基板的該佈線結構； 第一鈍化層，設置在該第一半導體部件上；第一導電通孔，設置在該第一鈍化層中並連接到該第一半導體部件；複數個第二凸塊結構，設置在該重分佈層和該第一導電通孔之間並直接連接該重分佈層和該第一導電通孔。
  14. 如請求項13之半導體封裝結構，其中該第一半導體部件透過該複數個第二凸塊結構電耦接到該重分佈層。
  15. 如請求項13之半導體封裝結構，其中，還包括圍繞該複數個第一凸塊結構和該複數個第二凸塊結構的底部填充材料。
  16. 如請求項15之半導體封裝結構，其中，該底部填充材料覆蓋該第一半導體部件的側壁。
  17. 如請求項13之半導體封裝結構，其中，該複數個第一凸塊結構的高度大於該第一半導體部件的高度。
  18. 如請求項13之半導體封裝結構，其中，該重分佈層橫向地延伸超過該第一半導體部件的側壁。
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