CN103730379A - 芯片封装方法及结构 - Google Patents

芯片封装方法及结构 Download PDF

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Publication number
CN103730379A
CN103730379A CN201410018025.4A CN201410018025A CN103730379A CN 103730379 A CN103730379 A CN 103730379A CN 201410018025 A CN201410018025 A CN 201410018025A CN 103730379 A CN103730379 A CN 103730379A
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China
Prior art keywords
chip
insulating barrier
opening
pad
metal interconnect
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CN201410018025.4A
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English (en)
Inventor
王之奇
李俊杰
杨莹
喻琼
王蔚
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China Wafer Level CSP Co Ltd
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China Wafer Level CSP Co Ltd
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Priority to CN201410018025.4A priority Critical patent/CN103730379A/zh
Publication of CN103730379A publication Critical patent/CN103730379A/zh
Priority to US14/590,891 priority patent/US9748162B2/en
Pending legal-status Critical Current

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Abstract

一种芯片封装方法和结构，所述芯片封装方法包括：提供第一芯片，所述第一芯片包括第一表面和与所述第一表面相对的第二表面，所述第一芯片的第一表面具有多个第一焊盘；提供第二芯片，所述第二芯片包括第三表面和与所述第三表面相对的第四表面，所述第二芯片的第三表面具有多个第二焊盘，所述第二芯片的面积大于第一芯片的面积；将所述第一芯片的第二表面与所述第二芯片的第三表面相结合，所述多个第二焊盘位于所述第一芯片和第二芯片的结合区域之外；形成第一绝缘层，所述第一绝缘层包覆所述第一芯片并与所述第二芯片结合。本发明的芯片封装方法工艺简单，封装结构体积小。

Description

芯片封装方法及结构
技术领域
本发明涉及半导体技术领域，尤其涉及一种芯片封装方法及结构。
背景技术
随着半导体芯片制造、集成和封装技术的不断进步，电子系统逐渐显现出多功能、高性能和高可靠性的发展趋势。为了将多个具有不同功能的有源组件与无源组件，以及诸如微机电系统（MEMS）、光学（Optics）元件等其它元件组合在同一封装体，使其成为可提供多种功能的一个系统或子系统，业界提出了系统级封装技术。
系统级封装可以作为一块标准单元用于PCB组装，也可以是最终的电子产品。与传统的芯片封装不同，系统级封装不仅可以应用于数字系统，还可以应用于光通讯、传感器以及MEMS等领域，因此，在计算机、自动化、通讯业等领域，系统级封装得到了广泛的应用。
现有的系统级封装采用金属引线工艺，将芯片与芯片间的焊盘用金属线进行引线键合，起到电学连接的作用；另外，现有的系统级封装还采用将两个芯片具有焊盘的表面相对贴合之后进行电学连接的封装方式。但是，上述的封装方法工艺复杂。
发明内容
本发明解决的问题是提供一种芯片封装方法和封装结构。
为解决上述问题，本发明提供了一种芯片封装方法，包括：提供第一芯片，所述第一芯片包括第一表面和与所述第一表面相对的第二表面，所述第一芯片的第一表面具有多个第一焊盘；提供第二芯片，所述第二芯片包括第三表面和与所述第三表面相对的第四表面，所述第二芯片的第三表面具有多个第二焊盘，所述第二芯片的面积大于第一芯片的面积；将所述第一芯片的第二表面与所述第二芯片的第三表面相结合，所述多个第二焊盘位于所述第一芯片和第二芯片的结合区域之外；形成第一绝缘层，所述第一绝缘层包覆所述第一芯片并与所述第二芯片结合。
可选的，所述第一芯片的第二表面与所述第二芯片的第三表面通过绝缘胶层结合。
可选的，所述第一绝缘层和所述绝缘胶层与所述第二芯片结合面的面积大于所述第一芯片的面积。
可选的，所述第一绝缘层为感光干膜、非感光干膜或者塑封材料。
可选的，所述第一绝缘层覆盖所述第一焊盘和所述第二焊盘。
可选的，还包括：刻蚀所述第一绝缘层，分别形成暴露出所述多个第一焊盘的多个第一开口和暴露出所述多个第二焊盘的多个第二开口。
可选的，还包括：形成多个金属互连结构，所述金属互连结构覆盖所述第一开口和所述第二开口的底部和侧壁、以及部分所述第一绝缘层的顶表面，所述金属互连结构与所述第一焊盘和所述第二焊盘电学连接。
可选的，还包括：在所述第一开口内形成第一插塞；在所述第二开口内形成第二插塞；在所述第一绝缘层上形成多个金属互连结构，所述金属互连结构与所述第一插塞和所述第二插塞电学连接。
可选的，还包括：在所述第一绝缘层和所述金属互连结构上形成第二绝缘层，所述第二绝缘层具有暴露出部分所述金属互连结构的第三开口；在所述第三开口内形成与所述金属互连结构电学连接的金属凸块，所述金属凸块的高度不低于所述第二绝缘层的顶部。
对应的，本发明还提供了一种芯片封装结构，包括：第一芯片，所述第一芯片包括第一表面和与所述第一表面相对的第二表面，所述第一芯片的第一表面具有多个第一焊盘；第二芯片，所述第二芯片包括第三表面和与所述第三表面相对的第四表面，所述第二芯片的第三表面具有多个第二焊盘，所述第二芯片的面积大于所述第一芯片的面积，所述第一芯片的第二表面与所述第二芯片的第三表面结合在一起，所述多个第二焊盘位于所述第一芯片与所述第二芯片的结合区域之外；第一绝缘层，所述第一绝缘层包覆所述第一芯片并与所述第二芯片结合。
可选的，还包括：绝缘胶层，位于所述第一芯片的第二表面与所述第二芯片的第三表面之间。
可选的，所述第一绝缘层和所述绝缘胶层与所述第二芯片结合面的面积大于所述第一芯片的面积。
可选的，所述第一绝缘层为感光干膜、非感光干膜或者塑封材料。
可选的，所述第一绝缘层具有暴露出所述多个第一焊盘的多个第一开口和暴露出所述多个第二焊盘的多个第二开口。
可选的，还包括：多个金属互连结构，覆盖所述第一开口和所述第二开口的底部和侧壁、以及部分所述第一绝缘层的顶表面，与所述第一焊盘和所述第二焊盘电学连接。
可选的，还包括：多个第一插塞，位于所述多个第一开口内，分别与所述多个第一焊盘对应电学连接；多个第二插塞，位于所述多个第二开口内，分别与所述多个第二焊盘对应电学连接；多个金属互连结构，位于所述第一绝缘层上，与所述第一插塞和所述第二插塞电学连接。
可选的，还包括：第二绝缘层，位于所述第一绝缘层和所述金属互连结构上，具有暴露出部分所述金属互连结构的第三开口；多个金属凸块，位于所述第三开口内且与所述多个金属互连结构对应电学连接，所述多个金属凸块的高度不低于所述第二绝缘层的顶部。
与现有技术相比，本发明技术方案具有以下优点：
本发明实施例的芯片封装方法中，将第一芯片的不具有焊盘的第二表面与所述第二芯片的第三表面相粘合，无需使第一芯片上的焊盘与第二芯片上的焊盘相对应，因此也无需形成再分布层（RDL），工艺简单。且由于本实施例中第一芯片和第二芯片上无需形成再分布层，第一芯片和第二芯片的厚度可以在原有基础上进一步减薄，使得封装结构的体积更小。另外，本实施例中，在将第一芯片与第二芯片相结合之后，还形成了第一绝缘层，所述第一绝缘层包覆所述第一芯片并与所述第二芯片相结合。增强了第一芯片和第二芯片之间结合的结构强度，使得第一芯片不容易从第二芯片上脱落，增强了整个封装结构的可靠性。
进一步的，本发明实施例的芯片封装方法中，通过形成绝缘层和金属互连结构，将金属凸块转移至绝缘层上，使得金属凸块高于第一芯片，无需因为金属凸块的高度小于第一芯片的厚度而在PCB板上形成额外的开孔，而可以直接通过金属凸块将第一芯片和第二芯片的封装结构结合至PCB板，简化了工艺。
对应的，本发明实施例的芯片封装结构也具有上述优点。
附图说明
图1是现有技术的芯片封装结构的剖面结构示意图；
图2是本发明一实施例的芯片封装方法100的流程示意图；
图3至图9是图2所示的芯片封装方法100封装过程中的中间结构的剖面结构示意图；
图10是本发明另一实施例的芯片封装方法200的流程示意图；
图11至图18是图10所示的芯片封装方法200封装过程中的中间结构的剖面结构示意图。
具体实施方式
本发明的发明人研究发现，通常地，两个芯片进行封装时，将两个芯片具有焊盘的表面相对结合以实现电学连接。请参考图1，图1为现有技术中两个大小不同的芯片进行系统级封装的剖面结构示意图，包括：第一芯片110，所述第一芯片110的表面具有第一焊盘111；第二芯片120，所述第二芯片120的面积大于所述第一芯片110，所述第二芯片120的表面具有第二焊盘121和第三焊盘122，所述第二芯片120表面的第二焊盘121与所述第一芯片110表面的第一焊盘111对应结合在一起；绝缘胶130，位于所述第一芯片110表面和第二芯片120表面之间的空隙内，用于粘合所述第一芯片110和所述第二芯片120；锡球140，位于所述第三焊盘122之上，用于与外部电路（如PCB板）电学连接。但是，上述的封装结构中，所述第一芯片110表面的第一焊盘111与所述第二芯片120表面的第二焊盘121通常为再分布层。所述再分布层通过在芯片表面形成额外的绝缘层以及金属层，使得芯片上原有的焊盘重新排布形成再分布层，以符合封装工艺的设计规则，使得所述第一芯片110表面的第一焊盘111能够与所述第二芯片120表面的第二焊盘121能够相互对应。再分布层的形成工艺复杂，且由于需要在第一芯片110和第二芯片120上形成再分布层，第一芯片110和第二芯片120的厚度不能太薄，导致封装结构的尺寸较大。
基于以上研究，本发明实施例提出了一种芯片封装方法，可以减小整体封装后的厚度、增加系统级芯片封装的可靠性以及降低芯片封装的工艺难度。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
需要说明的是，提供这些附图的目的是有助于理解本发明的实施例，而不应解释为对本发明的不当的限制。为了更清楚起见，图中所示尺寸并未按比例绘制，可能会做放大、缩小或其他改变。
请参考图2，图2示出了本发明一实施例的芯片封装方法100的流程示意图。下面结合附图对本发明第一实施例的芯片封装方法的步骤进行说明。
步骤S101，参考图3，提供第一芯片210，所述第一芯片210包括第一表面210a和与所述第一表面210a相对的第二表面210b，所述第一芯片210的第一表面210a具有多个第一焊盘211；提供第二芯片220，所述第二芯片220包括第三表面220a和与所述第三表面220a相对的第四表面220b，所述第二芯片220的第三表面220a具有多个第二焊盘221，所述第二芯片220的面积大于第一芯片210的面积。
所述第一芯片210和所述第二芯片220可以为单晶硅、SOI（绝缘体上硅）、SiGe或III-V族化合物材料。所述第一芯片210和所述第二芯片220包括制作于其中的半导体器件、金属互连结构以及其他半导体结构。所述第一芯片210和所述第二芯片220包含一个广义的范围，包括例如处理器、存储器以及控制器等集成电路芯片，也包括例如CCD、CMOS图像传感器等光学传感器芯片或者热传感器芯片、运动传感器芯片等其他传感器芯片，还包括微机电元件（MEMS）芯片等。
本实施例中，所述第一焊盘211和所述第二焊盘221分别为所述第一芯片210和第二芯片220的顶层金属电极或者位于顶层金属电极上的焊盘。所述第一焊盘211和第二焊盘221的材料可以为金、铜、铝或者银。在另外一些实施例中，所述第一焊盘211和所述第二焊盘221也可以为再分布层。
步骤S102，参考图4，将所述第一芯片210的第二表面210b与所述第二芯片220的第三表面220a相结合，所述多个第二焊盘221位于所述第一芯片210和第二芯片220的结合区域之外。
在一些实施例中，在所述第一芯片210的第二表面210b上形成绝缘胶层230，用于将所述第一芯片210的第二表面210b与所述第二芯片220的第三表面220a相结合。在另一些实施例中，在所述第二芯片220的第三表面220a的待结合区域上形成绝缘胶层230，将所述第一芯片210的第二表面210b与所述第二芯片220的第三表面220a相结合。所述绝缘胶层230的材料可以为绝缘硅胶、聚酰亚胺、BCB树脂等。所述绝缘胶层230用于粘合所述第一芯片210的第二表面210b与所述第二芯片220的第三表面220a，增强两者之间的结合力。
本实施例中，在将所述第一芯片210的第二表面210b与所述第二芯片220的第三表面220a相结合之前，还对所述第一芯片210和所述第二芯片220进行了减薄处理；通过减少所述第一芯片210和第二芯片220的厚度，可以减少整体封装结构的厚度。所述减薄处理是本领域技术人员所熟知的工艺，在此不再赘述。
与现有技术相比，本实施例中，将所述第一芯片210的第二表面210b与所述第二芯片220相结合，无需使得第一芯片210的第一表面210a上的第一焊盘211与第二芯片220上的焊盘相对应，因此也无需在第一芯片210或第二芯片220上形成再分布层，工艺简单。进一步的，由于本实施例中第一芯片210和第二芯片220上无需形成再分布层，对第一芯片210和第二芯片220进行减薄处理时，可以将所述第一芯片210和第二芯片220的厚度减到更小，使得封装结构的体积更小。
步骤S103，参考图5，形成第一绝缘层240，所述第一绝缘层240包覆所述第一芯片210并与所述第二芯片220结合，所述第一绝缘层240覆盖所述第一焊盘211和所述第二焊盘221。
本实施例中，所述第一绝缘层240为感光干膜。所述感光干膜为高分子化合物，例如聚酰亚胺、环氧树脂、硅胶或者苯并环丁烯等，在经过紫外线的照射后能够产生聚合反应形成稳定物质附着于第一芯片210和第二芯片220上。本实施例中，采用真空贴膜法形成所述感光干膜，包括：将感光干膜、第一芯片210和第二芯片220的封装体置于真空腔室内；将所述感光干膜覆盖于所述第一芯片210上，将所述第一芯片210包覆起来，并结合至所述第二芯片220第三表面220a上。真空腔室可以确保感光干膜与第一芯片210和第二芯片220之间无气泡，贴合紧密。本实施例中，所述感光干膜覆盖所述第一焊盘211和所述第二焊盘221，且所述第一绝缘层240和所述绝缘胶层230与所述第二芯片220结合面的面积大于所述第一芯片210的面积。
在一些实施例中，所述第一绝缘层240为非感光干膜，类似地，可以采用上述的真空贴膜法形成所述非感光干膜。
在一些实施中，所述第一绝缘层240可以为塑封材料，通过注塑工艺，在相应模具中填充塑封材料，包覆所述第一芯片210，并结合至所述第二芯片220的第三表面220a，经过升温固化后，形成所述第一绝缘层240。
在其他实施例中，所述第一绝缘层240也可以为其他绝缘材料。
本实施例中，所述感光干膜高出于所述第一芯片210的部分的厚度为5～20μm。在其他实施例中，当所述第一绝缘层240采用其他材料时，所述第一绝缘层240的厚度根据其绝缘能力而定，其厚度应当确保不会导致漏电。
在形成第一绝缘层240后，所述第一绝缘层240包覆所述第一芯片210、且覆盖所述第一芯片210在所述第二芯片220上的投影之外的区域，与所述第二芯片220相结合。
与现有技术相比，参考图1，现有技术中第一芯片110和第二芯片120之间通过绝缘胶130结合，绝缘胶130的面积只与第一芯片110的面积相当，导致其结合能力较差。而本实施例中，参考图5，第一芯片210和第二芯片220之间不仅通过绝缘胶层230结合，另外，由于所述第一绝缘层240包覆所述第一芯片210并与所述第二芯片220结合，增强了第一芯片210和第二芯片220之间结合的结构强度，使得第一芯片210不容易从第二芯片220上脱落，增强了整个封装后结构的可靠性。
步骤S104，参考图6，刻蚀所述第一绝缘层240，以分别形成暴露出所述多个第一焊盘211的多个第一开口251和暴露出多个第二焊盘221的多个第二开口252。
在一些实施例中，所述第一绝缘层240为感光干膜，可以采用光刻工艺形成所述第一开口251和第二开口252。具体包括：首先使用紫外光照射所述感光干膜待形成第一开口251和第二开口252区域之外的区域，使其产生聚合反应形成稳定物质，以阻挡后续的刻蚀；接着采用光刻工艺去除未被紫外光照射的感光干膜区域，形成第一开口251，所述第一开口251暴露出所述第一芯片210上的第一焊盘211，同时形成第二开口252，所述第二开口252暴露出所述第二芯片220上的第二焊盘221。
在一些实施例中，所述第一绝缘层240为塑封材料，可以采用激光开孔工艺形成第一开口251和第二开口252。具体包括：将激光作为热源对塑封材料的待开孔区域进行加热，使得待开孔区域快速升温，激光照射区域的塑封材料发生气化，形成对应的第一开口251和第二开口252。在一具体实施例中，所述激光的脉冲宽度为1ns～200ns，脉冲频率为80～200KHz，激光在聚焦点处的能量大于1E18W/cm2。采用激光开孔工艺无需形成掩膜就可以选择性的去除塑封材料，激光开孔时产生的热量只会集中在特定区域，且激光去胶工艺为非接触刻蚀，反应副产物为气态，污染小。
在一些实施例中，所述第一绝缘层240为非感光干膜，类似的，可以采用上述的激光开孔工艺在所述非感光干膜内形成第一开口251和第二开口252。
在一些实施例中，所述第一开口251和所述第二开口252的侧壁可以垂直于所述第二芯片220的表面。在另一些实施例中，所述第一开口251和所述第二开口252的侧壁也可以相对于所述第二芯片220的表面倾斜，使得所述第一开口251和所述第二开口252的顶端的宽度大于低端的宽度，有利于后续形成覆盖所述第一开口251和所述第二开口252底部和侧壁的金属材料层。
需要说明的，所述第一开口251和所述第二开口252也可以不在同一工艺步骤中形成。由于第一芯片210结合在第二芯片220的表面之上，第一芯片210第一表面上的第一焊盘211的高度高于第二芯片220第三表面上的第二焊盘221的高度，因此，在刻蚀所述第一绝缘层240形成暴露出第一焊盘211的第一开口251和暴露出第二焊盘221的第二开口252的过程中，需要刻蚀的第一绝缘层240的厚度不同。所述第一开口251和所述第二开口252在不同工艺步骤中形成，例如，先形成第二开口252再形成第一开口251，可以避免由于对第一绝缘层240的刻蚀厚度不同而对第一焊盘211或第二焊盘221的损伤。
步骤S105，参考图7，形成多个金属互连结构270，所述金属互连结构270覆盖所述第一开口251和所述第二开口252的底部和侧壁、以及部分所述第一绝缘层240的顶表面，所述金属互连结构270与所述第一焊盘211和所述第二焊盘221电学连接。
具体地，首先，采用溅射工艺、化学气相沉积工艺或电镀工艺等形成金属材料层（未图示），所述金属材料层覆盖所述第一开口251和所述第二开口252的底部和侧壁、以及所述第一绝缘层240的顶表面，所述金属材料层为铝、钛、铜或者其他导电材料；接着，采用光刻工艺，在所述金属材料层上形成图形化的光刻胶层（未图示），所述图形化的光刻胶层覆盖所述金属材料层的待形成金属互连结构区域；接着，以所述图形化的光刻胶层为掩膜，刻蚀所述金属材料层，得到图形化金属线路层；然后，去除所述图形化的光刻胶层，剩余的金属材料层构成多个金属互连结构270，所述金属互连结构270用于连接第一焊盘211和第二焊盘221。在一些实施例中，一个第一焊盘211与多个第二焊盘221通过金属互连结构270电学连接。在另外一些实施例中，多个第一焊盘211与一个第二焊盘221通过金属互连结构270电学连接。
步骤S106，参考图8，在所述第一绝缘层240和所述金属互连结构270上形成第二绝缘层280，所述第二绝缘层280具有暴露出部分所述金属互连结构270的第三开口281。
在一些实施例中，所述第二绝缘层280的材料为光刻胶。首先，采用涂胶工艺形成光刻胶层，所述光刻胶层覆盖所述第一绝缘层240和所述金属互连结构270的表面，并填充所述第一开口251和所述第二开口252（参考图7）；接着，采用光刻工艺在所述光刻胶层内形成第三开口281，所述第三开口281暴露出部分所述金属互连结构270。
在其他实施例中，所述第二绝缘层280也可以为感光干膜、非感光干膜、塑封材料或者其他绝缘材料。
步骤S107，参考图9，在所述第三开口281（参考图8）内形成与所述金属互连结构270电学连接的金属凸块290，所述金属凸块290的高度不低于所述第二绝缘层280的顶部。
在一些实施例中，所述金属凸块290为锡球。可以先在所述金属互连结构270上印刷锡膏，再进行高温回流，在表面张力作用下，形成锡球；也可以先在所述金属互连结构270上印刷助焊剂和锡球颗粒，再高温回流形成焊球；还可以在所述金属互连结构270上电镀锡柱，再高温回流形成焊球。
在其他实施例中，所述金属凸块290还可以为铜柱、金柱、锡球、或者铜柱和锡球的结合体等。
与现有技术相比，请继续参考图1，图1所示的现有技术的封装结构中，由于焊球140的直径通常小于所述第一芯片110的厚度，焊球140低于所述第一芯片110，因此，在通过焊球140将该封装结构连接至PCB板时，通常需要在PCB板上需要形成额外的与第一芯片110对应的开孔，以容纳所述第一芯片110，使焊球140与PCB板接触。而本实施例中，参考图10，通过形成第一绝缘层240、金属互连结构270和第二绝缘层280，将金属凸块290转移至第二绝缘层280上，使得金属凸块290高于所述第一芯片210，无需考虑因为金属凸块290的高度小于第一芯片210的厚度而需在PCB板上形成额外的开孔，而可以直接通过金属凸块290将第一芯片210和第二芯片220的封装结构结合至PCB板，简化了工艺。
对应于上述的芯片封装方法，本实施例还提供了一种芯片封装结构，继续参考图9，所述封装结构包括：
第一芯片210，所述第一芯片210包括第一表面（未标示）和与所述第一表面相对的第二表面（未标示），所述第一芯片的第一表面具有多个第一焊盘211；
第二芯片220，所述第二芯片220包括第三表面（未标示）和与所述第三表面相对的第四表面（未标示），所述第二芯片220的第三表面具有多个第二焊盘221，所述第二芯片220的面积大于所述第一芯片210的面积，所述第一芯片210的第二表面与所述第二芯片220的第三表面结合在一起，所述多个第二焊盘221位于所述第一芯片210与所述第二芯片220的结合区域之外；
绝缘胶层230，位于所述第一芯片210的第二表面与所述第二芯片220的第三表面之间；
第一绝缘层240，所述第一绝缘层240包覆所述第一芯片210并与所述第二芯片220结合，所述第一绝缘层240和所述绝缘胶层230与所述第二芯片220结合面的面积大于所述第一芯片210的面积，所述第一绝缘层240具有暴露出所述多个第一焊盘211的多个第一开口（未标示）和暴露出所述多个第二焊盘221的多个第二开口（未标示），所述第一绝缘层240可以为感光干膜、非感光干膜或者塑封材料；
多个金属互连结构270，覆盖所述第一开口和所述第二开口的底部和侧壁、以及部分所述第一绝缘层240的顶表面，与所述第一焊盘211和所述第二焊盘221电学连接；
第二绝缘层280，位于所述第一绝缘层240和所述金属互连结构270上，具有暴露出部分所述金属互连结构270的第三开口（未标示）；
多个金属凸块290，位于所述第三开口内且与所述多个金属互连结构270对应电学连接，所述多个金属凸块290的高度不低于所述第二绝缘层280的顶部。
本发明还提供了另一实施例，请参考图10，图10为本发明另一实施例的芯片封装方法200的流程示意图。下面结合附图对本发明该实施例的芯片封装方法200的步骤进行说明。为了简单明了起见，本实施例中与上一实施例中相同或相似的部分不再详细说明，可参考上一实施例。
步骤S201，参考图11，提供第一芯片310，所述第一芯片310包括第一表面310a和与所述第一表面310a相对的第二表面310b，所述第一芯片310的第一表面310a具有多个第一焊盘311；提供第二芯片320，所述第二芯片320包括第三表面320a和与所述第三表面320a相对的第四表面320b，所述第二芯片320的第三表面320a具有多个第二焊盘321，所述第二芯片320的面积大于第一芯片310的面积。
步骤S202，参考图12，将所述第一芯片310的第二表面310b与所述第二芯片320的第三表面320a相结合，所述多个第二焊盘321位于所述第一芯片310和第二芯片320的结合区域之外。
与上一实施例类似，本实施例中，将所述第一芯片310的第二表面310b与所述第二芯片320相结合，无需在第一芯片310或第二芯片320上形成再分布层，工艺简单。进一步的，可以将所述第一芯片310和第二芯片320的厚度减到更小，使得封装结构的体积更小。
步骤S203，参考图13，形成第一绝缘层340，所述第一绝缘层340包覆所述第一芯片310并与所述第二芯片320结合，所述第一绝缘层340覆盖所述第一焊盘311和所述第二焊盘321。
与上一实施例类似，本实施例中，第一芯片310和第二芯片320之间不仅通过绝缘胶层330结合，另外，由于所述第一绝缘层340包覆所述第一芯片310并与所述第二芯片320结合，增强了第一芯片310和第二芯片320之间结合的结构强度，使得第一芯片310不容易从第二芯片320上脱落，增强了整个封装后结构的可靠性。
步骤S204，参考图14，刻蚀所述第一绝缘层340，以分别形成暴露出所述多个第一焊盘311的多个第一开口351和暴露出多个第二焊盘321的多个第二开口352。
步骤S205，参考图15，在所述第一开口351（参考图14）内形成第一插塞361，在所述第二开口352（参考图14）内形成第二插塞362。
在一些实施例中，所述第一插塞361和第二插塞362的材料为锡，采用真空印锡工艺形成。在真空环境下，将锡膏通过印刷方式填至第一开口351和第二开口352中，使得锡膏充分填满所述第一开口351和所述第二开口352而不留下缝隙；位于所述第一开口351内的锡膏构成第一插塞361，位于所述第二开口352内的锡膏构成第二插塞362。由于所述第一开口351和第二开口352分别暴露出所述第一焊盘311和第二焊盘321，因此在形成所述第一插塞361和第二插塞362后，所述第一插塞361与所述第一焊盘311电学连接，所述第二插塞362与所述第二焊盘321电学连接，且所述第一绝缘层340暴露出所述第一插塞361和所述第二插塞362的顶表面。
在另外一些实施例中，所述第一插塞361和第二插塞362的材料还可以为铜或者其他金属材料。
步骤S206，参考图16，在所述第一绝缘层340上形成多个金属互连结构370，所述金属互连结构370与所述第一插塞361和所述第二插塞262电学连接。
具体地，在所述第一绝缘层340上通过溅射工艺形成金属材料层（未图示），所述金属材料层为铝、钛、铜或者其他导电材料，所述金属材料层覆盖所述第一插塞361和第二插塞362；在所述金属材料层上形成图形化的光刻胶层（未图示），所述图形化的光刻胶层覆盖所述金属材料层的待形成金属互连结构区域；以所述图形化的光刻胶层为掩膜，刻蚀所述金属材料层，直至暴露出所述第一绝缘层340；去除所述图形化的光刻胶层，剩余的金属材料层构成多个金属互连结构370，所述金属互连结构370用于连接第一插塞361和第二插塞362。在一些实施例中，一个第一插塞361与多个第二插塞362通过金属互连结构370电学连接。在另外一些实施例中，多个第一插塞361与一个第二插塞362通过金属互连结构370电学连接。
步骤S207，参考图17，在所述第一绝缘层340和所述金属互连结构370上形成第二绝缘层380，所述第二绝缘层380具有暴露出部分金属互连结构370的第三开口381。
步骤S208，参考图18，在所述第三开口381（参考图17）内形成与所述金属互连结构370电学连接的金属凸块390，所述金属凸块390的高度不低于所述第二绝缘层380的顶部。
与现有技术相比，本实施例中，通过形成第一绝缘层340、第二绝缘层380、第一插塞361、第二插塞362和金属互连结构370，将金属凸块390转移至第二绝缘层380上，使得金属凸块390高于所述第一芯片310，无需考虑因为金属凸块390的高度小于第一芯片310的厚度而需在PCB板上形成额外的开孔，而可以直接通过金属凸块390将第一芯片310和第二芯片320的封装结构结合至PCB板，简化了工艺。
对应于上述的芯片封装方法，本实施例还提供了一种芯片封装结构，继续参考图18，所述封装结构包括：
第一芯片310，所述第一芯片310包括第一表面（未标示）和与所述第一表面相对的第二表面（未标示），所述第一芯片的第一表面具有多个第一焊盘311；
第二芯片320，所述第二芯片320包括第三表面（未标示）和与所述第三表面相对的第四表面（未标示），所述第二芯片320的第三表面具有多个第二焊盘321，所述第二芯片320的面积大于所述第一芯片310的面积，所述第一芯片310的第二表面与所述第二芯片320的第三表面结合在一起，所述多个第二焊盘321位于所述第一芯片310与所述第二芯片320的结合区域之外；
绝缘胶层330，位于所述第一芯片310的第二表面与所述第二芯片320的第三表面之间；
第一绝缘层340，所述第一绝缘层340包覆所述第一芯片310并与所述第二芯片320结合，所述第一绝缘层340和所述绝缘胶层330与所述第二芯片320结合面的面积大于所述第一芯片310的面积，所述第一绝缘层340具有暴露出所述多个第一焊盘311的多个第一开口（未标示）和暴露出所述多个第二焊盘321的多个第二开口（未标示），所述第一绝缘层340可以为感光干膜、非感光干膜或者塑封材料；
多个第一插塞361，位于所述多个第一开口内，分别与所述多个第一焊盘311对应电学连接；
多个第二插塞362，位于所述多个第二开口内，分别与所述多个第二焊盘321对应电学连接；
多个金属互连结构370，位于所述第一绝缘层340上，与所述第一插塞361和所述第二插塞362电学连接；
第二绝缘层380，位于所述第一绝缘层340和所述多个金属互连结构370上，具有暴露出部分所述金属互连结构370的第三开口（未标示）；
多个金属凸块390，位于所述第三开口内且与所述多个金属互连结构370对应电学连接，所述多个金属凸块390的高度不低于所述第二绝缘层380的顶部。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (17)

1.一种芯片封装方法，其特征在于，包括：
提供第一芯片，所述第一芯片包括第一表面和与所述第一表面相对的第二表面，所述第一芯片的第一表面具有多个第一焊盘；
提供第二芯片，所述第二芯片包括第三表面和与所述第三表面相对的第四表面，所述第二芯片的第三表面具有多个第二焊盘，所述第二芯片的面积大于第一芯片的面积；
将所述第一芯片的第二表面与所述第二芯片的第三表面相结合，所述多个第二焊盘位于所述第一芯片和第二芯片的结合区域之外；
形成第一绝缘层，所述第一绝缘层包覆所述第一芯片并与所述第二芯片结合。
2.如权利要求1所述的芯片封装方法，其特征在于，所述第一芯片的第二表面与所述第二芯片的第三表面通过绝缘胶层结合。
3.如权利要求2所述的芯片封装方法，其特征在于，所述第一绝缘层和所述绝缘胶层与所述第二芯片结合面的面积大于所述第一芯片的面积。
4.如权利要求1所述的芯片封装方法，其特征在于，所述第一绝缘层为感光干膜、非感光干膜或者塑封材料。
5.如权利要求1所述的芯片封装方法，其特征在于，所述第一绝缘层覆盖所述第一焊盘和所述第二焊盘。
6.如权利要求5所述的芯片封装方法，其特征在于，还包括：
刻蚀所述第一绝缘层，分别形成暴露出所述多个第一焊盘的多个第一开口和暴露出所述多个第二焊盘的多个第二开口。
7.如权利要求6所述的芯片封装方法，其特征在于，还包括：
形成多个金属互连结构，所述金属互连结构覆盖所述第一开口和所述第二开口的底部和侧壁、以及部分所述第一绝缘层的顶表面，所述金属互连结构与所述第一焊盘和所述第二焊盘电学连接。
8.如权利要求6所述的芯片封装方法，其特征在于，还包括：
在所述第一开口内形成第一插塞；
在所述第二开口内形成第二插塞；
在所述第一绝缘层上形成多个金属互连结构，所述金属互连结构与所述第一插塞和所述第二插塞电学连接。
9.如权利要求7或8所述的芯片封装方法，其特征在于，还包括：
在所述第一绝缘层和所述金属互连结构上形成第二绝缘层，所述第二绝缘层具有暴露出部分所述金属互连结构的第三开口；
在所述第三开口内形成与所述金属互连结构电学连接的金属凸块，所述金属凸块的高度不低于所述第二绝缘层的顶部。
10.一种芯片封装结构，其特征在于，包括：
第一芯片，所述第一芯片包括第一表面和与所述第一表面相对的第二表面，所述第一芯片的第一表面具有多个第一焊盘；
第二芯片，所述第二芯片包括第三表面和与所述第三表面相对的第四表面，所述第二芯片的第三表面具有多个第二焊盘，所述第二芯片的面积大于所述第一芯片的面积，所述第一芯片的第二表面与所述第二芯片的第三表面结合在一起，所述多个第二焊盘位于所述第一芯片与所述第二芯片的结合区域之外；
第一绝缘层，所述第一绝缘层包覆所述第一芯片并与所述第二芯片结合。
11.如权利要求10所述的芯片封装结构，其特征在于，还包括：绝缘胶层，位于所述第一芯片的第二表面与所述第二芯片的第三表面之间。
12.如权利要求11所述的芯片封装结构，其特征在于，所述第一绝缘层和所述绝缘胶层与所述第二芯片结合面的面积大于所述第一芯片的面积。
13.如权利要求10所述的芯片封装结构，其特征在于，所述第一绝缘层为感光干膜、非感光干膜或者塑封材料。
14.如权利要求10所述的芯片封装结构，其特征在于，所述第一绝缘层具有暴露出所述多个第一焊盘的多个第一开口和暴露出所述多个第二焊盘的多个第二开口。
15.如权利要求14所述的芯片封装结构，其特征在于，还包括：多个金属互连结构，覆盖所述第一开口和所述第二开口的底部和侧壁、以及部分所述第一绝缘层的顶表面，与所述第一焊盘和所述第二焊盘电学连接。
16.如权利要求14所述的芯片封装结构，其特征在于，还包括：
多个第一插塞，位于所述多个第一开口内，分别与所述多个第一焊盘对应电学连接；
多个第二插塞，位于所述多个第二开口内，分别与所述多个第二焊盘对应电学连接；
多个金属互连结构，位于所述第一绝缘层上，与所述第一插塞和所述第二插塞电学连接。
17.如权利要求15或16所述的芯片封装结构，其特征在于，还包括：
第二绝缘层，位于所述第一绝缘层和所述金属互连结构上，具有暴露出部分所述金属互连结构的第三开口；
多个金属凸块，位于所述第三开口内且与所述多个金属互连结构对应电学连接，所述多个金属凸块的高度不低于所述第二绝缘层的顶部。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392975A (zh) * 2014-12-16 2015-03-04 南通富士通微电子股份有限公司 扇出晶圆封装结构
CN104465505A (zh) * 2014-12-16 2015-03-25 南通富士通微电子股份有限公司 扇出晶圆封装方法
CN104835808A (zh) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 芯片封装方法及芯片封装结构
CN107799424A (zh) * 2016-09-07 2018-03-13 恒劲科技股份有限公司 内埋式线路封装的方法
CN110783327A (zh) * 2019-10-24 2020-02-11 中芯集成电路（宁波）有限公司 晶圆级系统封装方法及封装结构
CN111146099A (zh) * 2019-12-31 2020-05-12 中芯集成电路（宁波）有限公司 半导体结构及其制作方法
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
DE102021107982B4 (de) 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10720415B2 (en) * 2016-11-01 2020-07-21 Innolux Corporation Display device and method for forming the same
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10910344B2 (en) * 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11121111B2 (en) * 2019-09-09 2021-09-14 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
KR102543996B1 (ko) * 2019-09-20 2023-06-16 주식회사 네패스 반도체 패키지 및 이의 제조방법
US11205630B2 (en) 2019-09-27 2021-12-21 Intel Corporation Vias in composite IC chip structures
US11094672B2 (en) 2019-09-27 2021-08-17 Intel Corporation Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
CN114649286B (zh) * 2022-05-19 2022-09-27 甬矽电子(宁波)股份有限公司 扇出型封装结构和扇出型封装方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW455962B (en) * 2000-01-28 2001-09-21 Fujitsu Ltd Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
JP2001298149A (ja) * 2000-04-14 2001-10-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US20010038151A1 (en) * 2000-03-09 2001-11-08 Yoshikazu Takahashi Semiconductor device and the method for manufacturing the same
CN1527415A (zh) * 2003-03-06 2004-09-08 ���µ�����ҵ��ʽ���� 薄膜压电元件及其制造方法与执行元件
CN1677634A (zh) * 2004-03-29 2005-10-05 三洋电机株式会社 半导体装置及其制造方法
CN101651122A (zh) * 2008-08-15 2010-02-17 财团法人工业技术研究院 立体导通结构及其制造方法
US7825520B1 (en) * 2006-11-16 2010-11-02 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
CN101877349A (zh) * 2009-04-30 2010-11-03 三洋电机株式会社 半导体模块及便携式设备
CN102097427A (zh) * 2009-11-10 2011-06-15 英飞凌科技股份有限公司 层叠型电子器件
CN102810484A (zh) * 2011-05-30 2012-12-05 拉碧斯半导体株式会社 半导体装置的制造方法及半导体装置
CN203746825U (zh) * 2014-01-16 2014-07-30 苏州晶方半导体科技股份有限公司 芯片封装结构

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001042893A1 (fr) * 1999-12-10 2001-06-14 Hitachi, Ltd Module semi-conducteur
US20110316117A1 (en) * 2007-08-14 2011-12-29 Agency For Science, Technology And Research Die package and a method for manufacturing the die package
US8304917B2 (en) * 2009-12-03 2012-11-06 Powertech Technology Inc. Multi-chip stacked package and its mother chip to save interposer
US8895440B2 (en) * 2010-08-06 2014-11-25 Stats Chippac, Ltd. Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV
US8476720B2 (en) * 2011-06-29 2013-07-02 Honeywell International Inc. Systems and methods for vertically stacking a sensor on an integrated circuit chip
US8916481B2 (en) * 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
JP5977051B2 (ja) * 2012-03-21 2016-08-24 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
TWI500135B (zh) * 2012-12-10 2015-09-11 Ind Tech Res Inst 堆疊式功率元件模組
US9446943B2 (en) * 2013-05-31 2016-09-20 Stmicroelectronics S.R.L. Wafer-level packaging of integrated devices, and manufacturing method thereof
US8912663B1 (en) * 2013-06-28 2014-12-16 Delta Electronics, Inc. Embedded package structure and method for manufacturing thereof
WO2014209404A1 (en) * 2013-06-29 2014-12-31 Intel Corporation Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
US9159671B2 (en) * 2013-11-19 2015-10-13 International Business Machines Corporation Copper wire and dielectric with air gaps
US11018025B2 (en) * 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW455962B (en) * 2000-01-28 2001-09-21 Fujitsu Ltd Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
US20010038151A1 (en) * 2000-03-09 2001-11-08 Yoshikazu Takahashi Semiconductor device and the method for manufacturing the same
JP2001298149A (ja) * 2000-04-14 2001-10-26 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
CN1527415A (zh) * 2003-03-06 2004-09-08 ���µ�����ҵ��ʽ���� 薄膜压电元件及其制造方法与执行元件
CN1677634A (zh) * 2004-03-29 2005-10-05 三洋电机株式会社 半导体装置及其制造方法
US7825520B1 (en) * 2006-11-16 2010-11-02 Amkor Technology, Inc. Stacked redistribution layer (RDL) die assembly package
CN101651122A (zh) * 2008-08-15 2010-02-17 财团法人工业技术研究院 立体导通结构及其制造方法
CN101877349A (zh) * 2009-04-30 2010-11-03 三洋电机株式会社 半导体模块及便携式设备
CN102097427A (zh) * 2009-11-10 2011-06-15 英飞凌科技股份有限公司 层叠型电子器件
CN102810484A (zh) * 2011-05-30 2012-12-05 拉碧斯半导体株式会社 半导体装置的制造方法及半导体装置
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104392975A (zh) * 2014-12-16 2015-03-04 南通富士通微电子股份有限公司 扇出晶圆封装结构
CN104465505A (zh) * 2014-12-16 2015-03-25 南通富士通微电子股份有限公司 扇出晶圆封装方法
CN104835808A (zh) * 2015-03-16 2015-08-12 苏州晶方半导体科技股份有限公司 芯片封装方法及芯片封装结构
US10276540B2 (en) 2015-03-16 2019-04-30 China Wafer Level Csp Co., Ltd. Chip packaging method and chip packaging structure
CN107799424A (zh) * 2016-09-07 2018-03-13 恒劲科技股份有限公司 内埋式线路封装的方法
CN110783327A (zh) * 2019-10-24 2020-02-11 中芯集成电路（宁波）有限公司 晶圆级系统封装方法及封装结构
CN111146099A (zh) * 2019-12-31 2020-05-12 中芯集成电路（宁波）有限公司 半导体结构及其制作方法
CN111146099B (zh) * 2019-12-31 2021-12-24 中芯集成电路（宁波）有限公司 半导体结构及其制作方法
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
DE102021107982B4 (de) 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur

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