CN102810484A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN102810484A
CN102810484A CN2012101725979A CN201210172597A CN102810484A CN 102810484 A CN102810484 A CN 102810484A CN 2012101725979 A CN2012101725979 A CN 2012101725979A CN 201210172597 A CN201210172597 A CN 201210172597A CN 102810484 A CN102810484 A CN 102810484A
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dielectric film
semiconductor chip
peristome
semiconductor device
semiconductor
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齐藤弘和
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Lapis Semiconductor Co Ltd
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Abstract

本发明涉及半导体装置的制造方法及半导体装置，提供一种半导体装置的制造方法，抑制搭载半导体芯片的基板的结晶缺陷，并且缩短制造时间。在本实施方式的半导体装置（101）（其制造方法）中，经过如下工序之后，在该状态下在第二绝缘膜（16）上形成布线结构（26）：在基板（例如第一半导体芯片（10））上形成第一绝缘膜（14）的工序，在第一绝缘膜（14）形成开口部（14B）的工序，在第一绝缘膜（14）的开口部内搭载第二半导体芯片（12）的工序，以及跨越在第二半导体芯片（12）上和第一绝缘膜（14）上形成第二绝缘膜（16）的工序。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明涉及半导体装置的制造方法及半导体装置。
背景技术
历来，例如被称为多片式WCSP（Wafer Level Chip Size Package，晶片级芯片尺寸封装件）等的半导体装置是在基板固定半导体芯片后形成布线结构来制作的。
作为半导体芯片对该基板的固定方法，已知通过薄膜（film）粘贴并固定半导体芯片的方法（参照专利文献1~3等）。
此外，作为其它的固定方法，也已知在对基板进行蚀刻之后，通过薄膜粘贴并固定半导体芯片的方法（参照专利文献4等）。
专利文献
专利文献1：日本特开2007-103714号公报；
专利文献2：日本特开2007-103715号公报；
专利文献3：日本特开2007-103716号公报；
专利文献4：日本特开2004-186497号公报。
可是，在现有的半导体芯片的固定方法中，现状是因为通过薄膜的粘贴来将半导体芯片固定在基板，所以需要长时间的热处理，此外需要对每个半导体芯片粘合薄膜，招致制造时间的巨大的增加。
此外，在将半导体芯片固定在基板时，当对基板施加蚀刻时制造时间进一步增加，并且招致基板的结晶缺陷的可能性变高。
发明内容
因此，本发明的课题在于提供一种半导体装置的制造方法，抑制搭载半导体芯片的基板的结晶缺陷，并且缩短了制造时间。
此外，本发明的课题在于提供一种半导体装置，抑制了搭载半导体芯片的基板的结晶缺陷。
上述课题通过以下的方案来解决。即，
本发明的半导体装置的制造方法至少具有：
在基板上形成第一绝缘膜的工序；
在所述第一绝缘膜形成开口部的工序；
在所述第一绝缘膜的所述开口部内搭载半导体芯片的工序；
跨越在所述半导体芯片上和所述第一绝缘膜上，形成第二绝缘膜的工序；以及
在所述第二绝缘膜上形成与所述半导体芯片电连接的布线结构的工序。
本发明的半导体装置至少具备：
基板；
第一绝缘膜，设置在所述基板上，具有开口部；
半导体芯片，搭载在所述第一绝缘膜的所述开口部内；
第二绝缘膜，跨越在所述半导体芯片上和所述第一绝缘膜上而设置；以及
布线结构，设置在所述第二绝缘膜上，与所述半导体芯片电连接。
根据本发明，能够提供一种半导体装置的制造方法，抑制搭载半导体芯片的基板的结晶缺陷，并且缩短了制造时间。
根据本发明，能够提供一种半导体装置，抑制了搭载半导体芯片的基板的结晶缺陷。
附图说明
图1是表示本实施方式的半导体装置的概略剖面图。
图2是表示本实施方式的半导体装置的制造方法的工序图。
图3是表示本实施方式的半导体装置的制造方法的工序图。
图4是表示在本实施方式的半导体装置中，在第一绝缘膜的开口部内搭载有半导体芯片的样子的平面图。
图5是表示在本实施方式的半导体装置的制造方法中，进行用于形成布线的电镀处理的样子的示意图。
图6是表示另一本实施方式的半导体装置的概略剖面图。
具体实施方式
以下，针对作为本发明的一例的实施方式，一边参照附图一边进行说明。
图1是表示本实施方式的半导体装置的概略剖面图。
本实施方式的半导体装置101例如如图1所示，具备：第一半导体芯片10、以及在第一半导体芯片10上搭载的第二半导体芯片12。
在第一半导体芯片10中例如设置有集成电路（未图示），与其电连接的焊盘电极10A设置于主面。而且，在第一半导体芯片10的主面，例如以露出焊盘电极10A的方式设置有保护膜（未图示）。
在第二半导体芯片12中也同样地，例如设置有集成电路（未图示），与其电连接的焊盘电极12A设置于主面。而且，在第二半导体芯片12的主面，例如以露出焊盘电极12A的方式设置有保护膜（未图示）。
而且，本实施方式的半导体装置101具备：第一半导体芯片10，在第一半导体芯片10上设置的具有开口部14B的第一绝缘膜14，在第一绝缘膜14的开口部14B内搭载的第二半导体芯片12，以及跨越在第二半导体芯片12上和第一绝缘膜14上而设置的第二绝缘膜16。
第一绝缘膜14的开口部14B被设置成其开口的大小比搭载的第二半导体芯片12的芯片尺寸大。而且，第二绝缘膜16以埋入到构成第一绝缘膜14的开口部14B的壁面和第二半导体芯片12的侧面的间隙中的方式而设置。
在第二绝缘膜16上，具备与第一半导体芯片10和第二半导体芯片12电连接的布线结构26。
布线结构26具有：通过设置在第一绝缘膜14及第二绝缘膜16的接触孔14A与第一半导体芯片10的焊盘电极10A电连接的布线18A，以及在布线18A的一部分上设置的与布线18A的一部分电连接的柱（post）电极20A。
此外，布线结构26具有：通过设置在第二绝缘膜16的接触孔16A与第二半导体芯片12的焊盘电极12A电连接的布线18B，以及在布线18B的一部分上设置的与布线18B的一部分电连接的柱电极20B。
而且，布线18A及布线18B介于第二绝缘膜16和层间绝缘膜22之间而设置。柱电极20A及柱电极20B以被层间绝缘膜22覆盖，并且顶面从层间绝缘膜22露出的方式而设置。
在布线结构26（其布线）设置有电连接的外部连接端子24A及外部连接端子24B。
具体地，外部连接端子24A例如设置在布线结构26的柱电极20A的顶面上。由此，谋求外部连接端子24A通过布线结构26的布线18A及柱电极20A，与第一半导体芯片10的焊盘电极10A电连接。
另一方面，外部连接端子24B例如设置在布线结构26的柱电极20B的顶面上。由此，谋求外部连接端子24B通过布线结构26的布线18B及柱电极20B，与第二半导体芯片12的焊盘电极12A电连接。
以下，针对本实施方式的半导体装置101的细节和本实施方式的半导体装置101的制造方法进行说明。
图2~图3是表示本实施方式的半导体装置的制造方法的工序图。
在本实施方式的半导体装置101的制造方法中，首先如图2（A）所示，以通过单片化而成为第一半导体芯片10的方式，准备按多个第一半导体芯片的每一个集成有焊盘电极10A、集成电路等的晶片10B。
接着，如图2（B）所示，在晶片10B上形成第一绝缘膜14。
具体地，例如根据第一绝缘膜14的材料种类，利用旋涂（spin coat）法、印刷法、CVD（化学气相生长）法、溅射法等在晶片10B上形成第一绝缘膜14。
作为第一绝缘膜14，可以是树脂膜（例如聚酰亚胺树脂、有机硅改性聚酰亚胺树脂、环氧树脂、BCB树脂、PBO树脂等）、无机膜（例如硅氧化膜、硅氮化膜）的任一种，但从成膜容易性、加工性（开口形成容易性）的观点出发，优选是感光性的树脂膜。
特别是从通用性、加工性的观点出发，作为第一绝缘膜14优选是聚酰亚胺树脂膜（特别是感光性的聚酰亚胺树脂膜）。
第一绝缘膜14可以形成为与第二半导体芯片12的厚度同等，也可以形成为比第二半导体芯片12薄或厚。在本实施方式中，示出以与第二半导体芯片12的厚度同等的厚度来形成第一绝缘膜14的方式。
再有，从第二半导体芯片12的操作性（后述的在第一绝缘膜14的开口部14B内搭载第二半导体芯片12时的搬送性）的观点出发，优选第一绝缘膜14比第二半导体芯片12形成得薄。
接着，如图2（C）所示，在第一绝缘膜14形成开口部14B。
具体地，例如根据第一绝缘膜14的材料种类，利用光刻（lithography）法、干法蚀刻法，在第一绝缘膜14形成开口部14B。
开口部14B例如以与第二半导体芯片12相同形状（从第二半导体芯片12主面侧观察的形状是相同形状）并且比第二半导体芯片12的大小（芯片尺寸）大一圈的方式，形成在第一绝缘膜14（参照图4）。
而且，开口部14B例如以使晶片10B（第一半导体芯片10）的表面露出的方式，即以贯通第一绝缘膜14、到达晶片10B（第一半导体芯片10）的表面的方式而形成。
再有，虽然示出了开口部14B贯通第一绝缘膜14而形成的方式，但也可以是非贯通的开口部。也就是说，开口部14B以不露出晶片10B（第一半导体芯片10）的表面（主面）的方式在第一绝缘膜14设置成凹部状也可。该情况下的开口部14B的深度也与第二半导体芯片12的厚度同等也可，比第二半导体芯片12的厚度浅或深也可。
但是，从第二半导体芯片12的操作性（后述的在第一绝缘膜14的开口部14B内搭载第二半导体芯片12时的搬送性）的观点出发，优选开口部14B比第二半导体芯片12形成得浅。
接着，如图2（D）所示，在第一绝缘膜14的开口部14B内搭载第二半导体芯片12。
具体地，例如以使设置有焊盘电极12A的主面的相反侧的面与晶片10B（第一半导体芯片10）相向的方式，在第一绝缘膜14的开口部14B内搭载第二半导体芯片12（参照图4）。
接着，如图3（E）所示，跨越在第二半导体芯片12上和第一绝缘膜14上形成第二绝缘膜16。
具体地，例如根据第二绝缘膜16的材料种类，利用旋涂法、印刷法、CVD（化学气相生长）法、溅射法等形成第二绝缘膜16。
第二绝缘膜16例如以覆盖第二半导体芯片12及第一绝缘膜14，并且埋入到构成第一绝缘膜14的开口部14B的壁面和第二半导体芯片12的侧面的间隙中的方式而形成。
作为第二绝缘膜16，可以是树脂膜（例如聚酰亚胺树脂、有机硅改性聚酰亚胺树脂、环氧树脂、BCB树脂、PBO树脂等）、无机膜（例如硅氧化膜、硅氮化膜）的任一种，但从成膜容易性、加工性（开口形成容易性）的观点出发，优选是感光性的树脂膜。
特别是从通用性、加工性的观点出发，作为第二绝缘膜16优选是聚酰亚胺树脂膜（特别是感光性的聚酰亚胺树脂膜）。
接着，如图3（F）所示，在第二绝缘膜上形成与第一半导体芯片10和第二半导体芯片12电连接的布线结构26。
具体地，例如首先根据第一绝缘膜14及第二绝缘膜16的材料种类，利用光刻（photolithography）法、干法蚀刻法，在第一绝缘膜14及第二绝缘膜16形成接触孔14A，该接触孔14A获得用于谋求与第一半导体芯片10的焊盘电极10A电连接的接触。
同样地，例如利用光刻法、干法蚀刻法，在第二绝缘膜16形成接触孔16A，该接触孔16A获得用于谋求与第二半导体芯片12的焊盘电极12A电连接的接触。
接着，例如利用电镀法来埋入接触孔14A，谋求与晶片10B（第一半导体芯片10）的焊盘电极10A电连接，并且在第一绝缘膜14上形成布线18A（例如钨（W）、铜（Cu）、铝（Al）等的层）。
同样地，例如利用电镀法来埋入接触孔16A，谋求与第二半导体芯片12的焊盘电极12A电连接，并且在第二绝缘膜16上形成布线18B（例如钨（W）、铜（Cu）、铝（Al）等的层）。
再有，布线18A及布线18B不需要完全埋入各接触孔，只要以谋求在各接触孔的底部与各焊盘电极的电连接的方式形成即可。
在这里，布线18A及布线18B例如在使晶片10B（第一半导体芯片10）的搭载有第二半导体芯片12的面侧朝向重力方向的状态下通过电镀处理而形成。
也就是说，布线18A及布线18B例如在使晶片10B（第一半导体芯片10）的搭载有第二半导体芯片12的面侧朝向重力方向的状态下，将在晶片10B（第一半导体芯片10）形成的第一绝缘膜14及第二绝缘膜16浸入电镀液28，进行电镀处理而形成（参照图5）。
再有，本电镀处理也可以在使晶片10B（第一半导体芯片10）的搭载有第二半导体芯片12的面侧朝向与重力方向相反的方向（上方）的状态下来进行。
再有，虽然没有图示，但优选在第二绝缘膜16上的至少布线18A及布线18B形成区域、构成各接触孔的壁面、以及从该各接触孔露出的各焊盘电极，在电镀处理前，利用溅射法等形成用于促进布线18A及布线18B的电镀生长的晶种（seed）膜（例如Ti/N膜、Ti/Cu膜等）。
接着，例如利用电镀法、溅射法等，在谋求与布线18A的一部分电连接的同时形成柱电极20A（例如以钨（W）、铜（Cu）、铝（Al）等构成的柱状电极）。
同样地，例如利用电镀法、溅射法等，在谋求与布线18B的一部分电连接的同时形成柱电极20B（例如以钨（W）、铜（Cu）、铝（Al）等构成的柱状电极）。
接着，例如根据层间绝缘膜22的材料种类，利用旋涂法、印刷法、CVD（化学气相生长）法、溅射法等，在第二绝缘膜16上以覆盖布线18A及布线18B和柱电极20A及柱电极20B的方式形成层间绝缘膜22。然后，根据需要以露出柱电极20A及柱电极20B的顶面的方式对层间绝缘膜22的表面施加切削处理。
这样，依次形成布线18A、布线18B、柱电极20A、柱电极20B、层间绝缘膜22，在第二绝缘膜16上形成布线结构26。
再有，布线结构26不限于这些结构，也可以是多层布线结构等的周知的布线结构。
接着，如图3（G）所示，例如在布线结构26上形成外部连接端子24A及外部连接端子24B。
具体地，通过焊料球、焊料膏的焊接，在布线结构26的柱电极20A及柱电极20B的顶面（从层间绝缘膜22露出的面）分别形成外部连接端子24A及外部连接端子24B。由此，谋求通过布线结构26的布线及柱电极，与各半导体芯片的电连接。
之后，例如根据需要通过晶片磨背机（back grinder）使镜片10B薄膜化后，通过切割进行单片化。
经过以上的结构，制造本实施方式的半导体装置101。
在以上说明的本实施方式的半导体装置101（其制造方法）中，通过经过如下工序进行制作，从而在晶片10B（第一半导体芯片10）上设置的第一绝缘膜14的开口部14B内搭载有第二半导体芯片12的状态下，被第二绝缘膜16固定化：在作为搭载半导体芯片（在本实施方式中是第二半导体芯片12）的基板的晶片10B（第一半导体芯片10）上形成第一绝缘膜14的工序，在第一绝缘膜14形成开口部14B的工序，在第一绝缘膜14的开口部内搭载第二半导体芯片12的工序，跨越在第二半导体芯片12上和第一绝缘膜14上形成第二绝缘膜16的工序。
而且，在该状态下在第二绝缘膜16上形成有布线结构26。
因此，第二半导体芯片12不使用粘接膜或对晶片10B（第一半导体芯片10）进行蚀刻，就能够在晶片10B（第一半导体芯片10）固定化。
因此，在本实施方式的半导体装置101（其制造方法）中，抑制搭载半导体芯片（在本实施方式中是第二半导体芯片12）的基板（在本实施方式中是第一半导体芯片10）的结晶缺陷，并且缩短制造时间，获得半导体装置101。
特别是在制造在第一半导体芯片10上搭载有第二半导体芯片12的WCSP时，不会伴随着在将第二半导体芯片12搭载于第一半导体芯片10时的制造位置对准部的工序的大幅增加。
此外，因为获得的半导体装置101不对第一半导体芯片10施加蚀刻，所以搭载半导体芯片的第一半导体芯片10的结晶缺陷被抑制。这是因为当对第二半导体芯片12使用粘接薄膜或进行晶片10B（第一半导体芯片10）的蚀刻时，对晶片10B（第一半导体芯片10）的负荷增加，发生结晶缺陷的概率上升，但在本实施方式中，不进行这些处理，难以对晶片10B（第一半导体芯片10）施加负荷。
在本实施方式的半导体装置101（其制造方法）中，将第一绝缘膜14的开口部14B形成得比第二半导体芯片12的芯片尺寸大，以埋入到构成第一绝缘膜14的开口部14B的壁面与第二半导体芯片12的侧面的间隙的方式形成第二绝缘膜16。
在本实施方式的半导体装置101（其制造方法）中，以露出第一半导体芯片10的表面的方式在第一绝缘膜14形成有开口部14B。
因此，第二半导体芯片12搭载于平面性优越的第一半导体芯片10的表面上，因此对第一半导体芯片10的表面没有倾斜地搭载第二半导体芯片12，连接不良等的故障的产生被抑制。
此外，也有不需要使第一绝缘膜14厚膜化到需要程度以上的优点。
在本实施方式的半导体装置101（其制造方法）中，在形成布线结构26时，例如在使第一半导体芯片10的搭载有第二半导体芯片12的面侧朝向重力方向的状态下通过电镀处理形成布线18A及布线18B。
因为在本状态下进行电镀处理，第二半导体芯片12也通过第二绝缘膜16而被固定化，所以不会发生第二半导体芯片12的落下、位置偏移。
此外，当第二半导体芯片12通过第二绝缘膜16被固定化时，在本电镀处理之外，例如在第二绝缘膜16形成接触孔16A时，能抑制接触孔16A和第二半导体芯片12（其焊盘电极12A）的偏移产生、或者在第二绝缘膜16形成后对晶片10B（第一半导体芯片10）搬送时，也能抑制其物理冲击等导致的第二半导体芯片12的位置偏移的产生。
在本实施方式的半导体装置101（其制造方法）中，当作为第一绝缘膜14及第二绝缘膜16而应用感光性的聚酰亚胺树脂膜时，由于聚酰亚胺树脂膜的通用性、加工性高，所以在低成本化的同时，第一绝缘膜14的开口部14B、第二绝缘膜16的接触孔16A的形成精度提高。例如，如果第一绝缘膜14的开口部14B的形成精度变高的话，则第二半导体芯片12的搭载精度也变高。
再有，虽然在本实施方式的半导体装置101（其制造方法）中，说明了以露出第一半导体芯片10的表面的方式在第一绝缘膜14形成有开口部14B的方式，但并不限定于此，例如也可以是如图6所示那样，以不露出第一半导体芯片10的表面的方式，在第一绝缘膜14形成有开口部14B的方式（也就是，以不贯通第一绝缘膜14的方式形成开口部14B的方式）。
在本方式的情况下，如果作为第一绝缘膜14应用树脂膜（特别是具有粘接性的树脂膜：例如感光性的聚酰亚胺树脂膜等）的话，由于开口部14B底面以具有粘接性的树脂面构成，所以在第一绝缘膜14的开口部14B内搭载有第二半导体芯片12时，与开口部14B的底面的贴紧性提高，第二半导体芯片12的位置偏移被抑制。
此外，在本实施方式的半导体装置101（其制造方法）中，说明了作为搭载第二半导体芯片12的基板而采用第一半导体芯片10的方式，但并不限定于此，本基板例如也可以是没有设置集成电路的半导体基板（例如硅基板等）、其它金属基板。
此外，本实施方式不被限定地解释，显然，在满足本发明的必要条件的范围内能够实现。
附图标记说明
10 第一半导体芯片；
10A 焊盘电极；
10B 晶片；
12 第二半导体芯片；
12A 焊盘电极；
14 第一绝缘膜；
14A 接触孔；
14B 开口部；
16 第二绝缘膜；
16A 接触孔；
18A、18B 布线；
20A、20B 柱电极；
22 层间绝缘膜
24A、24B 外部连接端子；
26 布线结构；
28 电镀液；
101 半导体装置。

Claims (7)

1.一种半导体装置的制造方法，其中，至少具有：
在基板上形成第一绝缘膜的工序；
在所述第一绝缘膜形成开口部的工序；
在所述第一绝缘膜的所述开口部内搭载半导体芯片的工序；
跨越在所述半导体芯片上和所述第一绝缘膜上，形成第二绝缘膜的工序；以及
在所述第二绝缘膜上形成与所述半导体芯片电连接的布线结构的工序。
2.根据权利要求1所述的半导体装置的制造方法，其中，在所述第一绝缘膜形成开口部的工序中，以所述开口部的大小比所述半导体芯片的芯片尺寸大的方式形成所述开口部，
在形成所述第二绝缘膜的工序中，以埋入到构成第一绝缘膜的开口部的壁面和所述半导体芯片的侧面的间隙中的方式形成第二绝缘膜。
3.根据权利要求1所述的半导体装置的制造方法，其中，所述形成开口部的工序，是以露出所述基板的表面的方式在所述第一绝缘膜形成开口部的工序。
4.根据权利要求1所述的半导体装置的制造方法，其中，所述形成布线结构的工序，包含在使所述基板的搭载有半导体芯片的面侧朝向重力方向的状态下，通过电镀处理在所述第二绝缘膜上形成布线的工序。
5.根据权利要求1所述的半导体装置的制造方法，其中，所述第一绝缘膜及所述第二绝缘膜是感光性的聚酰亚胺树脂膜。
6.一种半导体装置，其中，至少具备：
基板；
第一绝缘膜，设置在所述基板上，具有开口部；
半导体芯片，搭载在所述第一绝缘膜的所述开口部内；
第二绝缘膜，跨越在所述半导体芯片上和所述第一绝缘膜上而设置；以及
布线结构，设置在所述第二绝缘膜上，与所述半导体芯片电连接。
7.根据权利要求6所述的半导体装置，其中，所述第一绝缘膜的开口部的大小比所述半导体芯片的芯片尺寸大，所述第二绝缘膜埋入到构成所述第一绝缘膜的开口部的壁面与所述半导体芯片的侧面的间隙中而设置。
CN2012101725979A 2011-05-30 2012-05-30 半导体装置的制造方法及半导体装置 Pending CN102810484A (zh)

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