JP2012520568A - マスクを使用せずに導電性ビアに対して裏面位置合わせを行うことによる半導体構成部品の製造方法 - Google Patents

マスクを使用せずに導電性ビアに対して裏面位置合わせを行うことによる半導体構成部品の製造方法 Download PDF

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JP2012520568A
JP2012520568A JP2011554061A JP2011554061A JP2012520568A JP 2012520568 A JP2012520568 A JP 2012520568A JP 2011554061 A JP2011554061 A JP 2011554061A JP 2011554061 A JP2011554061 A JP 2011554061A JP 2012520568 A JP2012520568 A JP 2012520568A
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polymer layer
back surface
semiconductor
substrate
component
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JP5500464B2 (ja
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リー，ジン
ジアーン，トーンビー
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マイクロン テクノロジー， インク．
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Abstract

半導体構成部品（９０）を製造する方法が、回路面（５４）と、裏面（５６）と、導電性ビア（５８）とを有する半導体基板（５２）を提供するステップと、導電性ビア（５８）の端子部分（７６）を露出するために、基板（５２）の一部分を裏面（５６）から除去するステップと、端子部分（７６）を封入するポリマー層（７８）を裏面（５６）に堆積するステップと、次いで、ポリマー層（７８）および端子部分（７６）の端部を平坦化して、ポリマー層（７８）に埋め込まれた自己整合導体を形成するステップとを含む。導電性ビア（５８）に電気的に接触させて、端子接点（８６）や裏面再分配導体（８８）等の追加の裏面要素を形成することもできる。半導体構成部品（９０）は、半導体基板（５２）と、導電性ビア（５８）と、およびポリマー層（７８）に埋め込まれた裏面導体とを有する。積重ね半導体構成部品（９６）が、電気的に互いに通じる位置の整合した導電性ビア（５８）を有する複数の構成部品（９０-１、９０-２、９０-３）を有する。

Description

（本文中に技術分野に該当する記載なし）
チップ・スケール・パッケージ等の半導体構成部品は、前世代の構成部品よりも薄型化、小型化され続けている。同時に、半導体構成部品に対する電気的要求事項およびパッケージに関する要求事項は、より厳しくなっている。半導体構成部品の製造中の課題の１つは、回路面の要素に対する、半導体基板の裏面の要素の位置合わせである。たとえば、導電性ビアにより、回路面の導体およびボンド・パッド等の回路面要素と、裏面の導体および端子接点等の裏面要素とが相互接続される。こうした導電性ビアは小さくなり続けており、これにより、裏面の要素に対して導電性ビアの位置を合わせるための従来の製造プロセスがより難しいものになっている。
図１Ａ〜１Ｅは、半導体基板内の導電性ビアの、基板の裏面フィーチャに対する位置合わせを論点とする半導体製造プロセスを示す。図１Ａに示すように、半導体ウエハ１０は、半導体ダイ等の複数の半導体基板１２を有する。半導体ウエハ１０、また半導体基板１２それぞれは、回路面１６および裏面１８を有する。さらに、各半導体基板１２は、回路面１６からその裏面１８に延びる複数の導電性ビア１４を有する。各導電性ビア１４は、半導体基板１２内のビア絶縁体１２に並列な貫通ビア２０を含み、導電金属で充填される。
更に図１Ａに示すように、各半導体基板１２はまた、導電性ビア１４と電気的通じる複数の再分配導体２４を回路面１６上に有する。再分配導体２４は、内側誘電層２６により半導体基板１２から絶縁されており、外側誘電層２８で覆われている。ウエハ１０が、キャリア接着剤３２を使用することによりウエハ・キャリア３０に取り付けられ、これにより、裏面のシンニング（thinning）および平坦化等の裏面作製プロセスを実施することが可能になる。これらのプロセスにより、基板１２が平坦化され、導電性ビア１４の端部に平坦化されたコンタクタ４２（図１Ａ）が形成される。ウエハ・キャリア３０により、裏面要素（例えば、端子接点）の形成等の他のプロセスを行うことも可能になる。このケースでは、導電性ビア１４と電気的に通じる裏面導体３４を形成するためにフォト・パターニング・プロセスが行われている。
図１Ｂに示すように、ウエハ１０の裏面１８にレジスト層３６を堆積することによりフォト・パターニング・プロセスが開始される。レジスト層３６は、スピンコーティング等の従来のプロセスを使用することにより堆積することができる。次に、図１Ｃに示すように、レジスト層３６を露光し、これを現像して、ウエハ１０の裏面１８にフォトマスク３８を形成することができる。フォトマスク３８は、導電性ビア１４に接する露出されたコンタクタ４２と位置が合っているべき複数の開口部４０を有する。位置合わせは、回路面１６上およびウエハ１０の裏面１８上の位置合わせマークを使用することにより成し遂げることができる。しかし、導電性ビア１４のサイズおよび開口部４０のサイズならびに従来のフォト露光機器（photo exposure equipment）の限界に起因して、位置合わせを成し遂げるのが困難なことがある。図２Ａに示すように、位置合わせを容易にするために、導電性ビア１４を、フォトマスク３８内の（図２Ａ内に点線で示す）開口部４０よりも大きくすることができる。たとえば、導電性ビア１４は、約１８μｍの内径（ＩＤ）を有することがあり、フォトマスク３８内の開口部４０は、約１１μｍの直径（ＯＤ）を有することがある。これにより、導電性ビア１４の周囲で約３．５μｍの位置合わせ不良が起こることがある。
図２Ａは、導電性ビア１４の中心と開口部４０の中心とが完全に位置合わせされた最適な位置合わせ状態を示している。しかし実際には、図２Ｂに示すように、フォトマスク３８内の開口部４０は、導電性ビア１４と完全には位置が合わない。下記で更に説明するが、この状態では、導体３４（図２Ｄ）と基板１２との間に短絡４４（図２Ｄ）が形成されることがある。図２Ｃに示すように、フォトマスク３８内の開口部４０から、導電性ビア１４が完全に失われることがある。下記で更に説明するが、この状態では、開回路が形成されることがある。
図１Ｄに示すように、フォトマスク３８の形成に続いて、コンタクタ４２にエッチングを施して、汚染物および自然酸化物を除去することができる。次に、図１Ｅに示すように、無電解鍍金法等の方法で開口部４０内に導体３４を形成することができる。導体３４は、銅等の導電性の高い金属を含むことがある。更に図１Ｅに示すように、導体３４上に、端子接点（図示せず）に対する下部バンプ・メタライゼーション層４６、４８を形成することができる。下部バンプ・メタライゼーション層４６、４８は、無電解鍍金法等の適当な方法で、適当な金属から形成することができる。
図２Ｄおよび２Ｅは、導電性ビア１４に対する導体３４の不良位置合わせに起因する潜在的問題を示す。図２Ｄに示すように、位置合わせ不良が小さい場合（たとえば、５μｍ未満）、導体３４と半導体基板１２との間に短絡４４が起こることがある。図２Ｅに示すように、位置合わせ不良が大きい場合（たとえば、９μｍ超）、導体３４と導電性ビア１４との間に開回路が発生することがある。
上記に鑑みて、裏面要素を備える半導体構成部品を製造する改善された方法が当技術分野では必要とされる。ただし、上述の関連技術の例およびこれらに関する限定事項は、排他的なものではなく例示的なものであることを意図している。本明細書を読むことおよび添付の図面を検討することにより、こうした関連技術の他の限定事項が当業者には明らかになるであろう。
例示的実施形態を、参照符号を付けた図面に示す。これら実施形態および本明細書に添付の図面は、限定ではなく例とみなすことを意図している。
裏面フォト位置合わせ（photo alignment）工程を使用することによる半導体構成部品の従来製造方法の一工程段階を示す概略断面図である。 裏面フォト位置合わせ工程を使用することによる半導体構成部品の従来製造方法の、図１Ａに続く工程段階を示す概略断面図である。 裏面フォト位置合わせ工程を使用することによる半導体構成部品の従来製造方法の、図１Ｂに続く工程段階を示す概略断面図である。 裏面フォト位置合わせ工程を使用することによる半導体構成部品の従来製造方法の、図１Ｃに続く工程段階を示す概略断面図である。 裏面フォト位置合わせ工程を使用することによる半導体構成部品の従来製造方法の、図１Ｄに続く工程段階を示す概略断面図である。 従来方法における導電性ビアを示す、図１Ａを線２Ａ-２Ａで切ったものの拡大概略断面図である。 導電性ビアと裏面レジスト開口部との最適な位置合わせを示す、図１Ｃを線２Ｂ-２Ｂで切ったものの拡大概略断面図である。 導電性ビアと裏面レジスト開口部との位置合わせ不良を示す、図２Ｂと同等の拡大概略断面図である。 短絡を引き起こしている導電性ビアと裏面導体との位置合わせ不良を示す、図１Ｆを線２Ｄで切ったものの拡大概略断面図である。 開回路をもたらしている導電性ビアと裏面導体との位置合わせ不良を示す、図２Ｄと同等の拡大概略断面図である。 マスクを使用しない裏面導電性ビアの位置合わせを利用することにより半導体構成部品を製造する方法の一工程段階を示す概略断面図である。 マスクを使用しない裏面導電性ビアの位置合わせを利用することにより半導体構成部品を製造する方法の、図３Ａに続く工程段階を示す概略断面図である。 マスクを使用しない裏面導電性ビアの位置合わせを利用することにより半導体構成部品を製造する方法の、図３Ｂに続く工程段階を示す概略断面図である。 マスクを使用しない裏面導電性ビアの位置合わせを利用することにより半導体構成部品を製造する方法の、図３Ｃに続く工程段階を示す概略断面図である。 マスクを使用しない裏面導電性ビアの位置合わせを利用することにより半導体構成部品を製造する方法の、図３Ｄに続く工程段階を示す概略断面図である。 エッチバック工程後の導体を示す、図３Ｂを線４Ａで切ったものの拡大概略断面図である。 ポリマー堆積工程後の導電性ビアを示す、図３Ｃを線４Ｂで切ったものの拡大概略断面図である。 平坦化工程後の導電性ビアを示す、図３Ｄを線４Ｃで切ったものの拡大概略断面図である。 導電性ビアと裏面導体との位置の整合を示す、図３Ｅを線４Ｄで切ったものの拡大概略断面図である。 裏面導体に電気的に通じる裏面端子接点を示す、図４Ａと同等の拡大概略断面図である。 裏面導体に電気的に通じる裏面再分配導体および裏面端子接点を示す、図４Ａと同等の拡大概略断面図である。 図３Ａ〜３Ｅの方法に従って製造した半導体構成部品の平面図である。 半導体構成部品の側面図である。 半導体構成部品の断面図であって、図６Ｂを切断線６Ｃ-６Ｃで切ったものの断面図である。 図３Ａ〜３Ｅの方法に従って製造した構成部品を積み重ねたものの概略側面図である。
本明細書では、「半導体構成部品」は、集積回路および半導体デバイスを有する半導体基板を含む電子的要素を意味する。「ウエハレベル」は、複数の半導体構成部品を含む半導体ウエハ等の要素上で実行されるプロセスを意味する。「チップ・スケール」は、半導体ダイとおよそ同一の外形を有する半導体構成部品を意味する。
図３Ａ〜３Ｅを参照すると、マスクを使用しない導電性ビアに対する裏面位置合わせを利用することにより半導体構成部品を製造する方法が示してある。図３Ａに示すように、半導体ウエハ５０を提供することができる。半導体ウエハ５０は、半導体デバイスと集積回路とを含む半導体ダイ等の複数の半導体基板５２を有する。半導体ウエハ５０ならびに各半導体基板５２は、回路面５４および裏面５６を有するが、回路面５４には、半導体デバイスおよび集積回路が配置される。さらに、各半導体基板５２は、回路面５４からその裏面５６に延びる複数の導電性ビア５８を有する。導電性ビア５８は、半導体基板５２内の半導体デバイスおよび集積回路に電気的に通じる。
図３Ａに示すように、各導電性ビア５８は、半導体基板５２内にあり、ビア絶縁体６２に並列で、導電金属で充填された概ね円形の貫通ビア６０を含む。導電金属は、銅、ニッケル、金、アルミニウム、チタン、イリジウム、タングステン、銀、プラチナ、パラジウム、タンタル、モリブデン、亜鉛、錫、半田、これらの金属の合金等の導電性の高い金属を含むことがある。ビア絶縁体６２は、ポリマー（たとえば、ポリイミド）やＳｉＯ２等の絶縁材料を含むことがある。更に図３Ａに示すように、各半導体基板５２は、回路面５４に、導電性ビア５８に電気的に通じる複数の回路側再分配導体６６を更に有する。回路側再分配導体６６は、内側誘電層６４により半導体基板５２から絶縁されており、外側誘電層６８で覆われている。
半導体デバイスおよび集積回路を内部に備える半導体基板５２、導電性ビア５８、回路面再分配導体６６、誘電層６４、６８を含めて、ここまで説明してきた要素は全て、周知の半導体製造プロセスで形成することができる。例えば、基板５２中にビア６０をエッチングまたはレーザ加工し、ポリマー堆積や酸化物成長等の方法でビア中にビア絶縁体６２を形成し、次いで、電解析出、無電解鍍金、ＣＶＤ、ステンシリング、スクリーン印刷法等の方法でビア中に金属を堆積することにより、導電性ビア５８を形成することができる。導電性ビア５８を形成する他の方法では、基板５２内にビア６０を貫通させずに形成し、ビア６０を導電金属で充填し、次いでエッチングやソーイング（sawing）等の方法で基板５２にシンニングを施して導電性金属を露出させる。
両面テープ等のキャリア接着剤７２を使用することにより、ウエハ５０をウエハ・キャリア７０に取り付けるが、これは、紫外線照射で取り外すこともできる。ウエハ・キャリア７０により、裏面シンニング等の裏面作製プロセスを行うことが可能になる。グラインダ等の機械平坦化装置または化学機械平坦化（ＣＭＰ）装置を使用することによりシンニングを行って、シンニング済み裏面５６Ｔを形成することができる。裏面シンニングの後、ウエハ５０は、約１００μｍ〜約７２５μｍの厚みを有することができる。ウエハ・キャリア７０により、裏面要素（たとえば、端子接点）の形成等の他の裏面プロセスを行うことも可能になる。
次に、図３Ｂおよび４Ａに示すように、除去工程を行って、基板５２の裏面５６の一部分を除去し、導電性ビア５８の端子部分７６（図４Ａ）を露出させる。除去工程は、湿式エッチング・プロセス、乾式エッチング・プロセス、または反応性イオン・エッチング（ＲＥＩ）等のプラズマ・エッチング・プロセスを利用することにより行うことができる。たとえば、シリコンからなる半導体基板５２にエッチングを施す場合、水酸化テトラメチルアンモニウム（ＴＭＡＨ）の溶液、あるいは水酸化テトラメチルアンモニウム（ＫＯＨ）の溶液を使用することにより湿式エッチング・プロセスを行うことができる。図４Ａに示すように、除去工程を行って、半導体基板５２の約５〜１０μｍを除去し、これにより、シンニング済み裏面５６Ｔから、５〜１０μｍの高さＸを有する、導電性ビア５８の露出端子部分７６を残すことができる。
次に、図３Ｃおよび４Ｂに示すように、ポリマー堆積工程を行って、ポリマー層７８を形成するが、このポリマー層７８は、半導体基板５２のシンニング済み裏面５６Ｔを覆い、導電性ビア５８の露出端子部分７６を封入する。ポリマー層７８は、シリコン、ポリイミド、エポキシ等の硬化性ポリマーを含むことがある。さらに、ポリマー層７８は、ポリマー材料の熱膨張係数（ＣＴＥ）および粘度を調整するためのシリケート等の充填剤を含むことがある。スピンコーティング、ノズル堆積（nozzle deposition）、スクリーン印刷法、ステンシリング、リソグラフィ等の適当な方法で、シンニング済み裏面５６Ｔにポリマー層７８を堆積することができる。たとえば、スピンコーティングの場合、半導体ウエハ５０のシンニング済み裏面５６Ｔにスピンオンポリマーを塗布して、次いで、スピンコータを使用することにより半導体ウエハ５０を高速でスピンさせて液体を取り除くことができる。スピンコーティングの後、ポリマー材料は硬化することができる。結果として得られる堆積材料の厚さは、溶液の粘度およびスピン速度に依存する。この厚さは、導電性ビア５８の端子部分７６（図４Ａ）が封入されるように選択される。例として、ポリマー層７８は、１０〜２５μｍの厚さを有することができる。
次に、図３Ｄおよび４Ｃに示すように、平坦化工程を行って、導電性ビア５８に平坦化コンタクタ７４を形成する。平坦化工程により、ポリマー層７８も平坦化され、平坦化ポリマー表面８０が形成される。平坦化工程は、化学機械平坦化（ＣＭＰ）を利用することにより行うことができる。たとえば、適当なＣＭＰ装置が、Westech社、SEZ社、Plasma Polishing Systems社、TRUSI社等の製造業者から市販されている。平坦化工程はまた、グラインダを使用する機械平坦化法で行うことも、フル・オートマチックのサーフィス・プレーナ・ユニットであるＤＩＳＣＯ等のサーフィス・プレーナ・ユニットを使用するフライ・カットで行うことも可能である。平坦化工程は、導電性ビア５８の表面が終点となるように制御することも、少量の導電性ビア５８を除去するように制御することもできる。平坦化工程後のポリマー層７８の典型的な厚さとしては、５〜１０μｍがある。
次に、図３Ｅおよび４Ｄに示すように、メタライゼーション工程を行って、導電性ビア５８の平坦化コンタクタ７４上に下部バンプ・メタライゼーション層（ＵＢＭ）８２、８４を形成する。下部バンプ・メタライゼーション層（ＵＢＭ）８２、８４は、無電解鍍金法、電解析出、ＣＶＤ等の堆積法または鍍金法で形成することができる。下部バンプ・メタライゼーション（ＵＢＭ）層８２、８４は、端子接点８６を形成または接着する（図５Ａ）ための表面を提供するように構成された１つまたは複数の層を含むことがある。たとえば、下部バンプ・メタライゼーション（ＵＢＭ）層８２は、ニッケル、亜鉛、クロム、パラジウム等の金属から形成される接着層を含むことがある。下部バンプ・メタライゼーション層８４は、錫、パラジウム、金等の金属から形成される半田湿潤性金属層（solder wettable metal layer）を含むことがある。
半導体構成部品を製造する本発明による方法（図３Ａ〜３Ｅ）では、従来技術による方法（図１Ａ〜１Ｅ）のフォトマスク３８（図１Ｃ）が存在しない。さらに、本方法（図３Ａ〜３Ｅ）では、導電性ビア１４に対するマスク３８（図１Ｃ）の位置合わせが行われず、導体３４（図１Ｅ）が形成されない。本方法（図３Ａ〜３Ｅ）の場合、導電性ビア５８の端子部分７６（図４Ａ）が導体を形成し、これら導体は、導電性ビア５８に対して自己整合される。これにより、導電性ビア５８のＯＤを約１０μｍ以下とすることが可能になる。さらに、短絡４４（図２Ｄ）または開回路（図２Ｅ）が形成される可能性がない。この点について、ポリマー層７８により、端子部分７６（図４Ａ）と半導体基板５２との間に追加の電気絶縁がもたらされ、これにより、短絡が生じることができない。
図５Ａおよび５Ｂを参照すると、追加の裏面プロセスを行って、導電性ビア５８に電気的に通じる裏面要素を形成することができる。たとえば、図５Ａに示すように、下部バンプ・メタライゼーション層８２、８４上に端子接点８６を形成することができる。端子接点８６は、ステンシリングや下部バンプ・メタライゼーション層８２、８４上への半田合金のリフロー等の適当な堆積法で形成した、半田、他の金属または導電性ポリマーを含むことがある。図５Ｂに示すように、ポリマー層７８の平坦化表面８０上に、導電性ビア５８に電気的に通じる裏面再分配導体８８を形成することもできる。裏面再分配導体８８は、マスクによる無電解鍍金等の適当な方法で形成することも、金属の堆積層にパターニングを施すことにより形成することもできる。さらに、実質的に上で説明したように、裏面再分配導体８８上に端子接点８６を形成することができる。
裏面加工工程の後、半導体ウエハ５０にダイシングを施して、複数のチップ・スケール半導体構成部品９０（図６）を形成することができる。ダイシングは、レーザ加工、ソーイング、ウォーター・ジェット、エッチング等の方法で達成することができる。ダイシング工程の後、半導体構成部品９０（図６）をキャリア７０から外すことができる。
図６Ａ〜６Ｃに示すように、各半導体構成部品９０は、複数の導電性ビア５８を有する半導体基板５２を有する。各導電性ビア５８は、自己整合裏面導体を形成する端子部分７６を有するが、この自己整合裏面導体は、従来技術の裏面導体３４（図１Ｅ）と実質的に同等である。さらに、半導体構成部品９０は、導電性ビア５８の端子部分７６を封入する裏面ポリマー層７８と、導電性ビア５８と電気的に通じる端子接点８６とを有する。半導体構成部品９０はまた、内側誘電層６４と、導電性ビア５８と電気的に通じる回路面再分配導体６６と、回路面外側誘電層６８とを有する。外側誘電層６８は、導電性ビア５８と位置の合った開口部９２（図６Ｃ）を有する（あるいは、導電性ビア５８と電気的に通じる接点を備える）ことがあり、これにより、複数の半導体構成部品９０を積み重ねることが可能になる。
図７を参照すると、積重ね半導体構成部品９６が、モジュール基板９４に取り付けられた上部構成部品９０-１、中間構成部品９０-２および下部構成部品９０-３を含む積重ねアレイ内の複数の半導体構成部品９０を有する。上部構成部品９０-１の端子接点８６を中間構成部品９０-２の導電性ビア５８に接着することができ、中間構成部品９０-２の端子接点８６を下部構成部品９０-３の導電性ビア５８に接着することができる。さらに、下部構成部品９０-３の端子接点８６をモジュール基板９４上の電極に接着することができる。さらに、構成部品９０-１、９０-２、９０-３、モジュール基板９４間にアンダーフィル層９８を形成することができる。構成部品９０-１、９０-２、９０-３の導電性ビア５８の位置合わせにより、積重ね構成部品５６の製造が容易になる。
いくつかの例示的態様および例示的実施形態について上で議論してきたが、これらの特定の修正形態、置換え、これらに対する追加およびこれらを部分的に組み合わせた形態が、当業者には理解されるであろう。したがって、添付の特許請求の範囲、および今後導入される請求項は、こうした修正形態、置換え、追加、部分的組合せが全て、これら請求項の真の趣旨および範囲に含まれるものとして理解されることを意図している。

Claims (30)

  1. 半導体構成部品を製造する方法であって、
    回路面と、裏面と、複数の導電性ビアとを有する半導体基板を提供するステップと、
    前記導電性ビアの端子部分を露出するために、前記基板の一部分を前記裏面から除去するステップと、
    前記端子部分を封入するポリマー層を前記裏面に堆積するステップと、
    前記ポリマー層および前記端子部分を平坦化するステップと、
    を含む方法。
  2. 前記端子部分上に複数の端子接点を形成するステップを更に含む、
    請求項１に記載の方法。
  3. 前記端子部分と電気的に接触する複数の裏面再分配導体を前記ポリマー層上に形成するステップを更に含む、
    請求項１に記載の方法。
  4. 前記除去ステップが、エッチングを行うステップを含む、
    請求項１に記載の方法。
  5. 前記平坦化ステップで、前記端子部分が、前記ポリマー層に埋め込まれるとともに平坦化されたコンタクタを有する導体として形成される、
    請求項１に記載の方法。
  6. 半導体構成部品を製造する方法であって、
    回路面と、裏面と、複数の導電性ビアとを有する半導体基板を提供するステップであって、前記複数の導電性ビアが、前記基板内にあり、金属で充填され、電気的に絶縁された貫通ビアを含む、ステップと、
    前記導電性ビアの端子部分を露出するために、前記基板に前記裏面からエッチングを施すステップと、
    前記端子部分を封入するポリマー層を前記裏面に堆積するステップと、
    前記金属を含み、前記ポリマー層に埋め込まれ、平坦化されたコンタクタを有する自己整合導体を形成するために、前記ポリマー層、および前記導電性ビアの前記端子部分を平坦化するステップと、
    を含む方法。
  7. 前記コンタクタ上に複数のメタライゼーション層を形成し、前記メタライゼーション層上に端子接点を形成するステップを更に含む、
    請求項６に記載の方法。
  8. 前記コンタクタと電気的に接触する複数の裏面再分配導体を前記ポリマー層上に形成するステップを更に含む、
    請求項６に記載の方法。
  9. 前記エッチング・ステップの前に、前記裏面から前記基板にシンニングを施すステップを更に含む、
    請求項６に記載の方法。
  10. 前記堆積ステップが、スピンオン法で行われる、
    請求項６に記載の方法。
  11. 前記提供ステップで、前記半導体基板が、ウエハ・キャリアに取り付けた半導体ウエハ上に提供され、前記エッチング・ステップ、前記堆積ステップおよび前記平坦化ステップが、前記キャリアに取り付けた前記ウエハ上で行われる、
    請求項６に記載の方法。
  12. 前記エッチング・ステップで、前記基板の約５〜１０μｍが除去される、
    請求項６に記載の方法。
  13. 前記端子部分の高さが、約５〜１０μｍである、
    請求項６に記載の方法。
  14. 半導体構成部品を製造する方法であって、
    回路面と、裏面と、複数の集積回路を有する複数の半導体基板とを備える半導体ウエハを提供するステップと、
    前記集積回路に電気的に通じる複数の導電性ビアを前記基板中に形成するステップであって、各導電性ビアが、ビア、前記ビア内の絶縁層、および前記ビアを充填する金属を含む、ステップと、
    前記導電性ビアの端子部分を露出するために、前記裏面の一部分を除去するステップと、
    前記端子部分を封入するポリマー層を前記裏面に堆積するステップと、
    前記ポリマー層に埋め込まれ、平坦化されたコンタクタを有する自己整合導体を形成するために、前記ポリマー層および前記端子部分を平坦化するステップと、
    前記基板を分離するために前記ウエハにダイシングを施すステップと、
    を含む方法。
  15. 前記除去ステップが、エッチングを行うステップを含む、
    請求項１４に記載の方法。
  16. 前記除去ステップの前に、前記裏面から前記基板にシンニングを施すステップを更に含む、
    請求項１４に記載の方法。
  17. 前記ポリマー層を堆積する前記ステップが、スピンコーティングを行うステップを含む、
    請求項１４に記載の方法。
  18. 前記導体に電気的に通じる複数の裏面要素を前記ポリマー層上に形成するステップを更に含む、
    請求項１４に記載の方法。
  19. 前記コンタクタ上に下部バンプ・メタライゼーション層を形成し、前記下部バンプ・メタライゼーション層上に端子接点を形成するステップを更に含む、
    請求項１４に記載の方法。
  20. 前記コンタクタと電気的に接触する裏面再分配導体を前記ポリマー層上に形成するステップを更に含む、
    請求項１４に記載の方法。
  21. 回路面および裏面を有する半導体基板と、
    前記基板中の複数の導電性ビアであって、各導電性ビアが、ビア、前記ビア中の絶縁層、および前記ビアを充填する金属を含む導電性ビアと、
    前記裏面上のポリマー層と、
    前記導電性ビアの端子部分を含み、前記ポリマー層に埋め込まれた複数の裏面導体と、
    を備える半導体構成部品。
  22. 前記導体が、平坦化されたコンタクタを備える、
    請求項２１に記載の半導体構成部品。
  23. 前記導体上に複数の端子接点を更に備える、
    請求項２１に記載の半導体構成部品。
  24. 前記端子部分と電気的に接触する複数の裏面再分配導体を前記ポリマー層上に更に備える、
    請求項２１に記載の半導体構成部品。
  25. 前記端子部分の高さが、５〜１０μｍである、
    請求項２１に記載の半導体構成部品。
  26. 積重ねアレイ内の複数の半導体構成部品を備える積重ね半導体構成部品であって、
    各構成部品が、
    回路面および裏面を有する半導体基板と、
    前記基板中の複数の導電性ビアであって、各導電性ビアが、ビア、前記ビア中の絶縁層、および前記ビアを充填する金属を含む導電性ビアと、
    前記裏面上のポリマー層と、
    前記導電性ビアの端子部分を含み、前記ポリマー層に埋め込まれた複数の裏面導体と、
    を備え、
    前記構成部品が、前記導電性ビアと位置が合った状態で、回路面の裏面に積み重ねられる、
    積重ね半導体構成部品。
  27. 各構成部品が、自体上の前記導電性ビアと、隣接する構成部品上の前記導電性ビアとに接着された複数の端子接点を備える、
    請求項２６に記載の積重ね構成部品。
  28. 前記導体が、平坦化されたコンタクタおよび前記コンタクタ上の端子接点を有する、
    請求項２６に記載の積重ね構成部品。
  29. 前記積重ねアレイを支持するモジュール基板を更に備える、
    請求項２６に記載の積重ね構成部品。
  30. 前記構成部品が、第１の構成部品と、前記第１の構成部品上の前記導電性ビアに接着された複数の端子接点を有する第２の構成部品とを含む、
    請求項２６に記載の積重ね構成部品。
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US7998860B2 (en) 2011-08-16
EP2406816A4 (en) 2013-04-03
KR20110124295A (ko) 2011-11-16
SG173711A1 (en) 2011-09-29
CN102349140B (zh) 2014-03-26
TW201044477A (en) 2010-12-16
WO2010104637A1 (en) 2010-09-16
US20210134674A1 (en) 2021-05-06
US20100230794A1 (en) 2010-09-16
CN102349140A (zh) 2012-02-08
TWI424512B (zh) 2014-01-21
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JP5500464B2 (ja) 2014-05-21
US11869809B2 (en) 2024-01-09

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