CN102349140B - 用于使用与导电通孔的无掩模背侧对准制作半导体组件的方法 - Google Patents

用于使用与导电通孔的无掩模背侧对准制作半导体组件的方法 Download PDF

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CN102349140B
CN102349140B CN201080011143.2A CN201080011143A CN102349140B CN 102349140 B CN102349140 B CN 102349140B CN 201080011143 A CN201080011143 A CN 201080011143A CN 102349140 B CN102349140 B CN 102349140B
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hole
complanation
conductive
semiconductor
dorsal part
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CN102349140A (zh
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李劲
江同必
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本发明涉及一种用于制作半导体组件(90)的方法，所述方法包括以下步骤：提供具有电路侧(54)、背侧(56)及若干导电通孔(58)的半导体衬底(52)；从所述背侧(56)移除所述衬底(52)的若干部分以暴露所述导电通孔(58)的端子部分(76)；在所述背侧(56)上沉积聚合物层(78)以囊封所述端子部分(76)；及接着对所述聚合物层(78)及所述端子部分(76)的末端进行平面化以形成嵌入于所述聚合物层(78)中的若干自对准导体。还可形成与所述导电通孔(58)电接触的额外背侧元件，例如端子触点(86)及背侧再分布导体(88)。半导体组件(90)包括所述半导体衬底(52)、所述导电通孔(58)及嵌入于所述聚合物层(78)中的所述背侧导体。堆叠式半导体组件(96)包括具有彼此电连通的经对准导电通孔(58)的多个组件(90-1、90-2、90-3)。

Description

用于使用与导电通孔的无掩模背侧对准制作半导体组件的方法
背景技术
半导体组件(例如芯片尺寸封装)被制作得比先前几代组件更薄及更小。同时，对半导体组件的电及封装要求变得更加严格。在半导体组件的制作期间的一个挑战是半导体衬底的背侧上的元件与电路侧上的元件的对准。举例来说，导电通孔将电路侧元件(例如电路侧导体及接合垫)与背侧元件(例如背侧导体及端子触点)互连。导电通孔正在变小，因此用于将导电通孔与背侧元件对准的常规制作工艺变得更困难。
图1A到图1E图解说明其中半导体衬底中的导电通孔与所述衬底上的背侧特征的对准成问题的半导体制作工艺。如图1A中所示，半导体晶片10包括多个半导体衬底12，例如半导体晶粒。半导体晶片10以及半导体衬底12中的每一者包括电路侧16及背侧18。另外，每一半导体衬底12包括从其电路侧16延伸到背侧18的多个导电通孔14。每一导电通孔14包含在半导体衬底12中的贯穿通孔20，贯穿通孔20加衬有通孔绝缘体22且填充有导电金属。
如图1A中还展示，每一半导体衬底12还包括在电路侧16上与导电通孔14电连通的多个再分布导体24。再分布导体24通过内部电介质层26与半导体衬底12绝缘，且由外部电介质层28覆盖。使用载体粘合剂32将晶片10附接到晶片载体30，所述载体粘合剂准许执行背侧制作工艺(例如背侧薄化及平面化)。这些工艺对衬底12进行平面化，且在导电通孔14的末端上形成经平面化接触器42(图1A)。晶片载体30还允许执行其它工艺，例如背侧元件(例如，端子触点)的形成。在本情况下，正执行光图案化工艺以形成与导电通孔14电连通的背侧导体34。
如图1B中所示，通过在晶片10的背侧18上沉积抗蚀剂层36来起始光图案化工艺。可使用例如旋转涂覆等常规工艺来沉积抗蚀剂层36。接下来，如图1C中所示，抗蚀剂层36可经曝光及显影以在晶片10的背侧18上形成光掩模38。光掩模38包括多个开口40，所述多个开口应与导电通孔14上的经暴露接触器42对准。可使用晶片10的电路侧16及背侧18上的对准标记来实现对准。然而，归因子导电通孔14的大小及开口40的大小以及常规曝光设备的限制，可能难以实现对准。如图2A中所示，为了促进对准，可使得导电通孔14大于光掩模38中的开口40(由图2A中的虚线表示)。举例来说，导电通孔14可具有约18μm的内侧直径(ID)，而光掩模38中的开口40可具有约11μm的直径(OD)。此允许在导电通孔14的每一侧上发生约3.5μm的不对准。
图2A图解说明其中导电通孔14的中心与开口40的中心完全对准的最优对准情形。然而，如图2B中所示，在实际实践中，光掩模38中的开口40不与导电通孔14完全对准。如将进一步解释，此情形可致使在导体34(图2D)与衬底12之间形成短路44(图2D)。如图2C中所示，光掩模38中的开口40可与导电通孔14完全错位。如将进一步解释，此情形可形成开路。
如图1D中所示，在形成光掩模38之后，可蚀刻接触器42以移除污染物及自生氧化物层。接下来，如图1E中所示，可使用例如无电镀沉积等工艺在开口40中形成导体34。导体34可包含例如铜的高导电性金属。如图1E中还展示，可在导体34上形成用于端子触点(未显示)的凸块底部金属化层46、48。凸块底部金属化层46、48可使用适合工艺(例如用适合金属做材料的无电镀沉积)来形成。
图2D及图2E图解说明由导体34与导电通孔14的不对准引起的潜在问题。如图2D中所示，小量的不对准(例如，＜5μm)可引起导体34与半导体衬底12之间的短路44。如图2E中所示，大量的不对准(例如，＞9μm)可引起导体34与导电通孔14之间的开路。
鉴于前文，此项技术中需要用于制作具有背侧元件的半导体组件的经改进方法。然而，相关技术的前述实例及与其相关的限制打算为说明性而非排他性。所属领域的技术人员在阅读说明书及研究图式之后，将易于明了相关技术的其它限制。
附图说明
在图式的所参考图中图解说明示范性实施例。打算将本文中所揭示的实施例及图视为说明性而非限制性。
图1A到图1E是图解说明用于使用背侧光对准步骤制作半导体组件的现有技术方法中的步骤的示意性横截面图；
图2A是沿图1A的线2A-2A截取的放大示意性横截面图，其图解说明现有技术方法中的导电通孔；
图2B是沿图1C的线2B-2B截取的放大示意性横截面图，其图解说明导电通孔与背侧抗蚀剂开口之间的最优对准；
图2C是等效于图2B的放大示意性横截面图，其图解说明导电通孔与背侧抗蚀剂开口之间的不对准；
图2D是沿图1F的线2D截取的放大示意性横截面图，其图解说明导电通孔与背侧导体之间的产生短路的不对准；
图2E是等效于图2D的放大示意性横截面图，其图解说明导电通孔与背侧导体之间的产生开路的不对准；
图3A到图3E是图解说明用于使用无掩模背侧导电通孔对准来制作半导体组件的方法的示意性横截面图；
图4A是沿图3B的线4A截取的放大示意性横截面图，其图解说明在回蚀步骤之后的导电通孔；
图4B是沿图3C的线4B截取的放大示意性横截面图，其图解说明在聚合物沉积步骤之后的导电通孔；
图4C是沿图3D的线4C截取的放大示意性横截面图，其图解说明在平面化步骤之后的导电通孔；
图4D是沿图3E的线4D截取的放大示意性横截面图，其图解说明导电通孔与背侧导体的对准；
图5A是等效于图4A的放大示意性横截面图，其图解说明与背侧导体电连通的背侧端子触点；
图5B是等效于图4A的放大示意性横截面图，其图解说明背侧再分布导体及与所述背侧导体电连通的端子触点；
图6A是根据图3A到图3E的方法制作的半导体组件的平面图；
图6B是半导体组件的侧视立面图；
图6C是半导体组件沿图6B的截面线6C-6C截取的横截面图；且
图7是根据图3A到图3E的方法制作的堆叠式组件的示意性侧视立面图。
具体实施方式
如本文中所使用，“半导体组件”意指包括具有集成电路及半导体装置的半导体衬底的电子元件。“晶片级”意指在含有多个半导体组件的元件(例如半导体晶片)上进行的工艺。“芯片尺寸”意指具有与半导体晶粒的轮廓大约相同的轮廓的半导体组件。
参考图3A到图3E，图解说明用于使用与导电通孔的无掩模背侧对准制作半导体组件的方法。如图3A中所示，可提供半导体晶片50。半导体晶片50包括含有半导体装置及集成电路的多个半导体衬底52(例如半导体晶粒)。半导体晶片50以及半导体衬底52中的每一者包括半导体装置及集成电路位于其中的电路侧54及背侧56。另外，每一半导体衬底52包括从其电路侧54延伸到背侧56的多个导电通孔58。导电通孔58与半导体衬底52中的半导体装置及集成电路电连通。
如图3A中所示，每一导电通孔58包含半导体衬底52中的大体圆形贯穿通孔60，通孔60加衬有通孔绝缘体62且填充有导电金属。所述导电金属可包含高导电性金属，例如铜、镍、金、铝、钛、铱、钨、银、铂、钯、钽、钼、锌、锡、焊料及这些金属的合金。通孔绝缘体62可包含电绝缘材料，例如聚合物(例如，聚酰亚胺)或SiO2。如图3A中还展示，每一半导体衬底52在电路侧54上还包括与导电通孔58电连通的多个电路侧再分布导体66。电路侧再分布导体66通过内部电介质层64与半导体衬底52绝缘，且由外部电介质层68覆盖。
可使用众所周知的半导体制作工艺形成到目前为止所描述的所有元件，包括其中具有半导体装置及集成电路的半导体衬底52、导电通孔58、电路侧再分布导体66及电介质层64、68。举例来说，可通过以下操作来形成导电通孔58：蚀刻或激光加工贯穿衬底52的通孔60；使用例如聚合物沉积或氧化物生长等工艺在所述通孔中形成通孔绝缘体62；及接着使用例如电解沉积、无电镀沉积、CVD、模板印刷或丝网印刷等工艺在所述通孔中沉积金属。用于形成导电通孔58的另一方法是形成部分贯穿衬底52的通孔60、用导电金属填充通孔60，及接着使用例如蚀刻或锯割等工艺对衬底52进行薄化以暴露所述导电金属。
使用载体粘合剂72(例如双面胶带)将晶片50附接到晶片载体70，所述载体粘合剂可使用UV辐射去接合。晶片载体70准许执行背侧制作工艺，例如背侧薄化。可使用机械平面化设备(例如研磨机)或化学机械平面化(CMP)设备执行薄化以形成经薄化的背侧56T。在背侧薄化之后，晶片50可具有从约100μm到约725μm的厚度。晶片载体70还允许执行其它背侧工艺，例如形成背侧元件(例如，端子触点)。
接下来，如图3B及图4A中所示，执行移除步骤以移除衬底52的背侧56的若干部分且暴露导电通孔58的端子部分76(图4A)。可使用湿蚀刻工艺、干蚀刻工艺或等离子蚀刻工艺(例如反应性离子蚀刻(REI))来执行所述移除步骤。举例来说，为蚀刻由硅制成的半导体衬底52，可使用四甲基氢氧化铵(TMAH)溶液或(替代地)氢氧化钾(KOH)溶液来执行湿蚀刻工艺。如图4A中所示，可执行所述移除步骤以将半导体衬底52移除约5μm到10μm，从而使导电通孔58的经暴露端子部分76距经薄化背侧56T的高度X为从5μm到10μm。
接下来，如图3C及图4B中所示，执行聚合物沉积步骤以形成聚合物层78，聚合物层78覆盖半导体衬底52的经薄化背侧56T且囊封导电通孔58的经暴露端子部分76。聚合物层78可包含例如硅酮、聚酰亚胺或环氧树脂等可固化聚合物。另外，聚合物层78可包括填充物(例如硅酸盐)以用于调整热膨胀系数(CTE)及聚合物材料的粘度。可使用例如旋转涂覆、喷嘴沉积、丝网印刷、模板印刷或光刻等适合工艺在经薄化背侧56T上沉积聚合物层78。举例来说，借助旋转涂覆，可向半导体晶片50的经薄化背侧56T施加旋涂聚合物，接着使用旋转涂覆器使所述旋涂聚合物迅速旋转以使其排出液体。在旋转涂覆之后，可对所述聚合物材料进行固化。所得沉积材料的厚度取决于溶液的粘度及旋转速度。此厚度经选择以囊封导电通孔58的端子部分76(图4A)。举例来说，聚合物层78可具有从10μm到25μm的厚度。
接下来，如图3D及图4C中所示，执行平面化步骤以在导电通孔58上形成经平面化接触器74。所述平面化步骤还对聚合物层78进行平面化且形成经平面化聚合物表面80。可使用化学机械平面化(CMP)来执行所述平面化步骤。举例来说，适合CMP设备可从例如维思特科技公司(Westech)、SEZ、等离子抛光系统公司(Plasma PolishingSystems)或TRUSI等制造商购得。还可通过使用研磨机的机械平面化或使用表面平面单元(例如DISCO全自动表面平面单元)的飞刀切削来执行所述平面化步骤。所述平面化步骤可经控制以终止于导电通孔58的表面处或移除少量导电通孔58。在所述平面化步骤之后，聚合物层78的代表性厚度可为从5μm到10μm。
接下来，如图3E及图4D中所示，执行金属化步骤以在导电通孔58的经平面化接触器74上形成凸块底部金属化层(UBM)82、84。可使用沉积或镀覆工艺(例如无电沉积、电解沉积或CVD)来形成凸块底部金属化层(UBM)82、84。凸块底部金属化(UBM)层82、84可包含经配置以提供用于形成或接合端子触点86(图5A)的表面的一个或一个以上层。举例来说，凸块底部金属化(UBM)层82可包含由例如镍、锌、铬或钯等金属形成的粘合层。凸块底部金属化层84可包含由例如锡、钯或金等金属形成的焊料可润湿金属层。
用于制作半导体组件的本发明方法(图3A到图3E)消除现有技术方法(图1A到图1E)的光掩模38(图1C)。另外，本发明方法(图3A到图3E)消除掩模38(图1C)与导电通孔14的对准且消除导体34(图1E)的形成。借助本发明方法(图3A到图3E)，导电通孔58的端子部分76(图4A)形成与导电通孔58自对准的导体。此允许导电通孔58具有约10μm或小于10μm的OD。另外，不存在形成短路44(图2D)或形成开路(图2E)的可能性。在这点上，聚合物层78在端子部分76(图4A)与半导体衬底52之间提供额外电绝缘，使得无法发生短路。
参考图5A及图5B，可执行额外背侧工艺以形成与导电通孔58电连通的背侧元件。举例来说，如图5A中所示，可在凸块底部金属化层82、84上形成端子触点86。端子触点86可包含使用适合沉积工艺(例如模板印刷及焊料合金的回流)形成到凸块底部金属化层82、84上的焊料、另一金属或导电聚合物。如图5B中所示，还可在聚合物层78的经平面化表面80上形成与导电通孔58电连通的背侧再分布导体88。可使用适合工艺(例如通过掩模的无电镀沉积或通过对所沉积金属层进行图案化)来形成背侧再分布导体88。另外，大致如先前所描述，可在背侧再分布导体88上形成端子触点86。
在背侧处理步骤之后，可切割半导体晶片50以形成多个芯片尺寸半导体组件90(图6)。可使用例如激光作用、锯割、冲水或蚀刻等工艺实现切割。在所述切割步骤之后，可从载体70移除半导体组件90(图6)。
如图6A到图6C中所示，每一半导体组件90包括具有多个导电通孔58的半导体衬底52。每一导电通孔58包括形成自对准背侧导体的端子部分76，所述自对准背侧导体大致等效于现有技术背侧导体34(图1E)。另外，半导体组件90包括囊封导电通孔58的端子部分76的背侧聚合物层78及与导电通孔58电连通的端子触点86。半导体组件90还包括内部电介质层64、与导电通孔58电连通的电路侧再分布导体66及电路侧外部电介质层68。外部电介质层68可包括与导电通孔58对准(或替代地具有与导电通孔58电连通的触点)的开口92(图6C)，开口92准许多个半导体组件90的堆叠。
参考图7，堆叠式半导体组件96包括安装到模块衬底94的呈堆叠式阵列的多个半导体组件90，包括上部组件90-1、中间组件90-2及下部组件90-3。上部组件90-1上的端子触点86可接合到中间组件90-2上的导电通孔58，且中间组件90-2上的端子触点86可接合到下部组件90-3上的导电通孔58。另外，下部组件90-3上的端子触点86可接合到模块衬底94上的电极。此外，可在组件90-1、90-2、90-3与模块衬底94之间形成底填充层98。组件90-1、90-2、90-3上的导电通孔58的对准促进堆叠式组件56的制作。
尽管上文已论述大量示范性方面及实施例，但所属领域的技术人员将认识到某些修改、置换、添加及其子组合。因此打算将以上权利要求书及上文引入的权利要求解释为将所有此些修改、置换、添加及子组合包括在其真实精神及范围中。

Claims (27)

1.一种用于制作半导体组件的方法，其包含：
提供具有电路侧、背侧及多个导电通孔的半导体衬底，所述多个导电通孔包含从所述电路侧延伸到所述背侧的通孔、给所述通孔加衬的电绝缘层及所述通孔中的金属；
在所述电路侧上形成与所述导电通孔电接触的多个电路侧导体；
在所述电路侧上形成具有与所述导电通孔对准的开口的外部电介质层；
从所述背侧移除所述半导体衬底的若干部分以暴露所述导电通孔的端子部分及表面，所述端子部分及表面从所述背侧延伸而具有高度X；
在所述背侧上沉积聚合物层以囊封所述端子部分及所述端子部分的所述表面，其中所述聚合物层具有等于或大于所述高度X的厚度；
对所述聚合物层、所述端子部分及所述端子部分的所述表面进行平面化以形成包含嵌入于所述聚合物层中的所述金属的自对准导体、经平面化聚合物表面及所述导电通孔上的经平面化接触器，其中所述平面化步骤经控制以终止于所述端子部分的所述表面处；及
在所述经平面化接触器上形成多个端子触点。
2.根据权利要求1所述的用于制作半导体组件的方法，其进一步包含在移除所述半导体衬底的若干部分的步骤之前对所述半导体衬底进行薄化。
3.根据权利要求1所述的用于制作半导体组件的方法，其中所述形成所述端子触点的步骤包含在所述经平面化接触器上形成若干凸块底部金属化层。
4.根据权利要求1所述的用于制作半导体组件的方法，其中所述平面化步骤包含化学机械平面化（CMP）或研磨。
5.根据权利要求1所述的用于制作半导体组件的方法，其进一步包含在所述形成所述电路侧导体的步骤之前，在所述电路侧上形成电介质层且在所述电介质层上形成所述电路侧导体。
6.一种用于制作半导体组件的方法，其包含：
提供具有电路侧、背侧及多个导电通孔的半导体衬底，所述多个导电通孔包含所述半导体衬底中的从所述电路侧到所述背侧的贯穿通孔、给所述通孔加衬的电绝缘层及所述通孔中的金属；
从所述背侧蚀刻所述半导体衬底以暴露所述导电通孔的端子部分及表面，所述端子部分及表面从所述背侧延伸而具有高度X；
在所述背侧上沉积聚合物层以囊封所述端子部分及所述端子部分的所述表面，其中所述聚合物层具有等于或大于所述高度X的厚度；
对所述聚合物层进行平面化以形成经平面化聚合物表面，且对所述导电通孔的所述端子部分的所述表面进行平面化以形成包含嵌入于所述聚合物层中的所述金属及由所述端子部分的所述表面形成的经平面化接触器的自对准导体；
将所述平面化步骤控制为终止于所述端子部分的所述表面处；及
在所述经平面化聚合物表面上形成与所述经平面化接触器电接触的多个再分布导体。
7.根据权利要求6所述的用于制作半导体组件的方法，其进一步包含在所述再分布导体上形成多个金属化层，且在所述金属化层上形成若干端子触点。
8.根据权利要求6所述的用于制作半导体组件的方法，其进一步包含在所述再分布导体上形成多个端子触点。
9.根据权利要求6所述的用于制作半导体组件的方法，其进一步包含在所述蚀刻步骤之前从所述背侧对所述半导体衬底进行薄化。
10.根据权利要求6所述的用于制作半导体组件的方法，其中使用旋涂工艺来执行所述沉积步骤。
11.根据权利要求6所述的用于制作半导体组件的方法，其中所述提供步骤在附接到晶片载体的半导体晶片上提供所述半导体衬底，且在附接到所述晶片载体的所述半导体晶片上执行所述蚀刻、沉积及平面化步骤。
12.根据权利要求6所述的用于制作半导体组件的方法，其中所述蚀刻步骤将所述半导体衬底移除从5μm到10μm，且所述沉积步骤在所述背侧上形成具有从10μm到25μm的厚度的所述聚合物层。
13.根据权利要求6所述的用于制作半导体组件的方法，其中所述背侧上的所述端子部分的所述高度X为5μm到10μm，且所述沉积步骤在所述背侧上形成具有从10μm到25μm的厚度的所述聚合物层。
14.一种用于制作半导体组件的方法，其包含：
提供半导体晶片，所述半导体晶片包含电路侧、背侧及具有多个集成电路的多个半导体衬底；
形成贯穿所述半导体衬底的从所述电路侧到所述背侧的与所述集成电路电连通的多个导电通孔，每一导电通孔包含通孔、所述通孔中的绝缘层及填充所述通孔的金属；
在所述电路侧上形成电路侧电介质层，且在所述电路侧电介质层上形成与所述导电通孔电接触的多个电路侧导体；
在所述电路侧上形成具有与所述导电通孔对准的开口的外部电介质层；
移除所述背侧的若干部分以暴露所述导电通孔的端子部分及表面，所述端子部分及表面在所述背侧上具有高度X；
在所述背侧上沉积聚合物层以囊封所述端子部分，其中所述聚合物层具有等于或大于所述高度X的厚度；
对所述聚合物层进行平面化以形成经平面化聚合物表面，且对所述端子部分的所述表面进行平面化以形成嵌入于所述聚合物层中的具有由所述端子部分的所述表面形成的经平面化接触器的自对准导体；
将所述平面化步骤控制为终止于所述端子部分的所述表面处；
在所述经平面化聚合物表面上形成与所述经平面化接触器电接触的多个再分布导体；及
切割所述半导体晶片以分离所述半导体衬底。
15.根据权利要求14所述的用于制作半导体组件的方法，其中所述移除步骤包含蚀刻。
16.根据权利要求14所述的用于制作半导体组件的方法，其进一步包含在所述移除步骤之前从所述背侧对所述半导体晶片进行薄化。
17.根据权利要求14所述的用于制作半导体组件的方法，其中所述沉积所述聚合物层的步骤包含旋转涂覆。
18.根据权利要求14所述的用于制作半导体组件的方法，其进一步包含在所述聚合物层上形成与所述再分布导体电连通的多个背侧元件。
19.根据权利要求14所述的用于制作半导体组件的方法，其进一步包含在所述再分布导体上形成若干凸块底部金属化层，且在所述凸块底部金属化层上形成若干端子触点。
20.根据权利要求14所述的用于制作半导体组件的方法，其进一步包含在所述再分布导体上形成多个端子触点。
21.一种半导体组件，其包含：
半导体衬底，其具有电路侧及背侧；
所述半导体衬底中的多个导电通孔，每一导电通孔包含通孔、所述通孔中的绝缘层及填充所述通孔的金属；
所述背侧上的经平面化聚合物层，所述经平面化聚合物层的厚度等于从所述背侧延伸的高度X并且具有经平面化聚合物表面；
多个背侧导体，其包含所述导电通孔的嵌入于所述聚合物层中的端子部分和平面化至所述经平面化聚合物层的所述经平面化聚合物表面的经平面化接触器，所述端子部分通过从所述背侧移除所述半导体衬底的若干部分而形成，并且具有所述高度X；及
在所述经平面化接触器上的多个端子触点。
22.根据权利要求21所述的半导体组件，其进一步包含所述聚合物层上的与所述端子部分电接触的多个背侧再分布导体。
23.根据权利要求21所述的半导体组件，其中所述端子部分具有从5μm到10μm的高度。
24.一种堆叠式半导体组件，其包含：
呈堆叠式阵列形式的多个半导体组件，每一半导体组件包含：
半导体衬底，其具有电路侧及背侧；
所述半导体衬底中的多个导电通孔，每一导电通孔包含通孔、所述通孔中的绝缘层及填充所述通孔的金属；
所述半导体衬底的所述电路侧上的电路侧电介质层，其具有与所述导电通孔对准的多个开口；
所述背侧上的经平面化聚合物层，其厚度等于从所述背侧延伸的高度X并且具有经平面化聚合物表面；
多个背侧导体，其包含所述导电通孔的嵌入于所述聚合物层中的端子部分和平面化至所述经平面化聚合物层的所述经平面化聚合物表面的经平面化接触器，所述端子部分通过从所述背侧移除所述半导体衬底的若干部分而形成，并且以所述高度X从所述背侧延伸；及
在所述经平面化接触器上的多个端子触点；
所述半导体组件是借助对准的所述导电通孔背侧到电路侧地堆叠。
25.根据权利要求24所述的堆叠式半导体组件，其中所述多个端子触点接合到所述半导体组件上的所述导电通孔及邻近半导体组件上的所述导电通孔。
26.根据权利要求24所述的堆叠式半导体组件，其进一步包含支撑所述堆叠式阵列的模块衬底。
27.根据权利要求24所述的堆叠式半导体组件，其中所述组件包括第一组件及第二组件，所述第二组件具有接合到所述第一组件上的所述导电通孔的多个端子触点。
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