TWI424512B - 使用無遮罩背側校直於傳導通道之製造半導體元件之方法 - Google Patents

使用無遮罩背側校直於傳導通道之製造半導體元件之方法 Download PDF

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Publication number
TWI424512B
TWI424512B TW099106005A TW99106005A TWI424512B TW I424512 B TWI424512 B TW I424512B TW 099106005 A TW099106005 A TW 099106005A TW 99106005 A TW99106005 A TW 99106005A TW I424512 B TWI424512 B TW I424512B
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Taiwan
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back side
semiconductor
terminal portions
polymer layer
planarized
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TW099106005A
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English (en)
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TW201044477A (en
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Jin Li
Tongbi Jiang
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Micron Technology Inc
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Description

使用無遮罩背側校直於傳導通道之製造半導體元件之方法
半導體元件(諸如晶片尺度封裝)被製造得比前一代元件更薄及更小。同時，對半導體元件之電及封裝要求變得更加嚴格。在半導體元件之製造期間之一個挑戰係在一半導體基板之背側上之組件校直於在電路側上之組件。舉例而言，導電通道使電路側組件(諸如電路側導體及接合銲墊)與背側組件(諸如背側導體及端子觸點)互連。傳導通道變得更小，因此用於使傳導通道校直於背側組件之習用製造製程變得更困難。
圖1A至圖1E圖解說明一半導體製造製程，其中一半導體基板中之傳導通道校直於該基板上之背側特徵係一問題。如圖1A中所示，一半導體晶圓10包括複數個半導體基板12，諸如半導體晶粒。半導體晶圓10以及半導體基板12中之每一者包括一電路側16及一背側18。此外，每一半導體基板12包括自電路側16延伸至其背側18之複數個傳導通道14。每一傳導通道14包含在半導體基板12中之一貫穿通道20，貫穿通道20襯有一通道絕緣體22且填充有一傳導金屬。
亦如圖1A中所示，每一半導體基板12亦包括在電路側16上與傳導通道14電連通之複數個再分佈導體24。再分佈導體24藉由一內部介電層26與半導體基板12隔離，且由一外部介電層28覆蓋。使用一載體黏合劑32將晶圓10附接至一晶圓載體30，該載體黏合劑准許執行背側製造製程(諸如背側薄化及平坦化)。此等製程平坦化基板12，且在傳導通道14之末端上形成經平坦化接觸器42(圖1A)。晶圓載體30亦允許執行其他製程，諸如背側組件(例如，端子觸點)之形成。在本情形中，執行一光圖案化製程以形成與傳導通道14電連通之背側導體34。
如圖1B中所示，藉由將一抗蝕劑層36沈積於晶圓10之背側18上來起始光圖案化製程。可使用諸如旋轉塗佈等一習用製程來沈積抗蝕劑層36。接下來，如圖1C中所示，抗蝕劑層36可經曝露及顯影以在晶圓10之背側18上形成一光罩38。光罩38包括複數個開口40，該等開口應與傳導通道14上之經曝露接觸器42校直。可使用晶圓10之電路側16及背側18上之校直標記達成校直。然而，歸因於傳導通道14之大小及開口40之大小，及習用光曝光設備之限制，難以達成校直。如圖2A中所示，為便於校直，可使得傳導通道14大於光罩38中之開口40(由圖2A中之虛線表示)。舉例而言，傳導通道14可具有約18μm之一內徑(ID)，而光罩38中之開口40可具有約11μm之一外徑(OD)。此允許在傳導通道14之每一側上發生約3.5μm之未校直。
圖2A圖解說明其中傳導通道14之中心及開口40之中心精確校直之最佳校直情況。然而，如圖2B中所示，在實際應用中，光罩38中之開口40未與傳導通道14精確校直。如將進一步闡釋，此情況可致使在導體34(圖2D)與基板12之間形成短路44(圖2D)。如圖2C中所示，光罩38中之開口40可與傳導通道14完全錯位。如將進一步闡釋，此情況可形成 開路。
如圖1D中所示，在形成光罩38之後，可蝕刻接觸器42以移除污染物及自生氧化物層。接下來，如圖1E中所示，可使用諸如無電沈積等一製程在開口40中形成導體34。導體34可包含諸如銅等一高導電率金屬。亦如圖1E中所示，可在導體34上形成用於端子觸點(未顯示)之凸塊底層金屬化層46、48。凸塊底層金屬化層46、48可使用一合適製程(諸如用合適金屬做材料之無電沈積)來形成。
圖2D及圖2E圖解說明由導體34未校直於傳導通道14引起之潛在問題。如圖2D中所示，小量的未校直(例如，<5μm)可導致導體34與半導體基板12之間的短路44。如圖2E中所示，大量的未校直(例如，>9μm)可導致導體34與傳導通道14之間的一開路。
鑒於前述，此項技術中需要用於製造具有背側組件之半導體元件之改良方法。然而，相關技術之前述實例及與其相關之限制意欲係說明性而非排他性。熟習此項技術者在讀取說明書及研究圖式之後，將易於瞭解相關技術之其他限制。
實例性實施例系圖解說明於該等圖之引用圖式中。意欲將本文所揭示之實施例及圖式視為說明性而非限制性。
如本文所使用，「半導體元件」意指一電子組件，其包括具有積體電路及半導體裝置之一半導體基板。「晶圓位準」意指在含有多個半導體元件之一組件(諸如一半導體晶圓)上實施之一製程。「晶片尺度」意指具有與一半導體晶粒之輪廓大致相同之一輪廓之一半導體元件。
參照圖3A至圖3E，圖解說明一種使用無遮罩背側校直於傳導通道之製造半導體元件之方法。如圖3A中所示，可提供一半導體晶圓50。半導體晶圓50包括含有半導體裝置及積體電路之複數個半導體基板52(諸如半導體晶粒)。半導體晶圓50以及半導體基板52中之每一者包括半導體裝置及積體電路位於其中之一電路側54及一背側56。此外，每一半導體基板52包括自電路側54延伸至其背側56之複數個傳導通道58。傳導通道58與半導體基板52中之半導體裝置及積體電路電連通。
如圖3A中所示，每一傳導通道58包含在半導體基板52中之一大致圓形的貫穿通道60，通道60襯有一通道絕緣體62且填充有一傳導金屬。該傳導金屬可包含一高導電率金屬，諸如銅、鎳、金、鋁、鈦、銥、鎢、銀、鉑、鈀、鉭、鉬、鋅、錫、焊料及此等金屬之合金。通道絕緣體62可包含一電絕緣材料，諸如一聚合物(例如，聚醯亞胺)或SiO2 。亦如圖3A中所示，每一半導體基板52亦包括在電路側54上與傳導通道58電連通之複數個電路側再分佈導體66。電路側再分佈導體66藉由一內部介電層64與半導體基板52隔離，且由一外部介電層68覆蓋。
可使用熟知之半導體製造製程形成到目前為止所闡述之全部組件，包括具有半導體裝置及積體電路於其中之半導體基板52、傳導通道58、電路側再分佈導體66及介電層64、68。舉例而言，可藉由蝕刻或雷射加工通道60穿過基板52來形成傳導通道58；使用諸如聚合物沈積或氧化物生長等一製程在該等通道中形成通道絕緣體62；及然後使用諸如電解沈積、無電沈積、CVD、模板印刷或絲網印刷等一製程在該等通道中沈積一金屬。用於形成傳導通道58之另一方法係形成部分穿過基板52之通道60，用傳導金屬填充通道60，及然後使用諸如蝕刻或鋸割等一製程薄化基板52以曝露該傳導金屬。
使用一載體黏合劑72(諸如一雙側膠帶)將晶圓50附接至一晶圓載體70，該載體黏合劑可使用UV輻射去接合。晶圓載體70准許執行背側製造製程，諸如背側薄化。可使用一機械平坦化設備(諸如一研磨機)或一化學機械平坦化(CMP)設備執行薄化以形成一經薄化之背側56T。在背側薄化之後，晶圓50可具有自約100 μm至約725 μm之一厚度。晶圓載體70亦允許執行其他背側製程，諸如形成背側組件(例如，端子觸點)。
接下來，如圖3B及圖4A中所示，執行一移除步驟以移除基板52之背側56之部分且曝露傳導通道58之端子部分76(圖4A)。可使用一濕式蝕刻製程、一乾式蝕刻製程或一電漿蝕刻製程(諸如反應性離子蝕刻(REI))來執行該移除步驟。舉例而言，為蝕刻由矽製成之一半導體基板52，可使用四甲基氫氧化銨(TMAH)溶液或(替代地)氫氧化鉀(KOH)溶液來執行一濕式蝕刻製程。如圖4A中所示，可執行該移除步驟以將半導體基板52移除約5 μm至10 μm，使傳導通道58之所曝露端子部分76自經薄化背側56T之一高度X為自5 μm至10 μm。
接下來，如圖3C及圖4B中所示，執行一聚合物沈積步驟以形成一聚合物層78，其覆蓋半導體基板52之經薄化背側56T且囊封傳導通道58之所曝露端子部分76。聚合物層78可包含諸如聚矽氧、聚醯亞胺或環氧樹脂等一可固化聚合物。此外，聚合物層78可包括填充劑(諸如矽酸鹽)以用於調整熱膨脹係數(CTE)及聚合物材料之黏度。可使用諸如旋轉塗佈、噴嘴沈積、絲網印刷、模板印刷或光微影等一合適製程將聚合物層78沈積於經薄化背側56T上。舉例而言，藉助旋轉塗佈，可將一旋塗聚合物應用至半導體晶圓50之經薄化背側56T，然後使用一旋轉塗佈器迅速地旋塗該旋塗聚合物以使其排出液體。在旋轉塗佈之後該聚合物材料可固化。所得沈積材料之厚度相依於溶液之黏度及旋轉速度。此厚度經選擇以囊封傳導通道58之端子部分76(圖4A)。舉例而言，聚合物層78可具有自10 μm至25 μm之一厚度。
接下來，如圖3D及圖4C中所示，執行一平坦化步驟以在傳導通道58上形成經平坦化接觸器74。該平坦化步驟亦平坦化聚合物層78且形成一經平坦化之聚合物表面80。可使用化學機械平坦化(CMP)來執行該平坦化步驟。舉例而言，合適CMP設備可購自製造商，諸如Westech、SEZ、電漿拋光系統公司(Plasma Polishing Systems)或TRUSI。亦可藉由使用一研磨機之機械平坦化或使用一表面平坦單元(諸如一DISCO全自動表面平坦單元)之飛刀切削來執行該平坦化步驟。該平坦化步驟亦可經控制以終止於傳導通道58之表面處或移除少量傳導通道58。在該平坦化步驟之後，聚合物層78之一代表性厚度可自5 μm至10 μm。
接下來，如圖3E及圖4D中所示，執行一金屬化步驟以在傳導通道58之經平坦化接觸器74上形成凸塊底層金屬化層(UBM)82、84。可使用一沈積或鍍覆製程(諸如無電沈積、電解沈積或CVD)來形成凸塊底層金屬化層(UBM)82、84。凸塊底層金屬化(UBM)層82、84可包含經組態以提供用於形成或接合端子觸點86(圖5A)之表面之一個或多個層。舉例而言，凸塊底層金屬化(UBM)層82可包含由諸如鎳、鋅、鉻或鈀等一金屬形成之一黏合層。凸塊底層金屬化層84可包含由諸如錫、鈀或金等一金屬形成之一焊料可濕潤之金屬層。
用於製造半導體元件(圖3A至圖3E)之本發明方法消除先前技術方法(圖1A至圖1E)之光罩38(圖1C)。此外，本發明方法(圖3A至圖3E)消除光罩38(圖1C)校直於傳導通道14且消除導體34(圖1E)之形成。藉助本發明方法(圖3A至圖3E)，傳導通道58之端子部分76(圖4A)形成導體，其等自校直於傳導通道58。此允許傳導通道58具有約10 μm或更少之一OD。此外，不存在形成一短路44(圖2D)或形成一開路(圖2E)之可能性。就此而言，聚合物層78在端子部分76(圖4A)與半導體基板52之間提供額外電絕緣，因此不可能發生短路。
參照圖5A及圖5B，可執行額外背側製程以形成與傳導通道58電連通之背側組件。舉例而言，如圖5A中所示，端子觸點86可形成於凸塊底層金屬化層82、84上。端子觸點86可包含使用一合適沈積製程(諸如模板印刷或一焊料合金之回流)形成於凸塊底層金屬化層82、84上之焊料、另一金屬或一傳導聚合物。如圖5B中所示，亦可在聚合物層78之經平坦化表面80上形成與傳導通道58電連通之背側再分佈導體88。可使用一合適製程(諸如穿過一遮罩之無電沈積或藉由圖案化一經沈積金屬層)來形成背側再分佈導體88。此外，大致如先前所闡述，端子觸點86可形成於背側再分佈導體88上。
在背側處理步驟之後，半導體晶圓50可經切割以形成複數個晶片尺度半導體元件90(圖6)。可使用諸如雷射、鋸割、沖水或蝕刻等一製程完成切割。在該切割步驟之後，可自載體70移除半導體元件90(圖6)。
如圖6A至圖6C中所示，每一半導體元件90包括具有複數個傳導通道58之一半導體基板52。每一傳導通道58包括一端子部分76，其形成一自校直背側導體，該導體大致相當於一先前技術背側導體34(圖1E)。此外，半導體元件90包括囊封傳導通道58之端子部分76之一背側聚合物層78及與傳導通道58電連通之端子觸點86。半導體元件90亦包括一內部介電層64、與傳導通道58電連通之電路側再分佈導體66及一電路側外部介電層68。外部介電層68可包括與傳導通道58校直(或替代地具有與傳導通道58電通信之觸點)之開口92(圖6C)，其等准許多個半導體元件90之堆疊。
參照圖7，一堆疊半導體元件96包括一堆疊陣列中之複數個半導體元件90，包括安裝至一模組基板94之一上部元件90-1、一中間元件90-2及一下部元件90-3。上部元件90-1上之端子觸點86可接合至中間元件90-2上之傳導通道58，及中間元件90-2上之端子觸點86可接合至下部元件90-3上之傳導通道58。此外，下部元件90-3上之端子觸點86可接合至模組基板94上之電極。進一步地，可在元件90-1、90-2、90-3與模組基板94之間形成底填層98。元件90-1、90-2、90-3上之傳導通道58之校直便於堆疊元件56之製造。
儘管上文已論述大量實例性態樣及實施例，但熟習此項技術者將意識到某些修改、置換、添加或其子組合。因此意欲將以下隨附申請專利範圍及下文引入之申請專利範圍闡釋為將所有此等修改、置換、添加及子組合包括在其真實精神及範疇中。
10．．．半導體晶圓
12．．．半導體基板
14．．．傳導通道
16．．．電路側
18．．．背側
20．．．貫穿通道
22．．．通道絕緣體
24．．．再分佈導體
26．．．內介電層
28．．．外介電層
30．．．晶圓載體
32．．．載體黏合劑
34．．．背側導體
36．．．抗蝕劑層
38．．．光罩
40．．．開口
42．．．經曝露導體
44．．．短路
46．．．凸塊底層金屬化層
48．．．凸塊底層金屬化層
50．．．半導體晶圓
52．．．半導體基板
54．．．電路側
56．．．背側
56T．．．經薄化之背側
58．．．傳導通道
60．．．通道
62．．．通道絕緣體
64．．．內介電層
66．．．電路側再分佈導體
68．．．外電介指質層
70．．．晶圓載體
72．．．載體黏合劑
74．．．經平坦化之導體
76．．．端子部分
78．．．聚合物層
80．．．經平坦化之表面
82．．．凸塊底層金屬化層
84．．．凸塊底層金屬化層
86．．．端子觸點
88．．．背側再分佈導體
90．．．晶片尺度半導體元件
90-1．．．上部元件
90-2．．．中間元件
90-3．．．下部元件
92．．．開口
94．．．模組基板
96．．．堆疊半導體元件
98．．．下填充層
圖1A至圖1E係圖解說明使用一背側光校直步驟製造半導體元件之一先前技術方法中之步驟之示意性截面圖；
圖2A係沿圖1A之線2A-2A截取之一放大示意性截面圖，其圖解說明先前技術方法中之一傳導通道；
圖2B係沿圖1C之線2B-2B截取之一放大示意性截面圖，其圖解說明傳導通道與一背側抗蝕劑開口之間的最佳校直；
圖2C係相當於圖2B之一放大示意性截面圖，其圖解說明傳導通道與背側抗蝕劑開口之間的未校直；
圖2D係沿圖1F之線2D截取之一放大示意性截面圖，其圖解說明傳導通道與一背側導體之間的產生一短路之未校直；
圖2E係相當於圖2D之一放大示意性截面圖，其圖解說明傳導通道與一背側導體之間的產生一開路之未校直；
圖3A至圖3E係圖解說明一種使用無遮罩背側傳導通道校直製造半導體元件之方法之示意性截面圖；
圖4A係沿圖3B之線4A截取之一放大示意性截面圖，其圖解說明在一回蝕步驟之後的一傳導通道；
圖4B係沿圖3C之線4B截取之一放大示意性剖面圖，其圖解說明在一聚合物沈積步驟之後的傳導通道；
圖4C係沿圖3D之線4C截取之一放大示意性截面圖，其圖解說明在一平坦化步驟之後的傳導通道；
圖4D係沿圖3E之線4D截取之一放大示意性截面圖，其圖解說明傳導通道與一背側導體之校直；
圖5A係等效於圖4A之一放大示意性截面圖，其圖解說明與背側導體電連通之一背側端子觸點；
圖5B係相當於圖4A之一放大示意性截面圖，其圖解說明一背側再分佈導體及與該背側導體電連通之端子觸點；
圖6A係根據圖3A至圖3E之方法製造之一半導體元件之一平面圖；
圖6B係半導體元件之一側視圖；
圖6C係半導體元件沿圖6B之剖切線6C-6C截取之一截面圖；及
圖7係根據圖3A至圖3E之方法製造之堆疊元件之一示意性側視圖。
52．．．半導體基板
56T．．．經薄化之背側
58．．．傳導通道
60．．．通道
62．．．通道絕緣體
74．．．經平坦化之導體
78．．．聚合物層
80．．．經平坦化之聚合物表面
82．．．凸塊底層金屬化層
84．．．凸塊底層金屬化層

Claims (30)

  1. 一種用於製造一半導體元件之方法，其包含：提供具有一電路側、一背側及複數個傳導通道之一半導體基板，該等傳導通道包含自該電路側延伸至該背側之多個電氣絕緣通道，其至少部份地填充有一金屬；自該背側移除該半導體基板之部分以曝露自該背側延伸一高度X之該等傳導通道之多個端子部分及多個表面；將一聚合物層沈積於該背側上以囊封該等端子部分及該等端子部分之該等表面；及平坦化該聚合物層及該等端子部分至少至該等端子部分之該等表面。
  2. 如請求項1之方法，其進一步包含在該等端子部分之該等表面上形成複數個端子觸點。
  3. 如請求項1之方法，其進一步包含在該聚合物層上形成與該等端子部分之該等表面電接觸之複數個背側再分佈導體。
  4. 如請求項1之方法，其中該平坦化步驟移除至少一些該等傳導通道之該金屬且平坦化該等表面。
  5. 如請求項1之方法，其進一步包含在該移除步驟之前自該背側薄化該半導體基板。
  6. 一種用於製造一半導體元件之方法，其包含：提供具有一電路側、一背側及複數個傳導通道之一半導體基板，該複數個傳導通道包含在自該電路側至該背 側之該半導體基板中之填充有一金屬之電絕緣貫穿通道；自該背側蝕刻該半導體基板以曝露自該背側延伸一高度X之該等傳導通道之多個端子部分及多個表面；將一聚合物層沈積於該背側上以囊封該等端子部分及該等端子部分之該等表面；及平坦化該聚合物及該等傳導通道之該等端子部分之該等表面以形成多個自校直導體，該等自校直導體包含嵌入於該聚合物層及由該等端子部分之該等表面所形成之經平坦化接觸器中之該金屬。
  7. 如請求項6之方法，其進一步包含在該等接觸器上形成複數個金屬化層且在該等金屬化層上形成若干端子觸點。
  8. 如請求項6之方法，其進一步包含在該聚合物層上形成與該等接觸器電接觸之複數個背側再分佈導體。
  9. 如請求項6之方法，其進一步包含在該蝕刻步驟之前自該背側薄化該半導體基板。
  10. 如請求項6之方法，其中使用一旋塗製程執行該沈積步驟。
  11. 如請求項6之方法，其中該提供步驟在附接至一晶圓載體之一半導體晶圓上提供該半導體基板，且在附接至該載體之該半導體晶圓上執行該蝕刻、沈積及平坦化步驟。
  12. 如請求項6之方法，其中該蝕刻步驟移除該半導體基板 之自約5μm至10μm。
  13. 如請求項6之方法，其中該端子部分具有約5μm至10μm之一高度。
  14. 一種用於製造半導體元件之方法，其包含：提供一半導體晶圓，該半導體晶圓包含一電路側、一背側及具有複數個積體電路之複數個半導體基板；形成貫穿自該電路側至該背側之該半導體基板之與該等積體電路電連通之複數個傳導通道，每一該傳導通道包含一通道、該通道中之一絕緣層及填充該通道之一金屬；移除該背側之部分以曝露該等傳導通道之多個端子部分及多個表面，該等傳導通道具有一在該背側上之5μm至10μm之一高度X；將一聚合物層沈積於該背側上以囊封該等端子部分，該等端子部分具有一在該背側上之10μm至25μm之一厚度；平坦化該聚合物層及該等端子部分之該等表面以形成多個自校直導體，該等自校直導體嵌入於具有由該等端子部分之該等表面所形成之經平坦化接觸器之該聚合物層中；及切割該半導體晶圓以分離該等半導體基板。
  15. 如請求項14之方法，其中該移除步驟包含蝕刻。
  16. 如請求項14之方法，其進一步包含在該等移除步驟之前自該背側薄化該半導體晶圓。
  17. 如請求項14之方法，其中該沈積該聚合物層步驟包含旋轉塗佈。
  18. 如請求項14之方法，其進一步包含在該聚合物層上形成與該等導體電連通之複數個背側組件。
  19. 如請求項14之方法，其進一步包含在該等導體上形成若干凸塊底層金屬化層且在該等凸塊底層金屬化層上形成若干端子觸點。
  20. 如請求項14之方法，其進一步包含在該聚合物層上形成與該等導體電接觸之若干背側再分佈導體。
  21. 一種半導體元件，其包含：一半導體基板，其具有一電路側及一背側；該基板中之複數個傳導通道，每一該傳導通道包含一通道、該通道中之一絕緣層及填充該通道之一金屬；具有一厚度及一經平坦化聚合物表面之該背側上之一經平坦化聚合物層；及複數個背側導體，其自校至該等傳導通道，該等傳導通道包含該等傳導通道之該金屬之多個端子部分及在該等端子部分上之多個經平坦化接觸器，其經平坦化至該經平坦化聚合物層之該經平坦化聚合物表面，每一該背側導體包含嵌入於該經平坦化聚合物層中之一端子部分及一經平坦化接觸器；及接合至該等經平坦化接觸器之複數個端子接觸器。
  22. 如請求項21之半導體元件，其中該等背側導體包含若干經平坦化導體。
  23. 如請求項21之半導體元件，其進一步包含在該等背側導體上之複數個端子觸點。
  24. 如請求項21之半導體元件，其進一步包含在該聚合物層上之與該等端子部分電接觸之複數個背側再分佈導體。
  25. 如請求項21之半導體元件，其中該等端子部分具有自5μm至10μm之一高度。
  26. 一種堆疊半導體元件，其包含：一堆疊陣列中之複數個半導體元件，每一半導體元件包含：一半導體基板，其具有一電路側及一背側；該半導體基板中之複數個傳導通道，每一該傳導通道包含一通道、該通道中之一絕緣層及填充該通道之一金屬；該背側上之具有一厚度之一經平坦化聚合物層；及複數個背側導體，其自校至該等傳導通道，該等傳導通道包含嵌入於該經平坦化聚合物層中之該等傳導通道之該金屬之多個端子部分，該經平坦化聚合物層具有等於該經平坦化聚合物層之該厚度之一高度X及在該等端子部分上之多個經平坦化接觸器；及接合至該等經平坦化接觸器之複數個端子觸點；該等半導體元件堆疊背側校直於具有該等傳導通道之電路側及堆疊在一第一半導體元件上之該等端子觸點，其接合至在一毗鄰第二半導體元件上之該等傳導通道。
  27. 如請求項26之堆疊半導體元件，其進一步包含一電路側 介電層在該半導體基板之該電路側上，該半導體基板具有與該等傳導通道校直之複數個開口。
  28. 如請求項26之堆疊半導體元件，其中該等端子觸點包含接合至該等經平坦化接觸器之一金屬、一焊料或一傳導聚合物。
  29. 如請求項26之堆疊半導體元件，其進一步包含支援該堆疊陣列之一模組基板。
  30. 如請求項26之堆疊半導體元件，其進一步包含在安裝至一模組基板之該堆疊陣列中之一第三半導體元件。
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