TWI703699B - 半導體元件及其形成方法 - Google Patents

半導體元件及其形成方法 Download PDF

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TWI703699B
TWI703699B TW108112779A TW108112779A TWI703699B TW I703699 B TWI703699 B TW I703699B TW 108112779 A TW108112779 A TW 108112779A TW 108112779 A TW108112779 A TW 108112779A TW I703699 B TWI703699 B TW I703699B
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Taiwan
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conductive
bumps
holes
hole
bump
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TW108112779A
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TW202013655A (zh
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曾英誠
蔡豪益
黃育智
劉家宏
郭婷婷
戴志軒
吳邦立
賴季暉
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件，包含：多個被動電子組件，位於基底中；以及內連線結構，位於多個被動電子組件上方，內連線結構的多個導電特徵電耦合至多個被動電子組件。內連線結構的多個導電特徵包含：第一導電線，位於基底上方；導電凸塊，位於第一導電線上方，其中在平面圖中，導電凸塊具有第一細長形狀且完全安置於第一導電線的邊界內；以及第一通孔，位於第一導電線與導電凸塊之間，第一通孔電性連接至第一導電線及導電凸塊，其中在平面圖中，第一通孔具有第二細長形狀且完全安置於導電凸塊的邊界內。

Description

半導體元件及其形成方法
本發明的實施例是有關於半導體元件及其形成方法。
半導體行業歸因於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度的持續改良而已經歷快速增長。在很大程度上，積體密度的此改良來自最小構件大小的逐漸減小，此允許將更多的組件整合至給定區域中。由於近來對甚至更小的電子元件的需求增大，因而對半導體晶粒的更小且更具創造性的封裝技術的需求增大。
這些封裝技術的實例為積體扇出型(integrated fan-out；InFO)封裝技術。在InFO封裝中，將晶粒嵌入於模塑材料中。重佈線結構形成於晶粒的第一側上且電耦合至晶粒。重佈線結構延伸超出晶粒的側向範圍。重佈線結構的導電特徵(諸如導電線或導電墊)允許在超出晶粒的邊界的位置處與晶粒的電性連接。
積體被動元件(Integrated passive devices；IPD)及技術近來變得流行。可將多種被動元件，諸如電容器、電阻器、電感器、平衡-不平衡轉換器(baluns)、耦合器、分流器、濾波器或雙 工器整合於IPD中。由於高水準的整合，因此相較於例如表面安裝元件(surface mount devices；SMD)，IDP可實現佔據面積的顯著減小。同時，IPD可提供優於SMD的顯著成本減少及效能改良。
本發明實施例的一種半導體元件，包括多個被動電子組件以及內連線結構。多個被動電子組件位於基底中。內連線結構位於所述多個被動電子組件上方，所述內連線結構的多個導電特徵電耦合至所述多個被動電子組件，所述內連線結構的所述多個導電特徵包括第一導電線、導電凸塊以及第一通孔。第一導電線位於所述基底上方。導電凸塊位於所述第一導電線上方，其中在平面圖中，所述導電凸塊具有第一細長形狀且完全安置於所述第一導電線的邊界內。第一通孔位於所述第一導電線與所述導電凸塊之間，所述第一通孔電性連接至所述第一導電線及所述導電凸塊，其中在所述平面圖中，所述第一通孔具有第二細長形狀且完全安置於所述導電凸塊的邊界內。
本發明實施例的一種半導體元件，包括基底、多個電子組件以及多個金屬化物層。多個電子組件位於所述基底中。多個金屬化物層位於所述多個電子組件上方且電耦合至所述多個電子組件，其中所述多個金屬化物層包括多個第一通孔及在所述多個第一通孔上方的多個導電凸塊，所述多個導電凸塊電耦合至所述多個第一通孔，其中所述多個第一通孔在所述多個金屬化物層的最頂通孔層中。所述多個導電凸塊包括第一組凸塊、第二組凸塊以及第三組凸塊。第一組凸塊配置為耦合至電力供應器的第一極 性。第二組凸塊配置為耦合至所述電力供應器的第二極性。第三組凸塊配置為耦合至所述電力供應器的所述第一極性，其中所述第二組凸塊在所述第一組凸塊與所述第三組凸塊之間。
本發明實施例的一種半導體元件的形成方法，包括：在基底中形成多個被動電子組件；在所述基底上方形成多個第一通孔，所述多個第一通孔具有細長形狀且電耦合至所述多個被動電子組件；以及在所述多個第一通孔上方形成多個導電凸塊，所述多個導電凸塊電耦合至所述多個第一通孔中的相應通孔，所述多個導電凸塊具有所述細長形狀。形成所述多個導電凸塊包括：在第一區中形成多個第一導電凸塊，所述多個第一導電凸塊配置為耦合至電力供應器的第一極性；在鄰接於所述第一區的第二區中形成多個第二導電凸塊，所述多個第二導電凸塊配置為耦合至所述電力供應器的第二極性；以及在鄰接於所述第二區的第三區中形成多個第三導電凸塊，所述多個第三導電凸塊配置為耦合至所述電力供應器的所述第一極性，其中所述第二區在所述第一區與所述第三區之間。
100、100A、100B、400:半導體元件
101、261:基底
102、102G、102P:接觸墊
103:電子組件
105、109、113、117:介電層
107、115、115G、115P:導電線
110:內連線結構
111、119:通孔
121、121P、121G:導電凸塊
123、173:焊料區
133:電感器
141、141A、141B:電流路徑
143、143A、143B、143C:導電路徑
149、149G、149P、214:導電特徵
200:底部封裝體
210:背側重佈線結構
219:導電柱
220:晶粒
230、265:模塑材料
240:前側重佈線結構
255:外部連接件
262:半導體晶粒
263:導電墊
267:接線
268:導電接合部
300:頂部封裝體
500:半導體封裝體
1010、1020、1030:區塊
A-A、B-B、C-C:截面
D1、D2:偏移
L1、L2、L3:長度
PolG、PolG_P、PolG_G:極性組
W1、W2、W3:寬度
結合隨附圖式閱讀以下詳細描述時會最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種構件未按比例繪製。事實上，可出於論述清楚起見，任意地增加或減小各種構件的尺寸。
圖1A至圖1D說明根據一實施例的半導體元件的一部分的各種視圖。
圖2A說明在一實施例中的半導體元件的平面圖。
圖2B說明圖2A的半導體元件的一部分的放大圖。
圖3A說明根據一些實施例的半導體元件的多個電流路徑。
圖3B說明並聯連接的六個電感器的示意圖。
圖4說明根據一實施例的半導體元件的平面圖。
圖5說明根據一些實施例的半導體封裝體的截面圖。
圖6說明根據一些實施例的用於形成半導體元件的方法的流程圖。
以下揭露內容提供用於實施本發明的不同特徵的多個不同實施例或實例。以下描述組件及配置的特定實例以簡化本揭露內容。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件在第二構件上方或上的形成可包含第一構件及第二構件直接接觸地形成的實施例，且亦可包含額外構件可形成於第一構件與第二構件之間使得第一構件與第二構件可不直接接觸的實施例。
另外，為易於描述，本文中可使用空間相對術語，諸如「在...下方」、「在...下」、「低於」、「在...上方」、「高於」以及類似術語，以描述如所圖式中所說明的一個元件或構件與另一(一些)元件或構件的關係。除圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞同樣可相應地進行解釋。除非另外說明，否則在本文的整 個描述中，相同附圖標號是指相同元件。
在一實施例中，積體被動元件(IPD)包含形成在IPD的基底中的多個被動電子組件(例如，電容器)及在多個被動電子組件上方且電耦合至多個被動電子組件的內連線結構。內連線結構包括多個導電線、多個通孔以及多個導電凸塊。在一些實施例中，IPD的多個導電凸塊包含三個或大於三個極性組，其中每一極性組包含多個導電凸塊，所述多個導電凸塊配置為耦合至電力供應器的同一極性(例如，諸如+5V的供應電壓，或諸如電接地的參考電壓)。藉由具有三個或大於三個極性組，IPD的等效串聯電感(equivalent series inductance；ESL)減小。在一些實施例中，將內連線結構的最頂通孔層中的多個通孔連接至多個導電凸塊，且通孔的面積(例如，截面面積)在導電凸塊的面積(例如，截面面積)的約50%與約90%之間。藉由在最頂通孔層中具有大的通孔，以減小IPD的等效串聯電阻(equivalent series resistance；ESR)。
圖1A至圖1D說明根據一些實施例的半導體元件100的一部分的各種視圖(例如，截面圖及平面圖)。特定言之，圖1A說明沿圖1B中的截面B-B的半導體元件100的截面圖，且圖1B說明沿圖1A中的截面A-A的半導體元件100的平面圖。圖1C說明在一實施例中的沿圖1A中的截面C-C的半導體元件100的平面圖。圖1D說明在另一實施例中的沿圖1A中的截面C-C的半導體元件100的平面圖。應注意，由於圖1A至圖1D說明半導體元件100的一部分，因此半導體元件100可具有安置於超出所說明部分的面積中的額外元件(例如，電子組件103、導電凸塊121)。
半導體元件100可為具有電子組件103(諸如電容器)陣列的積體被動元件(IPD)，所述電子組件陣列整合於半導體元件100中。因此，半導體元件100亦可稱為IPD。下文論述使用電容器作為整合於半導體元件100中的被動電子組件(例如，電子組件103)的實例。本揭露內容的原理亦可應用於具有其他類型的被動電子組件(諸如電阻器、電感器以及類似者)的IPD。
如圖1A中所說明，半導體元件100包含形成於基底101中/上的電子組件103。內連線結構110形成於電子組件103上方及基底101上方，所述內連線結構包含形成於多個介電層(例如，介電層105、介電層109、介電層113以及介電層117)中的導電特徵，諸如導電線(例如，導電線107、導電線115)及通孔(例如，通孔111、通孔119)。內連線結構110亦包含導電凸塊121(例如，導電凸塊121P/導電凸塊121G)。內連線結構110電耦合至電子組件103。如圖1A中所說明，導電凸塊121(例如，導電凸塊121P、導電凸塊121G)形成於內連線結構110的通孔119的最頂層上方且電耦合至所述內連線結構的所述通孔119的所述最頂層。可視情況存在的焊料區123形成於導電凸塊121上方。
基底101可由諸如矽的摻雜或未摻雜的半導體材料或絕緣層上半導體(semiconductor-on-insulator；SOI)基底的主動層形成。基底101可包含其他半導體材料，諸如鍺；包含碳化矽、砷化鎵、磷化鎵、氮化鎵、磷化銦、砷化銦及/或銻化銦的合成半導體；包含矽鍺(SiGe)、磷化鎵砷(GaAsP)、砷化銦鋁(AlInAs)、砷化鎵鋁(AlGaAs)、砷化銦鎵(GaInAs)、磷化銦鎵(GaInP)及/或磷砷化銦鎵(GaInAsP)的合金半導體；或其組合。亦可使 用其他基底，諸如多層基底或梯度基底。
在圖1A中，使用適合製造技術使多個電子組件103(諸如被動電子組件)形成於基底101中或所述基底上。在所說明實施例中，多個電子組件103為多個電容器，且多個電容器中的每一者具有充當電容器的兩個端子的兩個接觸墊102(例如，接觸墊102G、接觸墊102P)。多個電子組件103中的每一者可包括基底及基底上方的一或多個介電層。接觸墊102表示用於與電子組件103電連接的接觸件。接觸墊102可包括鋁，但可替代地使用諸如銅的其他材料。每一電子組件103(例如，電容器)的接觸墊102配置為電耦合至電力供應器的兩個不同極性。舉例而言，接觸墊102P可配置為耦合至諸如+5V或+3V的供應電壓，且接觸墊102G可配置為耦合至諸如電接地的參考電壓。在本文中的整個論述中，數字後的字母「P」(例如，102P)用於指示導電特徵(例如，接觸墊102P)經組態以耦合至供應電壓(例如，+5V、+3V)，而數字後的字母「G」(例如，102G)用於指示導電特徵(例如，接觸墊102G)經組態以耦合至參考電壓(例如，電接地)
在圖1A的實例中，內連線結構110包含形成於多個介電層(例如，介電層105、介電層109、介電層113以及介電層117)中的多個金屬化物層，諸如導電線(例如，導電線107、導電線115)層及通孔(例如，通孔111、通孔119)層。內連線結構亦包含導電凸塊121(例如，導電凸塊121P/導電凸塊121G)。在圖1A中，內連線結構110包含多個導電線及多個通孔的多個交替層，其中最底金屬化物層為導電線107的層。在一些實施例中，導電凸塊121及通孔119形成於同一製程步驟中，在此情況下， 內連線結構110的最頂金屬化物層可包含導電凸塊121及通孔119。在本文的整個論述中，通孔119可稱為內連線結構110的最頂通孔層。圖1A中所展示的內連線結構110的結構(例如，內連線結構110中的金屬化物層的數目及位置)僅為實例而並非限制性的。其他結構亦為可能的且完全意欲包含於本揭露內容的範疇內。
仍參看圖1A，內連線結構110的介電層105、介電層109、介電層113以及介電層117可由下述者形成：聚合物，諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或類似者；氮化物，諸如氮化矽或類似者；氧化物，諸如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass；PSG)、硼矽酸鹽玻璃(borosilicate glass；BSG)、硼摻磷矽酸鹽玻璃(boron-doped phosphosilicate glass；BPSG)或類似者；或其組合，且可例如藉由旋塗、層壓、化學氣相沈積(chemical vapor deposition；CVD)或類似者形成。可經由任何適合的製程，諸如沈積、鑲嵌、雙金屬鑲嵌或類似者來形成內連線結構的導電特徵，諸如導電線107/導電線115及通孔111/通孔119。
圖1B說明在一實施例中的沿截面A-A的圖1A的半導體元件100的一部分的平面圖。如圖1B中所說明，多個電子組件103的陣列形成於基底101中/上，且多個電子組件103中的每一者具有接觸墊102P及接觸墊102G。圖1B進一步說明內連線結構110的最底層中的導電線107，其未在截面A-A中且以虛線說明。如圖1B中所說明，多個接觸墊102中的每一者電耦合至導電線107，且兩個相鄰電子組件103的接觸墊102G(例如，連接至電 接地)藉由導電線107耦合至一起。圖1B中所說明的電子組件103的陣列的形狀及大小以及電連接件僅為非限制性實例。其他形狀、大小以及電連接件亦為可能的且完全意欲包含於本揭露內容的範疇內。舉例而言，半導體元件100的多個電子組件103可形成於一列(例如，沿線對準)中，如圖1D中所說明。
返回參看圖1A，導電凸塊121(例如，導電凸塊121P、導電凸塊121G)形成於內連線結構110的通孔119上方且電耦合至所述內連線結構的所述通孔119。導電凸塊121充當半導體元件100的凸塊下金屬(under-bump metallurgy；UBM)結構，且因此亦可稱為半導體元件100的UBM結構。可使用用於形成導電凸塊121的任何適合的方法。導電凸塊121P及導電凸塊121G配置為耦合至電力供應器的兩個不同極性。舉例而言，導電凸塊121P可配置為耦合至供應電壓，例如+5V或+3V，且導電凸塊121G可配置為耦合至參考電壓，諸如電接地。
在一例示性實施例中，導電凸塊121及通孔119形成於同一製程步驟中。舉例而言，在形成介電層117後，多個第一開口形成於介電層117中以暴露下方導電線115。第一開口的位置對應於隨後形成的通孔119的位置。接著，晶種層形成於介電層117上方且沿介電層117中的第一開口的內部形成。接著，圖案化罩幕層(例如，光阻)形成於晶種層上方，且一或多種導電材料(諸如銅)形成(例如，藉由電鍍)於圖案化罩幕層的開口中且形成於晶種層上方。接著，將罩幕層移除，且亦將晶種層上未形成一或多種導電材料的部分移除。
在所說明的實施例中，內連線結構110包括多個電並聯 導電路徑(electrically parallel conductive path)143(例如，導電路徑143A、導電路徑143B、導電路徑143C)，其中的每一者包含多個導電特徵(例如，導電線及通孔)，所述多個導電特徵電耦合於導電凸塊121與電子組件103的至少一個接觸墊102之間。在圖1A的實例中，導電凸塊121G下方的導電線(例如，導電線115及導電線107)及通孔(例如，通孔119及通孔111)在導電凸塊121G與接觸墊102G之間形成第一導電路徑143A。在圖1A的實例中，第一導電路徑143A耦合至兩個鄰接電子組件103的接觸墊102G。類似地，兩個額外導電路徑143B及導電路徑143C由耦合於導電凸塊121P與相應接觸墊102P之間的導電線(例如，導電線115及導電線107)及通孔(例如，通孔119及通孔111)形成。
在一些實施例中，內連線結構110中沒有連接內連線結構110的不同導電路徑143的導電特徵(例如，導電線或通孔)。換言之，內連線結構110的導電路徑143並未彼此交叉(例如，並未實體地相交)，因此導電路徑143稱為電並聯導電路徑。因此，流動於半導體元件100中的電流(例如，正電流，參看圖1A中的電流路徑141A或電流路徑141B)在離開導電凸塊121P後，可僅在通過電子組件103後返回至導電凸塊121G。舉例而言，參看圖1A中的電流路徑141A，電流自導電凸塊121P向下行進，朝向接觸墊102P穿過導電路徑143B，穿過電子組件103、自接觸墊102G向上行進，穿過導電路徑143A，且返回導電凸塊121G處。
在所說明的實施例中，電子組件103的陣列是並聯連接的電容器。如下文將將更詳細地論述，經由導電凸塊121P將接觸墊102P電耦合至供應電壓，且經由導電凸塊121G將接觸墊102G 電耦合至電接地。本領域的技術人員將瞭解，各自具有電容C的N個並聯連接的電容器的等效電容為N×C。因此，藉由並聯連接多個電容器，半導體元件100能夠將更大等效電容(例如，0.001微法(μF)至100微法)提供至外部電路或外部元件。
隨著半導體元件的大小在後期處理技術中持續縮小且隨著半導體元件的速度(例如，時脈速度)持續增大，半導體元件的寄生特徵(parasitic characteristic)可對半導體元件的效能造成不可忽略的影響，且因此應在半導體元件的設計及製造期間考慮所述寄生特徵。舉例而言，對於具有積體電容器的IPD，IPD元件的等效串聯電感(ESL)可限制(例如，降低)IPD的操作頻率，因為當在高於共振頻率的頻率下操作時，由於ESL，IPD可表現為電感器而非電容器。另外，IPD的等效串聯電阻(ESR)可藉由消耗電力來降低IPD的效率。本文中所揭露的各種實施例設計有利地減小半導體元件的ESL及ESR，因此改良半導體元件的效能。
圖1C說明在一實施例中的沿圖1A中的截面C-C的半導體元件100的平面圖。為簡單起見，圖1C中並未說明半導體元件100的所有構件。另外，為說明各個構件的相對位置，以虛線說明截面C-C中並沒有的一些構件(例如，通孔119、導電線115、通孔111以及導電線107)。
在圖1C中，經由相應通孔119將多個導電凸塊121(例如，導電凸塊121P、導電凸塊121G)中的每一者電耦合至相應導電線115，且經由相應通孔111將多個導電線115中的每一者電耦合至相應導電線107。在圖1C中，多個導電線115中的每一者可包含並未說明的額外區段。如下文參看圖2A、圖2B、圖3A、圖 3B以及圖4將更詳細論述，多個導電凸塊121形成三個或大於三個極性組，其有利地減小半導體元件100的ESL。另外，導電凸塊121的形狀及通孔119的面積與相應導電凸塊121的面積之間的比率經設計以減小半導體元件的ESR。
圖1D說明根據另一實施例的沿圖1A中的截面C-C的半導體元件100的平面圖。為簡單起見，圖1D中並未說明半導體元件100的所有構件。另外，為說明各個構件的相對位置，以虛線說明截面C-C中並沒有的一些構件(例如，通孔119、導電線115、通孔111以及導電線107)。
在圖1D的實例中，多個電子組件103沿直線對準。導電線107可將來自兩個鄰接電子組件103的接觸墊102G(或接觸墊102P)電耦合在一起。如圖1D中所說明，經由相應通孔119將多個導電凸塊121(例如，121P、121G)中的每一者電耦合至相應導電線115，且經由相應通孔111將多個導電線115中的每一者電耦合至相應導電線107。在圖1D中，多個導電線115中的每一者可包含並未說明的額外區段。如下文中將更詳細論述，多個導電凸塊121形成三個或大於三個極性組，其有利地減小半導體元件100的ESL。另外，導電凸塊121的形狀及通孔119的面積與相應導電凸塊121的面積之間的比率經設計以減小半導體元件的ESR。
對圖1C及圖1D的實例的改變為可能的且充分意欲包含於本揭露內容的範疇內。舉例而言，在圖1D中，說明第一列電子組件103。可存在與第一列電子組件103並聯安置的第二列電子組件103。電耦合至第二列中的相應電子組件103的導電線115可對相應通孔119的位置及相應導電凸塊121的位置進行重佈線，使 得可以如圖2A中所說明的類似模式來安置所有通孔119及導電凸塊121。
下文參考圖2A、圖2B以及圖4的論述集中於半導體元件(例如，圖2A及圖2B中的半導體元件100A、圖4中的半導體元件100B)的內連線結構110的導電凸塊121及某些構件(例如，通孔119、通孔111)的設計。因此，圖2A、圖2B以及圖4中省略電子組件103以避免混雜。
圖2A說明在一實施例中的半導體元件100A的平面圖。圖2A中的半導體元件100A的平面圖類似於圖1D中的半導體元件100的平面圖，但具有不同數目個電子組件103及導電凸塊121。應注意，為了清晰起見，圖2A中未說明半導體元件100A的所有構件。另外，為說明各個構件的相對位置，圖2A中亦說明的截面中不可見的一些構件(例如，通孔119、導電線115、通孔111以及電子組件103)。圖2B是展示圖2A的導電凸塊121及耦合至導電凸塊121的某些導電特徵(例如，通孔119、通孔111)的放大圖。
現參看圖2A，圖2A說明內連線結構110(參看圖1A)的導電凸塊121(例如，導電凸塊121G、導電凸塊121P)及電耦合至導電凸塊121的一些導電特徵，諸如通孔119、導電線115以及通孔111。應注意，在圖1A的示意性實例中，內連線結構110具有兩個通孔層(例如，通孔111、通孔119)、兩個導電線層(例如，導電線107、導電線115)以及導電凸塊121的層，其中通孔119是內連線結構110的最頂通孔層，導電線115是內連線結構110的最頂導電線層，且通孔111是內連線結構110的第二最頂通 孔層。在一些實施例中，對於其中內連線結構110具有比圖1A中所說明的更多的通孔層及導電線層的實施例，通孔119應解釋為內連線結構的最頂通孔層，導電線115應解釋為內連線結構的最頂導電線層，且通孔111應解釋為內連線結構的第二最頂通孔層。
在圖2A中，將多個導電凸塊121中的每一者安置於相應導電線115上方。可將導電凸塊121安置於相應導電線115的邊界(例如，側壁)內。如圖2A中所說明，多個導電凸塊121中的每一者具有細長形狀。在圖2A中，導電凸塊121被繪示為具有跑道橢圓形狀。此僅為非限制性實例。其他適合的形狀，諸如矩形、橢圓形或類似者亦為可能的且完全意欲包含於本揭露內容的範疇內。在一些實施例中，多個導電凸塊121中的每一者具有長度L2(參看圖2B)及寬度W2(參看圖2B)，且長度L2與寬度W2之間的比率大於約3，諸如在約3與約100之間。如下文中更詳細論述，導電凸塊121的細長形狀連同長度L2與寬度W2之間的較大比率增大了導電凸塊121的面積且幫助減小半導體元件100的ESR。
圖2A亦說明內連線結構110的通孔119。將多個通孔119中的每一者電耦合至相應導電凸塊121。在一些實施例中，在圖2A(或圖2B)的平面圖中，多個通孔119中的每一者所具有的面積在導電凸塊121的面積的約20%至約95%之間(諸如在約50%與約90%之間)。在一些實施例中，通孔119具有長度L1(參看圖2B)及寬度W1(參看圖2B)，其中L1在L2的約50%與約90%之間，且W1在W2的約50%與約90%之間。舉例而言，在一實施例設計中，長度L2為約340微米，寬度W2為約40微米，長度L1為約330微米，且寬度W1為約30微米。導電凸塊121的細長形 狀增大導電凸塊121的面積，且由於通孔119所具有的面積例如為導電凸塊121的面積的50%至90%，因此相較於習知設計，亦增大通孔119的面積。通孔119的較大面積(例如，截面面積)有利地減小所形成半導體元件(例如，半導體元件100、半導體元件100A、半導體元件100B)的ESR，進而改良半導體元件的效率(例如，減小電力消耗)。
雖然通孔119的較大面積(例如，大於導電凸塊121的面積的約50%)有助於減小ESR，但通孔119的面積可能並沒有(例如，100%的)符合導電凸塊121的面積。例如由於用於形成導電凸塊121的開口的微影製程中的誤差容限(error margin)，因此製造方法可限制通孔119的面積與導電凸塊121的面積的接近程度。若通孔119的面積接近導電凸塊121的面積的100%(例如，大於95%)，允許微影製程的足夠誤差容限則可能不存在。換言之，微影製程中的誤差(例如，未對準)可能導致形成具有較差電連接的缺陷導電凸塊121。因此，用於通孔119的面積的以上列舉範圍(例如，導電凸塊121的面積的50%至90%)實現良好ESR減小，同時防止或減少形成缺陷導電凸塊121。
在圖2A及圖2B的所說明的實施例中，通孔119的形狀在幾何上類似於導電凸塊121的形狀。換言之，通孔119的形狀可為導電凸塊121的形狀的按比例調整(例如，收縮)版本。然而，此僅為實例且並不限制。舉例而言，通孔119可具有與導電凸塊121的形狀不同的形狀，但仍具有例如在導電凸塊121的面積的約50%與約90%之間的面積。
圖2A及圖2B進一步繪示經由導電線115(例如，導電 線115G、導電線115P，亦參看圖1A)耦合至相應通孔119的通孔111。在所說明的實施例中，通孔111的面積小於通孔119的面積。舉例而言，通孔111的面積可在相應通孔119的面積的約10%與約90%之間。如圖2B中所說明，通孔111具有分別小於通孔119的長度L1及寬度W1的長度L3及寬度W3。在一些實施例中，長度L3在0.1微米與約10微米之間，且寬度W3在約0.1微米與約10微米之間。
在一些實施例中，藉由增大最頂通孔(例如，通孔119)層的面積(例如，截面面積)來減小半導體元件100的ESR，但較低通孔(例如，通孔111)層的面積(例如，截面面積)並未顯著地影響ESR。因此，通孔111(及其他更低通孔層，若存在)的面積可形成為小於通孔119的面積，其意謂相較於通孔119，可藉由更短的處理時間及更少材料(例如，銅)來形成通孔111。因此，藉由形成大於通孔111的通孔119(例如，更大截面面積)而在半導體元件的生產中實現更低ESR與更低處理時間/材料成本之間的良好平衡。
在圖2A及圖2B的實例中，通孔111具有與通孔119不同的形狀。舉例而言，通孔111具有環形形狀，而通孔119具有跑道橢圓形狀。在其他實施例中，通孔111及通孔119具有類似形狀(例如，幾何上類似形狀)。另外，雖然通孔111被繪示為具有環形形狀，但通孔111可具有其他適合的形狀，諸如正方形、矩形、八邊形或類似形狀。
參看圖2A，將導電凸塊121分組成多個極性組PolG(例如，極性組PolG_P、極性組PolG_G)，其中每一極性組包含配置 為耦合至電力供應器的同一極性的一或多個導電凸塊121。舉例而言，極性組PolG_P包含配置為耦合至電壓供應(例如，+5V、+3V)的一或多個導電凸塊121P，且極性組PolG_G包含配置為耦合至參考電壓(例如，電接地)的一或多個導電凸塊121G。在一些實施例中，將同一極性組(例如，極性組PolG_P或極性組PolG_G)中的一或多個導電凸塊121沿半導體元件100A的上部表面安置於矩形區中。在圖2A中，兩個矩形區域被繪示為圍繞導電凸塊121的虛線矩形，並藉由標記PolG_P及標記PolG_G指出。為避免混雜，並未標記其他五個矩形區，每一區圍繞相應導電凸塊121。
在所說明的實施例中，極性組中的所有導電凸塊121配置為耦合至電力供應器的同一極性。換言之，極性組不應包含配置為耦合至電力供應器的不同極性的導電凸塊。在一些實施例中，彼此緊鄰的極性組配置為耦合至電力供應器的不同極性，且兩個緊鄰極性組之間沒有單獨導電凸塊(例如，並不屬於極性組的導電凸塊)。導電凸塊121可僅屬於單一極性組，或以另一方式陳述，沒有導電凸塊121屬於兩個不同極性組。因此，在一些實施例中，不同極性組之間沒有共用(例如，通用)導電凸塊。在一些實施例中，極性組並不彼此相交。在一些實施例中，兩個緊鄰極性組的矩形區(例如，參看圖2A中的PolG_P及PolG_G)並未交疊。
在圖2A的實例中，存在導電凸塊121的七個極性組(為避免混雜，僅標記兩個極性組)，其中每一極性組包含一個導電凸塊121。特定言之，存在三個極性組PolG_P，每一個由圍繞相應導電凸塊121P的矩形區來定界，且存在四個極性組PolG_G，每 一個由圍繞相應導電凸塊121G的矩形區來定界。如圖2A中所說明的極性組的數目及每一極性組中的導電凸塊的數目僅為實例且非限制性的。極性組中可存在超過一個導電凸塊(參看圖4)，且導電凸塊121的極性組的數目可為三個、四個或更多個。如下文中詳細論述，藉由具有導電凸塊121的三個或大於三個極性組，有利地減小半導體元件100的ESL。
仍參看圖2A，導電凸塊121G彼此對準，且導電凸塊121P彼此對準。然而，導電凸塊121G的一端與導電凸塊121P的一端之間存在偏移D1。換言之，導電凸塊121G藉由偏移D1而與導電凸塊121P錯開。在一些實施例中，偏移D1在導電凸塊121的長度L2(參看圖2B)的約5%與約50%之間，諸如約10%與約20%之間。導電凸塊121G與導電凸塊121P之間的偏移D1有助於在將半導體元件附接至另一元件或封裝體(參見例如圖5)時減小半導體元件(例如，半導體元件100、半導體元件100A或半導體元件100B)的傾斜(例如，非水平的)。暫時參看圖5，當執行回焊製程以使得用於將半導體元件400/半導體元件100/半導體元件100A/半導體元件100B的導電凸塊121附接至底部封裝體200的導電特徵149(例如，襯墊)的焊料區123(參看圖1A中的標記)熔融時，若導電凸塊121P與導電凸塊121G全部對準，則所有導電凸塊121上的熔融焊料可不均勻地流動至一側(例如，所有熔融焊料可流動至導電凸塊121的左端或右端，參看圖2A)。因此，由於導電凸塊121的不同端上的不同焊料量，因此半導體元件(例如，400/100/100A/100B)可能相對於底部封裝體200傾斜(例如，不平行於所述底部封裝體)，因此導致兩個元件之間的不可靠電連 接。在本揭露內容中，藉由具有導電凸塊121G與導電凸塊121P之間的偏移D1，導電凸塊121的錯開分佈減小或阻止熔融焊料流動至導電凸塊121的同一端的可能性，進而減小或防止半導體元件的傾斜。在一些實施例中，若偏移D1小於長度L2的約5%，則半導體元件的傾斜可仍然發生；若偏移D1大於長度L2的約50%，則可不利地影響(例如，減小)ESL的減小量。較大偏移D1(例如，>50%)亦可能限制所形成IPD元件的大小。用於在接合製程期間減小或防止半導體元件傾斜的多種結構及方法揭露於美國專利申請第16/215,373號中，所述申請以全文引用的方式併入本文中。
圖3A說明根據一些實施例的具有七個極性組的半導體元件(例如，半導體元件100A及半導體元件100B)的多個電流路徑141。應注意，為簡單起見，圖3A中僅說明導電凸塊121P及導電凸塊121G。圖1A中說明電流路徑141(例如，電流路徑141A、電流路徑141B)的更多細節。如圖3A中所說明，導電凸塊121P與相應鄰近導電凸塊121G之間存在總計六個並聯電流路徑141。在一些實施例中，每一對導電凸塊121P與導電凸塊121G之間存在寄生電感，且因此藉由具有七個極性組及六個並聯電流路徑141，半導體元件100具有與六個並聯連接寄生電感器的等效電感相等的寄生電感(例如，ESL)。
圖3B說明並聯連接的六個電感器133的示意圖。本領域的技術人員將瞭解多個並聯連接電感器的等效電感小於多個並聯連接電感器中的每一者的電感。舉例而言，假定多個電感器133中的每一者具有標示為L的同一電感，則六個並聯連接電感器133 的等效電感是L/6。因此，藉由具有導電凸塊121的三個或大於三個極性組(因此具有兩個或大於兩個並聯電流路徑141)，相較於導電凸塊的習知兩端設計(例如，僅包含兩個極性組)，半導體元件100的ESL減小(例如，減小超過一半)。
圖4說明根據一實施例的類似於圖2A的半導體元件100A的另一半導體元件100B的平面圖。圖4中存在導電凸塊121的七個極性組，且為避免混雜僅標記兩個。圖4中的極性組類似於圖2A中的極性組，但每一極性組中具有更多個導電凸塊121。特定言之，在圖4中，導電凸塊121的每一極性組(例如，極性組PolG_G或極性組PolG_P)包含兩個導電凸塊121(例如，兩個導電凸塊121G或兩個導電凸塊121P)。在圖4中，將每一導電凸塊121電耦合至相應通孔119、相應導電線115以及相應通孔111。關於導電凸塊121相對於通孔119的形狀及大小及通孔119相對於通孔111的形狀及大小的上文論述適用於圖4的實施例。舉例而言，圖4中的多個導電凸塊121中的每一者的長度與寬度之間的比率大於約3，諸如在約3與約100之間。在一些實施例中，每一通孔119的面積在與通孔119耦合的相應導電凸塊121的面積的約20%至約95%之間，諸如在約50%與約90%之間。在一些實施例中，通孔111的面積小於通孔119的面積，且通孔111可具有與通孔119不同的形狀。如圖4中所說明，導電凸塊121G的一端與導電凸塊121G的一端之間存在偏移D2，其中D2可在導電凸塊121的長度的約10%與約20%之間。在一實施例中，圖4中的導電凸塊121的長度及寬度分別為約140微米及約40微米，且圖4中的通孔119的長度及寬度分別為約130微米及約30微米。
本文中所揭露之實施例實現優於不具有所揭露構件的設計的顯著效能改良。執行模擬以研究圖2A的半導體元件100A及圖4的半導體元件100B的ESL及ESR。對於比較，亦模擬具有電力墊(例如，配置為連接至諸如+5V的供應電壓)及接地墊(例如，配置為連接至諸如電接地的參考電壓)的參考兩端元件。模擬結果展示了相較於參考兩端元件，半導體元件100A及半導體元件100B兩者在100兆赫(MHz)頻率下實現ESL減小約98%，且在100兆赫頻率下實現ESR減小約94%。
另外，亦模擬第二參考元件的ESL及ESR以用於比較。第二參考元件的導電凸塊具有七個極性組，其中每一極性組包含多個環形微凸塊(例如，具有1：1縱橫比)，且經由具有比微凸塊更小的面積(例如，截面)的通孔將每一微凸塊耦合至下方導電線(例如，內連線結構中)。模擬結果展示相較於第二參考元件，半導體元件100A及半導體元件100B在100兆赫頻率下分別實現ESL減小約20%及約10%，且在100兆赫頻率下分別實現ESR減小約33%及約23%。
圖5說明根據一些實施例的半導體封裝體500的截面圖。半導體封裝體500包含底部封裝體200、頂部封裝體300以及附接至底部封裝體200的半導體元件400(例如，IPD)。半導體元件400可為上文揭露的半導體元件100、半導體元件100A或半導體元件100B。
在圖5中，將可為上文所揭露的半導體元件(例如半導體元件100、半導體元件100A或半導體元件100B)中的任一者的半導體元件400附加至底部封裝體200。底部封裝體200具有前側 重佈線結構240與背側重佈線結構210之間的晶粒220。前側重佈線結構240及背側重佈線結構210中的每一者包含形成於一或多個介電層中的導電特徵(例如，導電線及通孔)。模塑材料230形成於前側重佈線結構240與背側重佈線結構210之間。諸如銅柱的導電柱219形成於模塑材料230中。導電柱219將前側重佈線結構240與背側重佈線結構210電耦合。
仍參看圖5，經由導電接合部268將頂部封裝體300接合至底部封裝體200。如圖5中所說明，頂部封裝體300具有基底261及附接至基底261的上部表面的一或多個半導體晶粒262(例如記憶體晶粒)。在一些實施例中，基底261包含矽、砷化鎵、絕緣體上矽(silicon on insulator；「SOI」)或其他類似材料。在一些實施例中，基底261為多層電路板。在一些實施例中，基底261包含雙順丁烯二醯亞胺三嗪(bismaleimide triazine；BT)樹脂、FR-4(由編織玻璃纖維布與耐火的環氧樹脂黏合劑構成的複合材料)、陶瓷、玻璃、塑料、載帶、膜或其他支撐材料。基底261可包含形成於基底261中/上的導電特徵(例如導電線及通孔)。如圖5中所說明，基底261具有形成於基底261的上部表面及下部表面上的導電墊263，所述導電墊263電耦合至基底261的導電特徵。藉由(例如)接線267將一或多個半導體晶粒262電耦合至導電墊263。可包括環氧樹脂、有機聚合物、聚合物或類似者的模塑材料265形成於基底261上方及半導體晶粒262周圍。在一些實施例中，如圖5中所說明，模塑材料265與基底261相接。
在一些實施例中，執行回焊製程以將頂部封裝體300電耦合及機械耦合至背側重佈線結構210。導電接合部268形成於背 側重佈線結構210的導電墊263與導電特徵214之間。在一些實施例中，導電接合部268包括焊料區、導電柱(例如至少在銅導柱之末端表面具有焊料區域之銅導柱)或任何其他合適之導電結合部。類似地，可執行回焊製程以將半導體元件400的導電凸塊121接合至底部封裝體200的導電特徵149(例如，導電墊)。在一些實施例中，導電特徵149的形狀、大小以及位置符合(例如，等於)相應導電凸塊121的形狀、大小以及位置。焊料區173可形成於導電特徵149與導電凸塊121之間。在一些實施例中，將導電凸塊121P接合至導電特徵149P，所述導電特徵149P(例如)經由底部封裝體200的外部連接件255來電耦合至電力供應器的供應電壓(例如，+5V、+3V)。類似地，將導電凸塊121G接合至導電特徵149G，所述導電特徵149G經由(例如)外部連接件255來電耦合至電力供應器的參考電壓(例如，電接地)。
對所揭露實施例的改變為可能的且充分意欲包含於本揭露內容的範疇內。舉例而言，可將極性組的數目及極性組內的導電凸塊的數目改變為其他適合的數目。導電凸塊121的形狀或大小及通孔119的形狀或大小可經修改以具有其他適合的形狀/值，而不背離本揭露內容的精神。作為另一實例，整合於半導體元件中的被動元件(例如，電容器)可具有可互換(例如，可切換極性)的兩個端子，且因此上文關於配置為耦合至特定極性的導電特徵(例如，導電凸塊121P或導電凸塊121G)的說明及論述可切換(例如，導電凸塊121P/導電凸塊115P切換為導電凸塊121G/導電凸塊115G，導電凸塊121G/導電凸塊115G切換為導電凸塊121P/導電凸塊115G)以形成本揭露內容的其他實施例。
圖6說明根據一些實施例的用於形成半導體元件的方法1000的流程圖。應理解，圖6中所示的實施例方法僅為多個可能實施例方法的實例。本領域中具有通常知識者將認識到許多改變、替代物以及修改。舉例而言，可添加、移除、置換、重排以及重複如圖6中所說明的各種步驟。
參看圖6，在區塊1010中，在基底中形成多個被動電子組件。在區塊1020中，在基底上方形成多個第一通孔，第一通孔具有細長形狀且電耦合至被動電子組件。在區塊1030中，在多個第一通孔上方形成多個導電凸塊，導電凸塊電耦合至第一通孔中的相應通孔，導電凸塊具有細長形狀，其中形成多個導電凸塊包括：在第一區中形成配置為耦合至電力供應器的第一極性的多個第一導電凸塊；在鄰接於第一區的第二區中形成配置為耦合至電力供應器的第二極性的多個第二導電凸塊；以及在鄰接於第二區的第三區中形成配置為耦合至電力供應器的第一極性的多個第三導電凸塊，其中第二區在第一區與第三區之間。
實施例可實現優點。藉由在導電凸塊121中具有三個或大於三個極性組，減小所形成半導體元件的ESL。藉由形成具有較大截面面積(例如，導電凸塊121的面積的50%至90%)的通孔119，亦減小所形成半導體元件的ESR。所揭露實施例藉由允許更高操作頻率及藉由降低電力消耗來改良所形成半導體元件的效能。為形成大於通孔111的通孔119，在降低ESR與減少製程時間/成本之間實現良好平衡。
在一實施例中，半導體元件包含基底中的多個被動電子組件；以及多個被動電子組件上方的內連線結構，內連線結構的 多個導電特徵電耦合至多個被動電子組件。內連線結構的多個導電特徵包含：第一導電線，位於基底上方；導電凸塊，位於第一導電線上方，其中在平面圖中，所述導電凸塊具有第一細長形狀且完全安置於第一導電線的邊界內；以及第一通孔，位於第一導電線與導電凸塊之間，所述第一通孔電性連接至第一導電線及導電凸塊，其中在平面圖中，第一通孔具有第二細長形狀且完全安置於導電凸塊的邊界內。在一實施例中，內連線結構包含多個導電凸塊，其中內連線結構包含多個導電路徑，其中多個導電路徑中的每一者將多個導電凸塊中的一者耦合至多個被動電子組件中的一者的至少一個接觸墊，其中內連線結構不含在多個導電路徑之間提供電連接的導電特徵。在一實施例中，多個被動電子組件屬於同一類型，其中多個被動電子組件是電容器、電阻器或電感器。在一實施例中，在平面圖中，第一通孔所具有的面積在導電凸塊的面積的約50%與約90%之間。在一實施例中，內連線結構包含第一導電線與基底之間的第二通孔，第二通孔電耦合至第一通孔，其中在平面圖中，第二通孔的面積小於第一通孔的面積。在一實施例中，第二細長形狀在幾何上類似於第一細長形狀。
在一實施例中，半導體元件包含：基底；多個電子組件，位於基底中；以及多個金屬化物層，位於多個電子組件上方且電耦合至多個電子組件，其中多個金屬化物層包含多個第一通孔及多個第一通孔上方的多個導電凸塊，多個導電凸塊電耦合至多個第一通孔，其中多個第一通孔在多個金屬化物層的最頂通孔層中，其中多個導電凸塊包含：第一組凸塊，配置為耦合至電力供應器的第一極性；第二組凸塊，配置為耦合至電力供應器的第二 極性；以及第三組凸塊，配置為耦合至電力供應器的第一極性，其中第二組凸塊在第一組凸塊與第三組凸塊之間。在一實施例中，第一組凸塊安置於第一區中，第二組凸塊安置於第二區中，且第三組凸塊安置於第三區中，其中第一區與第二區之間沒有導電凸塊，其中第二區與第三區之間沒有導電凸塊。在一實施例中，多個電子組件是電容器、電阻器或電感器。在一實施例中，在平面圖中，多個導電凸塊中的每一者具有細長形狀。在一實施例中，細長形狀具有長度及寬度，長度與寬度之間的比率大於約3。在一實施例中，將多個導電凸塊中的第一導電凸塊電性連接至多個第一通孔中的第一通孔，其中在平面圖中，第一通孔的面積在第一導電凸塊的面積的約50%與約90%之間。在一實施例中，在平面圖中，第一通孔具有與第一導電凸塊類似的幾何形狀。在一實施例中，多個金屬化物層包含多個導電路徑，其中多個導電路徑中的每一者包含多個金屬化物層的多個導電線及多個通孔，所述多個導電線及所述多個通孔耦合於多個導電凸塊的一者與多個電子組件的一者的接觸墊之間，其中在所述多個金屬化層中不存在導電特徵來連接耦合至不同導電凸塊的多個導電路徑。在一實施例中，多個金屬化物層包含在多個第一通孔與基底之間的多個第二通孔的層，其中多個第二通孔電耦合至相應的多個第一通孔，其中在平面圖中，多個第一通孔中的每一者所具有的面積大於多個第二通孔中的相應一者的面積。在一實施例中，多個第一通孔中的每一者的形狀不同於多個第二通孔中的相應一者的形狀。
在一實施例中，半導體元件的形成方法包含：在基底中形成多個被動電子組件；在基底上方形成多個第一通孔，所述多 個第一通孔具有細長形狀且電耦合至多個被動電子組件；以及在多個第一通孔上方形成多個導電凸塊，所述多個導電凸塊電耦合至多個第一通孔中的相應通孔，多個導電凸塊具有細長形狀，其中形成多個導電凸塊包含：在第一區中形成多個第一導電凸塊，所述多個第一導電凸塊配置為耦合至電力供應器的第一極性；在鄰接於第一區的第二區中形成多個第二導電凸塊，所述多個第二導電凸塊配置為耦合至電力供應器的第二極性；以及在鄰接於第二區的第三區中形成多個第三導電凸塊，所述多個第三導電凸塊配置為耦合至電力供應器的第一極性，其中第二區在第一區與第三區之間。在一實施例中，在俯視圖中，多個第一通孔中的每一者具有第一面積，所述第一面積在相應導電凸塊的第二面積的約50%與約90%之間。在一實施例中，所述方法更包含在多個第一通孔與基底之間形成多個第二通孔，其中多個第二通孔中的每一者電耦合至相應第一通孔，其中在俯視圖中，多個第二通孔中的每一者所具有的第三面積小於相應第一通孔的第一面積。在一實施例中，多個第一通孔的形狀不同於多個第二通孔的形狀。
前文概述若干實施例的特徵以使得本領域的技術人員可更佳地理解本揭露內容的態樣。本領域的技術人員應理解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。本領域的技術人員亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且本領域的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100:半導體元件
101:基底
102G、102P:接觸墊
103:電子組件
105、109、113、117:介電層
107、115:導電線
110:內連線結構
111、119:通孔
121P、121G:導電凸塊
123:焊料區
141A、141B:電流路徑
143A、143B、143C:導電路徑
A-A、C-C:截面

Claims (10)

  1. 一種半導體元件，包括：多個被動電子組件，位於基底中；以及內連線結構，位於所述多個被動電子組件上方，所述內連線結構的多個導電特徵電耦合至所述多個被動電子組件，所述內連線結構的所述多個導電特徵包括：第一導電線，位於所述基底上方；導電凸塊，位於所述第一導電線上方，其中在平面圖中，所述導電凸塊具有第一細長形狀且完全安置於所述第一導電線的邊界內；以及第一通孔，位於所述第一導電線與所述導電凸塊之間，所述第一通孔電性連接至所述第一導電線及所述導電凸塊，其中在所述平面圖中，所述第一通孔具有第二細長形狀且完全安置於所述導電凸塊的邊界內。
  2. 如申請專利範圍第1項所述的半導體元件，其中所述內連線結構包括多個導電凸塊，其中所述內連線結構包括多個導電路徑，其中所述多個導電路徑中的每一者將所述多個導電凸塊中的一者耦合至所述多個被動電子組件中的一者的至少一個接觸墊，其中所述內連線結構不含在所述多個導電路徑之間提供電連接的導電特徵。
  3. 一種半導體元件，包括：基底；多個電子組件，位於所述基底中；以及多個金屬化物層，位於所述多個電子組件上方且電耦合至所 述多個電子組件，其中所述多個金屬化物層包括多個第一通孔及在所述多個第一通孔上方的多個導電凸塊，所述多個導電凸塊電耦合至所述多個第一通孔，其中所述多個第一通孔在所述多個金屬化物層的最頂通孔層中，其中所述多個導電凸塊包括：第一組凸塊，配置為耦合至電力供應器的第一極性；第二組凸塊，配置為耦合至所述電力供應器的第二極性；以及第三組凸塊，配置為耦合至所述電力供應器的所述第一極性，其中所述第二組凸塊在所述第一組凸塊與所述第三組凸塊之間。
  4. 如申請專利範圍第3項所述的半導體元件，其中所述第一組凸塊安置於第一區中，所述第二組凸塊安置於第二區中，且所述第三組凸塊安置於第三區中，其中所述第一區與所述第二區之間沒有導電凸塊，其中所述第二區與所述第三區之間沒有導電凸塊。
  5. 如申請專利範圍第3項所述的半導體元件，其中在平面圖中，所述多個導電凸塊中的每一者具有細長形狀。
  6. 如申請專利範圍第3項所述的半導體元件，其中所述多個金屬化物層包括多個導電路徑，其中所述多個導電路徑中的每一者包括所述多個金屬化物層的多個導電線及多個通孔，所述多個導電線及所述多個通孔耦合於所述多個導電凸塊的一者與所述多個電子組件的一者的接觸墊之間，其中在所述多個金屬化層中不存在導電特徵來連接耦合至不同導電凸塊的所述多個導電路徑。
  7. 如申請專利範圍第3項所述的半導體元件，其中所述多個金屬化物層包括在所述多個第一通孔與所述基底之間的多個第二通孔的層，其中所述多個第二通孔電耦合至相應的多個第一通孔，其中在平面圖中，所述多個第一通孔中的每一者所具有的面積大於所述多個第二通孔中的相應一者的面積。
  8. 如申請專利範圍第7項所述的半導體元件，其中所述多個第一通孔中的每一者所具有的形狀不同於所述多個第二通孔中的所述相應一者的形狀。
  9. 一種半導體元件的形成方法，包括：在基底中形成多個被動電子組件；在所述基底上方形成多個第一通孔，所述多個第一通孔具有細長形狀且電耦合至所述多個被動電子組件；以及在所述多個第一通孔上方形成多個導電凸塊，所述多個導電凸塊電耦合至所述多個第一通孔中的相應通孔，所述多個導電凸塊具有所述細長形狀，其中形成所述多個導電凸塊包括：在第一區中形成多個第一導電凸塊，所述多個第一導電凸塊配置為耦合至電力供應器的第一極性；在鄰接於所述第一區的第二區中形成多個第二導電凸塊，所述多個第二導電凸塊配置為耦合至所述電力供應器的第二極性；以及在鄰接於所述第二區的第三區中形成多個第三導電凸塊，所述多個第三導電凸塊配置為耦合至所述電力供應器的所述第一極性，其中所述第二區在所述第一區與所述第三區之間。
  10. 如申請專利範圍第9項所述的方法，進一步包括在所述多個第一通孔與所述基底之間形成多個第二通孔，其中所述多個第二通孔中的每一者電耦合至相應第一通孔，其中在所述俯視圖中，所述多個第二通孔中的每一者所具有的第三面積小於所述相應第一通孔的所述第一面積。
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