TWI467720B - 裝置及低應力晶片封裝陣列製造方法 - Google Patents

裝置及低應力晶片封裝陣列製造方法 Download PDF

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Publication number
TWI467720B
TWI467720B TW100108675A TW100108675A TWI467720B TW I467720 B TWI467720 B TW I467720B TW 100108675 A TW100108675 A TW 100108675A TW 100108675 A TW100108675 A TW 100108675A TW I467720 B TWI467720 B TW I467720B
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Taiwan
Prior art keywords
wafer
conductive
traces
substrate
trace
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TW100108675A
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TW201218344A (en
Inventor
Chen Hua Yu
Hao Yi Tsai
Jiun Yi Wu
Tin Hao Kuo
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201218344A publication Critical patent/TW201218344A/zh
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Description

裝置及低應力晶片封裝陣列製造方法
本發明係有關於一種積體電路，特別是有關於一種半導體晶片內的內連(interconnection)結構。
積體電路通常形成於一基底上，例如一半導體晶圓。接合凸塊(bonding bump)/走線上方凸塊(bump-on-trace)為積體電路中局部的內連結構。凸塊經由電性連接裝置而提供積體電路一介面。可利用傳統技術來將封裝引線(package terminal)連接至積體電路，例如熱壓(thermocompression)或熱聲波(thermosonic)打線及其他習知技術。
晶片內連技術，例如覆晶(flip chip)，也稱為C4接合(Controlled Collapse Chip Connection)，將半導體裝置內連接至具有焊料凸塊(設於晶片輸出接觸位置)的外部電路。焊料凸塊在進行最後的晶圓製程步驟期間，設於晶圓頂側的晶片接墊上。為了將晶片組裝於外部電路(例如，一電路板或另一晶片或晶圓)上，將晶片反置，使其頂側面向下，且其接觸墊覆蓋外部電路上相稱的接墊，接著焊料溢於覆晶與用於支撐外部電路的基底之間，以完成內連接。對照於打線接合，其中晶片為直立組裝且利用接線將晶片接墊內連接至外部電路。結果為覆晶封裝遠小於傳統鑑載(carrier-based)系統，原因在於晶片是直接坐落於電路板上。當內連接線更短，可大幅降低電感及熱阻。因此，覆晶提供了更高速的裝置。
高密度覆晶內連線的近來趨勢是在CPU及GPU封裝中採用圓形或近圓形的銅柱焊料凸塊(copper pillar solder bump)。對於傳統焊料凸塊來說，銅柱焊料凸塊為一種引人注目的替代物，原因在於其可提供固定的晶片和基底之間的間距(間隙)並且與焊料和焊料之間的間距無關。這是十分重要的，因為大部分的高密度電路會充填(under fill)具黏性的類高分子黏著混合物，較小的間距會造成黏著劑難以流動至晶片下方。
然而，傳統上圓形的銅柱焊料凸塊存在數個缺點。其一為圓形的銅柱焊料凸塊的尺寸會加於內連結構，而限制了內連金屬走線的間距大小。因此，現今的圓形銅柱焊料凸塊最終將成為IC工業中裝置持續微縮的瓶頸。
另一缺點在於封裝電路及下方膜層的機械應力。此應力來自於晶片與封裝結構的熱膨脹不匹配。此應例對於具有介電常數低於3的超低介電常數(extra low K,ELK)的電路來說特別重要。封裝變得更加的脆弱，導致膜層分離。
另外，在焊料凸塊對接墊界面處的大電流密度引起電遷移及電應力。由電遷移所造成的損害類型包括焊料接點內的微裂紋(microcracking)以及接合層脫層(delamination)。
如此說來，我們所需的是可提供高密度間距的低應力內連電路。
本說明書揭露本發明許多不同的實施例，而在本發明一實施例中，一種裝置，包括：一晶片，位於一第一基底上；一導電結構，形成於晶片上，導電結構包括一導電柱以及形成於導電柱上方的一焊料凸塊，其中導電結構在平行第一基底的一平面中具有一長條形剖面；一走線，形成於面向晶片的一第二基底上；以及一阻焊層，形成於第二基底上，阻焊層具有一開口位於走線上方；晶片上的導電結構以及阻焊層的開口內的走線形成一走線上方凸塊內連線，且導電結構的長條形剖面的一長軸與走線為同軸的，且走線對準指向於晶片的一中心部。
本發明另一實施例中，一種裝置，包括：一晶片，位於一第一基底上，晶片具有一中心區、一角落區以及一周圍邊緣區；一第一導電結構陣列，具有一長條形剖面形成於晶片的角落區內，每一第一導電結構包括一導電柱以及形成於導電柱上方的一焊料凸塊；一第二導電結構陣列，具有一長條形剖面形成於該晶片的該周圍邊緣區內，每一第二導電結構包括一導電柱以及形成於導電柱上方的一焊料凸塊；以及一金屬走線陣列，位於面向第一基底的一第二基底上；每一第一導電結構以及每一第二導電結構分別與金屬走線形成一同軸走線上方凸塊內連線；晶片的角落區中的第一導電結構陣列的長條形剖面的一長軸指向於晶片的中心區，且晶片的周圍邊緣區中的第二導電結構陣列的長條形剖面的一長軸垂直對準於晶片的邊緣。
本發明又一實施例中，一種低應力晶片封裝陣列製造方法，包括：在一第一基底上提供一晶片；將晶片劃分為一中心區、一角落區以及一周圍邊緣區；在晶片的角落區產生複數個第一導電柱，第一導電柱在平行第一基底的一平面中具有一長條形剖面；在晶片的周圍邊緣區產生複數個第二導電柱，第二導電柱在平行第一基底的平面中具有一長條形剖面；在每一第一導電柱及每一第二導電柱上方形成一焊料凸塊；在一第二基板上形成複數個走線；在第二基板上塗覆一阻焊層；在走線上方的阻焊層內形成複數個開口；將第二基板反置，以面向第一基板；以及透過每一凸塊將第一導電柱及等第二導電柱連接至走線。第一導電柱及第二導電柱的長條形剖面的長軸與對應的走線為同軸的，且晶片的角落區的第一導電柱對準晶片的一對角線，且晶片的周圍邊緣區的第二導電柱垂直對準晶片的邊緣。
要瞭解的是本說明書以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了達到簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。再者，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第一特徵之上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，在空間上的相關用語，例如”上/下”、”頂部/底部”、”垂直/水平”，係使本說明書容易表達而非限定一絕對方向。舉例來說，一上層及一下層可表示關於形成於一基底上的基底或是積體電路各自的關係，而非絕對方向。
請參照第1A及1B圖，其分別繪示出習知走線上方圓形銅柱凸塊結構100(其形成於內連接一基底上的金屬走線的一積體電路上)之平面及剖面示意圖。從上視方向來看，一圓形銅柱凸塊110係形成於一金屬走線120上，且靠近一相鄰走線130。一額外的環形區115表示因設計更動而可能產生的凸塊尺寸變化，其造成銅凸塊與相鄰走線130之間的空間縮小。第1B圖係繪示出沿著垂直走線的平面的對應結構剖面示意圖。一積體電路通常包括圖案化的導電層、絕緣層、及半導體層而形成的電路。該電路可包括一內連結構或是具有開口151的局部積體電路150(例如，多層內連線(multilayer interconnect,MLI)或多個導電走線及具有作為電性接觸的開口的層間介電層)，開口上先設置銅層，接著為焊料界面層。對銅層及焊料界面層進行一圖案化製程(例如，微影及蝕刻)，以定義出內連銅柱結構111。銅柱111的一端電性連接積體電路150的開口151，並透過另一端的界面層112而貼附至一焊料凸塊105。接著翻轉具有電路150的晶片，以面向具有基底101及走線121及131的一內連板(interconnecting board)。具有銅柱111的電路150接著放置於內連基底上方的走線121上方，使焊料凸塊105與走線121接觸而形成一走線上方凸塊連接。在一些方法中，可固化黏著劑填入凸塊之間的空隙而容許在嵌合製程(mating process)期間固化，以在回流製程(reflow process)期間限制熔融的焊料。凸塊111與相鄰走線131之間的間隙116係做為短路防護。因此，適當的間隙提供了充分固化製程。然而，凸塊放置於微間距上，其相同於內連基底的最小走線間距。因此此製程成為封裝製程的挑戰，因為凸塊及接合間距可能過小。再者，安全得間隙空間容易受到凸塊尺寸變化(環形區115)的影響。
第2圖係繪示出根據一實施例之走線上方同軸長條形凸塊結構(例如，一長條形凸塊與金屬走線連接)210之平面示意圖以及對照的習知走線上方圓形銅凸塊250之平面示意圖。在上方的裝置中，走線上方同軸長條形凸塊結構是一長條形結構位於走線212的頂部，且靠近一相鄰走線215，其與走線212以一空間218隔開。下方的裝置繪示出習知圓形銅柱251位於走線252上，且與相鄰走線255之間形成一空間258。相較之下，在相同的凸塊及接合間距時，走線上方同軸長條形凸塊以大於間隙258(由走線上方圓形凸塊所形成)的空間218作為保護。
第3圖係繪示出對應於第2圖中實施例的走線上方同軸長條形凸塊結構310剖面示意圖以及作為對照的相似的習知圓形銅柱結構350剖面示意圖，其相似於第1B圖中的結構100。上述剖面為垂直走線的長度。走線上方同軸長條形銅柱凸塊結構形成於內連接一基底上的金屬走線的一積體電路上。積體電路通常包括圖案化的導電層、絕緣層、及半導體層而形成的電路。該電路可包括一內連結構或是具有開口306的局部積體電路305，開口上先設置銅層，接著為焊料界面層。對銅層及焊料界面層進行一圖案化製程(例如，微影及蝕刻)，以定義出內連長條形銅柱結構。長條形銅柱311的一端電性連接積體電路350的開口306，並透過另一端的界面層312而貼附至一焊球315。焊球315在長條形銅柱的末端表面延伸成長條形形。接著翻轉具有電路305的晶片，以面向具有基底301及走線321及331的一內連板。具有銅柱311、界面層312及焊球315所構成的結構的電路305接著放置於內連基底上方的走線321上方，使長條形焊球315與走線321形成一走線上方長條形凸塊連接。長條形銅柱311以一空間316而與相鄰走線331隔開。
下方剖面圖係繪示出具有圓形銅柱111的習知結構350。圓形銅柱111的一端連接積體電路的一開口151或是局部的積體電路150，且另一端連接銅柱111的焊料界面層112及焊料凸塊105。該習知銅柱堆疊放置於走線121上而與相鄰走線131之間形成一空間356。相較之下，在相同的凸塊及接合間距時，走線上方同軸長條形凸塊具有大於間隙356(由走線上方圓形凸塊所形成)的空間316。
走線上方長條形凸塊結構可包括一銅柱。然而，柱體材料不僅限定為銅。其他適當的柱體材料包括：鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物(例如，矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合)、銅、銅合金、鉭、氮化鉭或其組合。焊料凸塊可含鉛或無鉛。焊料可包括：錫、銅、銀、鉍、銦、鋅、銻、Sn-Ag-Cu、Ag-Cu-Zn、Sn-Ag-Cu-Mn或與構成走線的其他金屬的合金。
適當的走線材料包括：金屬、金屬合金、金屬矽化物、鋁或鋁合金、銅、銅/鎳合金、銅-浸鍍錫(immersion tin,IT)、銅-化學鎳鈀金(electroless nickel electroless palladium immersion gold,ENEPIG)、銅-有機保焊劑(organic solderability preservatives,OSP)及/或其組合。
適當的內連基底材料包括：非導電的支撐層，例如，氧化矽、低介電常數材料(如，介電常數小於2.5(超低介電常數(extra low k,ELK)))、氮化矽、氮氧化矽、聚亞醯胺(polyimide)、旋塗玻璃(spin-on glass,SOG)、氟矽玻璃(fluoride-doped silicate glass,FSG)、未摻雜矽玻璃(undoped silica glass,USG)、碳氧化矽(SiOC)、黑鑽石(加州聖塔克拉拉應用材料公司)、乾凝膠(Xerogel)、空氣膠(Aerogel)、氟化非晶矽碳(amorphous fluorinated carbon)、聚對二甲苯(Parylene)、苯並環丁烯(bis-benzocyclobutene,BCB)、SiLK(密西根密德蘭陶氏化學)及/或其他適當材料。
請參照第4圖，其繪示出根據三個實施例之走線上方長條形凸塊結構平面示意圖。結構410包括形成於走線411的凸塊415，凸塊外型為具有二個凸面彎曲側邊的矩形。矩形的長軸變成共軸，亦即，平行或幾乎平行走線411的軸。結構440包括形成於走線441上的一橢圓型凸塊445。橢圓的長軸也是與走線441共軸。相似地，結構480包括形成於走線480上的一長條形凸塊485。凸塊485的長軸也是與走線481共軸。長條形凸塊的長軸對準走線方向，以將凸塊側邊到最接近的相鄰走線之間的空間最大化。上述實施例的特徵容許更密集的圖案案凸塊及接合間距，因而具有更緊密的金屬空間設計規則。
請參照第5圖，其分別繪示出根據第2圖中一實施例之走線上方長條形凸塊結構陣列平面示意圖以及第1圖中習知走線上方圓形凸塊結構陣列平面示意圖。在上方陣列510中，一列的長條形凸塊511、515、520、525各自形成於交替的走線512、516、522、526上。為了增加封裝密度，在列的方向的走線上方凸塊接點是交錯設置(staggered)的，因而第5圖的一列中凸塊僅出現於相隔走線上。因此凸塊511與走線514之間的空間為標號541。
在第5圖的下方陣列550中，圓形凸塊551，555，560，565各自形成於交替的走線552，556，562，566上，而凸塊551與走線554之間具有凸塊至相鄰走線的空間581。如第5圖所示，在相同的凸塊與接合製程設計規則下，上方陣列510較下方陣列550具有更多的走線能被封裝於相同的區域。因此，根據本實施例的陣列510較習知陣列550具有更緊密的間距以及更大的接合製程容許度。
在上述實施例中，走線上方同軸長條形凸塊結構的陣列(511、515、520、525)可包括銅柱。然而，柱體材料不僅限定為銅。其他適當的柱體材料包括：鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物(例如，矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合)、銅、銅合金、鉭、氮化鉭或其組合。焊料凸塊可含鉛或無鉛。焊料可包括：錫、銅、銀、鉍、銦、鋅、銻、Sn-Ag-Cu、Ag-Cu-Zn、Sn-Ag-Cu-Mn或與構成走線的其他金屬的合金。
適當的走線材料包括：金屬、金屬合金、金屬矽化物、鋁或鋁合金、銅、銅/鎳合金、銅-浸鍍錫(IT)、銅-化學鎳鈀金(ENEPIG)、銅-有機保焊劑(OSP)及/或其組合。
走線上方同軸長條形凸塊結構的另一優點在於較習知圓形或類圓形凸塊具有更大的著落區(landing area)，而無需增加凸塊寬度。較大的著落區提供與走線更大的接觸面積，因而有較低的電流密度通過界面。根據布拉克方程式(Black’s equation)，因電遷移以及電磁場引起固相內分子重排(移動)的現象，半導體電路的平均失效時間(mean time to failure,MTTF)正比於接觸面積。
MTTF=Awj-n e(Q/kT) 　(布拉克方程式)
A為常數；J為電流密度；n為模型參數，近似於2；Q為活化能(電子伏特，eV)k微波茲曼(Boltzmann)常數；T為絕對溫度(K)；W為金屬線的寬度。
布拉克方程式為一種經驗模型，其描述失效速率與溫度的相依性、電流密度誘發電應力以及特定技術及材料。A、n、Q的值可由經驗資料的模型擬合(fitting)而得到。通常銅(Cu)或鋁(Al)內連線中發生電遷移的電流密度為106至107 A/cm2 。然而，電遷移發生於十分低的電流密度。對一般的焊料接點而言，例如今日IC晶片所使用的SnPb或無鉛SnAgCu，電遷移發生於104 A/cm2 的低電流密度。電遷移造成一淨原子沿電子流的方向運送。原子聚積於陽極且在陰極形成孔洞，因此在焊料界面處誘發電應力。由於高電流密度造成電流聚集效應，孔洞延展成微裂縫並造成電路失效。
當近來IC工業從接墊上方凸塊(bump-to-pad)進展到走線上方凸塊，電遷移損害變得更加嚴重，這是因為相較於接墊上方凸塊結構，走線上方凸塊減少走線上一半的接墊面積。為了補足損失的接觸面積，習知走線上方圓形凸塊需為凸塊直徑的兩倍。然而，突出的凸塊從最接近的相鄰走線處佔用安全空間，而降低用於內連電路的製程容許度。
根據一些實施例的走線上方長條形凸塊較相較於習知走線上方圓形凸塊具有全面的大走線接觸界面。走線上方長條形凸塊的長度增加會成正比地擴大與走線的重疊區域。同時凸塊的寬度幾乎沒有改變。因此，走線上方長條形凸塊的一顯著優點在於降低電遷移損害。
第6A及6B圖比較了第2圖中走線上方長條形凸塊結構以及第1圖中習知走線上方圓形凸塊結構平面與剖面示意圖，該剖面為沿走線方向的截面。在第6A圖中，左邊為同軸長條形結構610平面示意圖，而右邊為剖面示意圖。在平面示意圖中，長條形凸塊611位於走線612上。在對應的剖面示意圖中，走線上方長條形銅柱結構凸塊結構形成於內連接一基底上的金屬走線的一積體電路上。該電路可包括一內連結構或是具有開口616的局部積體電路615，開口電性連接至銅柱618的頂端。焊料界面層621及斜面的焊料凸塊622形成於銅柱618的底端。凸塊622兩側的斜面由焊球嵌合走線而成。具有基底624及導電走線623的一內連板放置於翻轉的具有電路615的晶片上，使焊料凸塊622及走線623形成走線上方凸塊連接。通過內連表面的電流以虛線625表示之。在第6B圖中，習知走線上方凸塊結構640的平面示意圖中呈現出一圓形凸塊641位於走線642上方。對應的結構640剖面示意塗包括一圓形銅柱648，其一端連接積體電路645的一開口646或是局部的積體電路645，且另一端連接圓形銅柱648的焊料界面層651及焊料凸塊652。具有基底654及金屬走線653的一內連板放置於翻轉的具有電路645的晶片上，使焊料凸塊652及走線653形成走線上方凸塊連接。通過內連表面的電流以虛線655表示之。如圖所示，使用圓形凸塊的電流密度高於使用長條形凸塊。
走線上方同軸長條形凸塊結構可包括一銅柱。然而，柱體材料不僅限定為銅。其他適當的柱體材料包括：鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物(例如，矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合)、銅、銅合金、鉭、氮化鉭或其組合。焊料凸塊可含鉛或無鉛。焊料可包括：錫、銅、銀、鉍、銦、鋅、銻、Sn-Ag-Cu、Ag-Cu-Zn、Sn-Ag-Cu-Mn或與構成走線的其他金屬的合金。
第7A圖係繪示出根據本發明其他實施例之凸塊外型，上述外型包括具有彎曲側邊的矩形701、卵形702極膠囊形703。第7B圖係繪示出習知圓形凸塊711及八角形凸塊712。
第8圖係繪示出連接走線上方長條形凸塊結構的一些走線。走線具有筆直的側邊801，也可具有彎曲的側邊，其突出成圓形802、方形803、卵形804、菱形805或多邊形806。
第9圖係繪示出根據一些實施例之一長條形凸塊與一走線的相對位置及尺寸。長條形凸塊的短邊相較於走線的寬度可為寬短邊910、相等短邊920或是窄短邊930。
第10圖係繪示出多個長條形凸塊與多個走線的相對位置。長條形凸塊可突出於走線的中心(如，1010)、指與走線單側局部重疊(如，1020)或是位於走線中間內(如，1030)。
請參照第11圖，其繪示出根據一實施例之走線上方凸塊內連線向心佈線圖1100。此佈線包括一球柵陣列(ball grid array,BGA)組裝板1110以及組裝於板1110上的一晶片1120，期內連電路的面朝下。晶片1120上所示的內連線圖微向下表面的佈線圖而不上表面。該圖繪示出位於晶片不同的位置的不同內連線結構特徵。在一中心位置中，內連線的特徵在於為圓形柱體，而在晶片周圍，內連線圖案化成位於走線上的同軸長條形柱體。然而，周圍的內連線具有兩種柱體取向(orientation)。順沿著四個直線邊緣，內連線1130的取向為垂直晶片的邊緣，而靠近晶片四個角落，內連線1140則取向為斜向地朝向晶片中心1150。
第12圖係繪示出根據一實施例之位於晶片1200角落區及周邊區內之長條形內連線概括圖。位於晶片1200角落的長條形內連線1210、1220、1230及1240指向晶片中心1290且與相鄰邊線夾45°角。沿著晶片1200邊緣的長條形內連線1250、1260、1270及1280則垂直各自的邊緣。
包含角落的晶片周圍通常需要最小間距，因其時常包含高於位在中心區域的電源及接地端點的內連線密度。如以上所述，同軸長條形柱體陣列提供了較習知圓形柱體陣列更緊密的間距以及更大的接合製程容許度。因此，走線上方同軸長條形凸塊為晶片封裝外側邊緣的內連線選擇。
在本實施例中，走線上方同軸長條形凸塊結構陣列(1230、1240)可包括一銅柱。然而，柱體材料不僅限定為銅。其他適當的柱體材料包括：鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物(例如，矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合)、銅、銅合金、鉭、氮化鉭或其組合。焊料凸塊可含鉛或無鉛。焊料可包括：錫、銅、銀、鉍、銦、鋅、銻、Sn-Ag-Cu、Ag-Cu-Zn、Sn-Ag-Cu-Mn或與構成走線的其他金屬的合金。
適當的走線材料包括：金屬、金屬合金、金屬矽化物、鋁或鋁合金、銅及銅合金及/或其組合。
第13圖係繪示出根據本發明實施例之向心內連線結構佈線的一角落處。標號1300為晶片1301的四等分之一圖。該圖1300具有三個區域：被阻焊層1311所保護的中心區1310、不具阻焊層的周圍內連線區1320以及被阻焊層覆蓋的晶片邊緣1330。在中心區1310內，在阻焊層內形成與圓形柱體1314嵌合的圓孔1312，以露出走線1313。在晶片的周圍內連線區1320內，周圍內連線區1320的走線1321、1323、1325為明線(open line)而無阻焊劑。圖案化內連電路上方的長條形柱體1322、1324、1326並分別與走線1321、1323、1325同軸嵌合。完成內連線之後，走線1321及長條形柱體1322順沿著一周圍邊緣並垂直該邊緣，位於一角落的走線1323及長條形柱體1324傾斜地指向晶片中心，而靠近角落的走線1325及長條形柱體1326也指向晶片中心以助於走線轉向。
第14A圖係繪示出覆晶封裝的剪應力分佈。應力向量1401、1402、1403、1404沿對角方向於晶片1400的四的角落拉引。由於基底不匹配的熱收縮及膨脹，晶片四個角落的剪應力非常嚴重。向心的同軸長條形內連線至少有二個理由可降低內連線的界面上的剪應力。第一，金屬走線平行剪應力方向而提供較佳的界面層支撐。第二，每一走線上方長條形凸塊的接觸界面具有較大界面面積而降低膜層應力，這是因為平均的界面層剪應力與界面面積成反比，如以下公式所示：
τ=F/A
其中，
τ=剪應力
F=施力
A=截面積
第14B圖係繪示出向心的長條形內連線的剪應力向量。在圖1430中，同軸對準走線1431的長條形柱體1432具有大於習知圓形柱體1436的接觸面積(正比於長度1433)，且具有相同的走線線寬1437，因此在界面層處發生層離(delamination)的風險會大幅降低。
第14C圖係繪示出根據本發明另一實施例之在晶片不同區域中的向心內連線佈線。晶片1450在中心區及周圍區包含具有不同接觸密度的各種內連線圖案。舉例來說，位於中心區1460及1463的電源及接地端點的密度低於位於晶片內的區域1462。高密度會增加封裝應力及晶片上的拉力，如第14A圖所述。如以上所述，走線上方同軸長條形凸塊內連陣列相較於習知圓形柱體陣列，有較緊密的間距及較大的接合製程容許度。因此，走線上方同軸長條形凸塊內連陣列是根據降低表面應力而設計的。舉例來說，位於對角角落1451及1453具有相似的圖案，原因在於這些角落鄰近相似的電源及接地端點。當晶片上附近的圖案不同時，角落1452及1454的長條形內連線形成了不同的佈線，以適應其加載於對應角落的特定應力。在周圍邊緣區中，陣列可劃分成具有不同特徵的次陣列。周圍佈線可包含多列的走線上方長條形凸塊內連陣列。舉例來說，陣列1471及1474包含具有不同尺寸及間距的結構，而陣列1472、1473及1475則改變了陣列寬度、長度、間距及圖案。
第15圖係繪示出在內連基底上進行走線圖案化製程期間，開通阻焊層的一些選擇。在走線上開通阻焊層，積體電路側的柱體頂不上的嵌合焊料可與走線形成電性接觸。然而若有需要，仍可開通沒有焊料之處的走線上方阻焊層。在焊料接合製程之後的底膠填充製程，黏著劑將填入及密封用以圍繞柱體的阻焊層開口所留下得間隙。
圖1510表示走線上方焊料開口的第一部上視圖，周圍區1511的阻焊層大抵上被開通，該處需要最小的凸塊及接合間距。走線表面上的阻焊層也被開通，該處周圍為了製程上的方便而沒有柱體置入。然而，在中心區1513中，電源及接地端點不需要最小的凸塊及接合間距，因此只開通用於銅柱入孔(landing hole)1512的阻焊層。
圖1520表示走線上方焊料開口的第二部上視圖，其中周圍區1521及中心區1522兩處的阻焊層大抵上被開通，無論凸塊及接合間距是否最小，或銅柱是否置入於阻焊區1522內。
圖1530表示第三部，周圍區1531的阻焊層大抵上被開通，該處需的凸塊及接合間距最小。然而，在中心區1533中，電源及接地端點不需要最小的凸塊間距，僅選擇性開通位於一或多個遮罩區1534及1535的阻焊層，無論銅柱是否置入這些區域。
請參照第16圖，其繪示出根據本發明一實施例之製造走線上方長條形凸塊結構的方法166流程圖。方法1600可用於製造上述圖式中的結構，例如結構210、310、410、440、440、480、510、610、910、920、930、1010、1020、1030、1130、1140、1210、1280、1322、1324、1326以及1432。可以理解的是在其他方法實施例中，可在進行方法1600之前、期間或之後進行額外的步驟，而以下所述的某些步驟也可重複進行或省略。
方法1600起始於步驟1610，在一第一基底上形成或局部形成一積體電路。基底可為半導體晶圓，例如矽晶圓。另外，基底可包括其他元素半導體材料，例如絕緣層上覆矽(silicon on insulator,SOI)、鍺、化合物半導體(例如，碳化矽、砷化鎵、砷化銦及磷化銦)、合金半導體材料(例如，鍺化矽、矽鍺碳、磷砷化鎵、磷銦化鎵)及/或其他習知基底組成物。
積體電路可由沉積於基底上的導電層、半導體層及絕緣層所構成。步驟1615為形成位於積體電路表面上用於製作接合層的接觸結構。在步驟1620中，一光阻層沉積於積體電路的表面上。在步驟1625中，進行圖案化以形成所需的長條形介層洞。介層洞內可置入柱體材料，以將積體電路的裝置電性接觸於封裝端點。在步驟1630中，沉積一些鍍層。一鍍層構成了柱形介層洞內的柱體插塞(plug)。其他鍍層可為頂部焊料層以及位於焊料層與柱體層之間的界面層。在步驟1635中，去除光阻而形成所需的長條形柱體。內連結構的導電柱體的材料可包括：鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物(例如，矽化鎳、矽化鈷、矽化鎢、矽化鉭、矽化鈦、矽化鉑、矽化鉺、矽化鈀或其組合)、銅、銅合金、鉭、氮化鉭或其組合及/或其他適當材料。形成內連柱體結構的製程可包括：物理氣相沉積(physical vapor deposition,PVD)或濺鍍(sputtering)、化學氣相沉積(chemical vapor deposition,CVD)、電鍍及/或其他適當製程。其他用於形成內連柱體結構的製造技術可包括：微影及蝕刻製程，以圖案化用於垂直柱體的導電層，後續可接著進行回蝕刻或化學機械研磨(chemical mechanical polishing,CMP)製程。
在下一步驟1640中，對焊料層施加熱回流製程且在柱體頂部形成接觸焊料凸塊。在步驟1645中，翻轉具有積體電路的晶片，使焊料凸塊面向走線。
在並列的順序中，方法1600包括步驟1660，在一分開的第二基底上形成一導電層。接著進行步驟1665，圖案化導電層，以形成導電走線。可採用微影製程(包括：形成光阻層、烘烤製程、曝光製程、顯影製程)、濕式或乾式蝕刻製程及/或其他適當的製程等來形成製造導電層。方法1600進行至步驟1670，沉積阻焊層並進行圖案化，以形成內連開口。阻焊層用於防護定義開口(該處露出走線以嵌合焊料柱體)外側任何不要的內連線短路。
方法1600接著進行至步驟1680，步驟1680中翻轉的晶片對準於第二基底，而具有焊料的柱體頂部將覆蓋導電走線，以形成內連線。可進行一些製程，例如熱風回流(heat air reflow)或熱接合(thermosonic bonding)，以液化焊料頂端而形成內連接。在步驟1690中，透過底膠填充製程在圍繞柱體的間隙內填入黏著劑，例如高分子材料，來提供絕緣、支撐及穩定性而完成接合。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於後續本發明的詳細說明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其它結構或製程的變更或設計基礎，以進行相同於本發明實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本發明之精神和保護範圍內，且可在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
100．．．走線上方圓形銅柱凸塊結構
101、301、624、654．．．基底
105、622、652．．．焊料凸塊
110．．．圓形銅柱凸塊
111．．．銅柱結構/凸塊
112、312．．．界面層
115．．．環形區
116．．．空間/間隙
120、653．．．金屬走線
121、131、212、252、321、331、411、441、481、512、514、516、522、526、552、554、556、562、566、612、642、1313、1321、1323、1325、1431．．．走線
150、615、645．．．積體電路
151、306、616、646．．．開口
210、310．．．走線上方同軸長條形凸塊結構
211．．．長條形結構
215、255．．．相鄰走線
218、258、316、356、541、581．．．空間
250．．．走線上方圓形銅凸塊
251、311、648．．．銅柱
305．．．積體電路/內連電路
315．．．焊球
350．．．銅柱結構
410、440、480．．．結構
415、445、485．．．凸塊
510、550、1471、1472、1473、1474、1475．．．陣列
511、515、520、525、611．．．長條形凸塊
551、555、560、565、641、711．．．圓形凸塊
610．．．銅軸長條形結構
618、648．．．銅柱
621、651．．．焊料界面層
623．．．導電走線
625、655．．．電流
640．．．走線上方凸塊結構
701．．．具有側邊彎曲的矩形
702、804．．．卵形
703．．．膠囊形
712．．．八角形凸塊
801．．．筆直側邊
802．．．圓形
803．．．方形
805．．．菱形
806．．．多邊形
910．．．寬短邊
920．．．相等短邊
930．．．窄短邊
1010．．．突出於走線中心
1020．．．與走線單側局部重疊
1030．．．位於走線中間
1100．．．向心佈線圖
1110．．．球柵陣列組裝板
1120、1200、1301、1400、1450．．．晶片
1130、1140．．．內連線
1150、1290．．．晶片中心
1160、1314、1436．．．圓形柱體
1210、1220、1230、1240、1250、1260、1270、1280．．．長條形內連線
1300．．．晶片四等分之一圖
1310．．．中心區
1311．．．阻焊層
1312．．．圓孔
1320．．．周圍內連線區
1330．．．晶片邊緣
1322、1324、1326、1432．．．長條形柱體
1401、1402、1403、1404．．．應力向量
1430、1510、1520、1530．．．圖
1433．．．長度
1437．．．走線線寬
1460、1463、1513、1533．．．中心區
1451、1452、1453、1454．．．角落
1462．．．區域
1511、1521、1531．．．周圍區
1512．．．銅柱立孔
1522．．．中心區/阻焊區
1534、1535．．．遮罩區
1600．．．方法
1610、1615、1620、1625、1630、1635、1640、1645、1660、1665、1670、1680、1690．．．步驟
第1A至1B圖係分別繪示出習知走線上方圓形銅柱凸塊內連線之平面及剖面示意圖。
第2圖係繪示出根據一實施例之走線上方長條形凸塊結構之平面示意圖以及習知走線上方圓形凸塊結構之平面示意圖。
第3圖係繪示出對應於第2圖中走線上方長條形凸塊結構以及習知走線上方凸塊結構之剖面示意圖，該剖面為垂直走線的平面。
第4圖係繪示出根據不同實施例之走線上方長條形凸塊結構平面示意圖。
第5圖係分別繪示出根據第2圖中一實施例之走線上方長條形凸塊結構陣列平面示意圖以及第1圖中習知走線上方圓形凸塊結構陣列平面示意圖。
第6A至6B圖係分別繪示出根據第3圖中一實施例之走線上方長條形凸塊結構剖面示意圖以及習知走線上方圓形凸塊結構剖面示意圖，該剖面為沿著走線的平面。
第7A圖係繪示出根據本發明其他實施例之走線上方長條形凸塊結構外型。
第7B圖係繪示出走線上方圓形或類圓形凸塊結構。
第8圖係繪示出連接走線上方長條形凸塊結構的一些走線。
第9圖係繪示出一長條形凸塊與一走線的相對位置及尺寸。
第10圖係繪示出多個長條形凸塊與多個走線的相對位置。
第11圖係繪示出根據一實施例之走線上方凸塊內連線向心佈線圖1100。
第12圖係繪示出位於晶片角落區及周邊區內之長條形內連線概括圖。
第13圖係繪示出根據本發明實施例之位於晶片角落處的向心內連線佈線。
第14A圖係繪示出覆晶封裝的典型物理應力方向。
第14B圖係繪示出向心的長條形內連線的應力向量。
第14C圖係繪示出根據本發明另一實施例之在晶片不同區域中的向心內連線佈線。
第15圖係繪示出開通阻焊層的一些選擇。
第16圖係繪示出根據本發明不同實施例之向心佈線結構製造方法流程圖。
101、301．．．基底
105．．．焊料凸塊
111．．．銅柱結構/凸塊
112、312．．．界面層
121、131、321、331．．．走線
150．．．積體電路
151、306．．．開口
305．．．積體電路/內連電路
310．．．走線上方同軸長條形凸塊結構
311．．．銅柱
315．．．焊球
316、356．．．空間
350．．．銅柱結構

Claims (9)

  1. 一種裝置，包括：一晶片，位於一第一基底上；複數個第一導電結構，形成於該晶片的一周圍部分中，其中該晶片的該周圍部分包括一晶片角落及一晶片平直邊緣，其中每一該等第一導電結構包括一導電柱以及形成於該導電柱上方的一焊料凸塊，並且在平行該第一基底的一平面中具有一長條形剖面；複數個走線，形成於面向該晶片的一第二基底上；以及一阻焊層，形成於該第二基底上，該阻焊層具有複數個開口位於該等走線上方；其中該晶片上的該等第一導電結構以及該阻焊層的該等開口內的該等走線形成複數個走線上方凸塊內連線，其中連接至該晶片平直邊緣的該等走線包括具有第一長度的走線以及具有不同於該第一長度之第二長度的走線，且其中在每一該等走線上方凸塊內連線中，該等第一導電結構的該長條形剖面的一長軸與該走線為同軸的，且其中位於該晶片角落的該等走線上方凸塊內連線對準該晶片的一對角線，且位於該晶片平直邊緣的該等走線上方凸塊內連線垂直對準該晶片平直邊緣。
  2. 如申請專利範圍第1項所述之裝置，更包括一第二導電結構，其在平行該第一基底的該平面中具有圓形剖面，其中具有該圓形剖面的該第二導電結構位於該晶片的該中心部。
  3. 一種裝置，包括：一晶片，位於一第一基底上，該晶片具有一中心區、一角落區以及一周圍邊緣區；一第一導電結構陣列，具有一長條形剖面形成於該晶片的該角落區內，每一第一導電結構包括一導電柱以及形成於該導電柱上方的一焊料凸塊；一第二導電結構陣列，具有一長條形剖面形成於該晶片的該周圍邊緣區內，每一第二導電結構包括一導電柱以及形成於該導電柱上方的一焊料凸塊；以及一金屬走線陣列，位於面向該第一基底的一第二基底上，其中每一第一導電結構以及每一第二導電結構分別與該金屬走線形成一同軸走線上方凸塊內連線，其中連接至該周圍邊緣區的該等金屬走線包括具有第一長度的金屬走線以及具有不同於該第一長度之第二長度的金屬走線，其中該晶片的該角落區中的每一該等第一導電結構陣列的該長條形剖面的一長軸指向於該晶片的該中心區，且該晶片的該周圍邊緣區中的每一該等第二導電結構陣列的該長條形剖面的一長軸垂直對準於該晶片的該周圍邊緣。
  4. 如申請專利範圍第3項所述之裝置，更包括一第三導電結構陣列，位於該晶片的該中心區，該等第三導電結構在平行該第三基底的該平面中具有圓形剖面。
  5. 如申請專利範圍第3項所述之裝置，其中該第一導 電結構陣列及該第二導電結構陣列具有既定佈線。
  6. 如申請專利範圍第3項所述之裝置，其中該第一導電結構陣列及該第二導電結構陣列包括複數個次陣列，其中該等次陣列具有彼此不同的既定佈線。
  7. 一種低應力晶片封裝陣列製造方法，包括：在一第一基底上提供一晶片；將該晶片劃分為一中心區、一角落區以及一周圍邊緣區；在該晶片的該角落區產生複數個第一導電柱，該等第一導電柱在平行該第一基底的一平面中具有一長條形剖面；在該晶片的該周圍邊緣區產生複數個第二導電柱，該等第二導電柱在平行該第一基底的該平面中具有一長條形剖面；在每一第一導電柱及每一第二導電柱上方形成一焊料凸塊；在一第二基板上形成複數個走線；在該第二基板上塗覆一阻焊層；在該等走線上方的該阻焊層內形成複數個開口；將該第二基板反置，以面向該第一基板；以及透過每一凸塊將該等第一導電柱及該等第二導電柱連接至該等走線，其中該等第一導電柱及該等第二導電柱的該等長條形剖面的長軸與對應的該等走線為同軸的，其中連接至該周圍邊緣區的該等走線包括具有第一長度的走線以及 具有不同於該第一長度之第二長度的走線，其中該晶片的該角落區的該等第一導電柱對準該晶片的一對角線，且該晶片的該周圍邊緣區的該等第二導電柱垂直對準該晶片的邊緣。
  8. 如申請專利範圍第7項所述之低應力晶片封裝陣列製造方法，其中在該晶片的該角落區及該周圍邊緣區中的大部分的該阻焊層為開通的。
  9. 如申請專利範圍第7項所述之低應力晶片封裝陣列製造方法，其中在該晶片的該角落區、該周圍邊緣區及該中心區中的大部分的該阻焊層為開通的或僅有部分的該阻焊層是開通的。
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