TWI685074B - 晶片封裝結構及相關引腳接合方法 - Google Patents

晶片封裝結構及相關引腳接合方法 Download PDF

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TWI685074B
TWI685074B TW106134885A TW106134885A TWI685074B TW I685074 B TWI685074 B TW I685074B TW 106134885 A TW106134885 A TW 106134885A TW 106134885 A TW106134885 A TW 106134885A TW I685074 B TWI685074 B TW I685074B
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Taiwan
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gold bump
pin
bonding surface
plane
width
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TW106134885A
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English (en)
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TW201830623A (zh
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張盈楨
陳柏琦
曾國瑋
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矽創電子股份有限公司
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Abstract

一種晶片封裝結構，包含有一晶片以及一軟性薄膜基板。該晶片形成有一金凸塊，該軟性薄膜基板形成有一引腳，其中該金凸塊包含一第一接合面以及數個側壁。該金凸塊透過一共晶材料包覆層，電性連接該引腳，且該共晶材料包覆層覆蓋該第一接合面以及該數個側壁的至少一個。

Description

晶片封裝結構及相關引腳接合方法
本發明係關於一種晶片封裝結構及相關引腳的接合方法，尤其是關於一種採用非嵌入式接合的晶片封裝結構及相關引腳的接合方法。
薄膜覆晶(Chip on Film，COF)封裝是一種將晶粒覆晶接合(Flip Chip Bonding)在軟性薄膜基板(Film Substrate)上的技術，以取代傳統打線(Wire Bonding)方式。透過薄膜覆晶封裝，可運用軟性薄膜基板作為晶片的載體，透過將晶片上的金凸塊(Gold Bump)與軟性薄膜基板上的引腳接合(Inner Lead Bonding)，以將晶片及其電子零件直接安置於軟性薄膜基板上。如此可省去傳統的印刷電路板，達到更輕薄短小的目的。
為了因應晶片性能提升(例如：解析度增加)，或者為符合元件輕薄短小的需求，引腳接合技術面臨了高腳數(High Pin Count)和細間距(Fine Pitch)的設計挑戰。由於細間距引腳或金凸塊接合的精密度要求較高，因此在設計對應封裝技術時，須考量引腳尺寸、金凸塊尺寸、共晶材料、接合應力以及焊接溫度等參數並加以優化分析，使得引腳與金凸塊的接點具有良好的導電性、機械結合度以及足夠的可靠度。
第1圖為一晶片封裝結構1進行引腳接合操作在一XZ平面上的第一視角圖(沿一Y方向)。晶片封裝結構1包含一晶片10、一金凸塊(Gold Bump)11、一引腳(Inner Lead)12以及一軟性薄膜基板(Film substrate)13。晶片10包含一晶粒(Die)100、至少一接墊(Pad)101以及一保護層(Passivation layer)102。
接墊101電性連接晶粒100，用來作為晶粒100的訊號通道。保護層102覆蓋晶粒100，其中保護層102形成有一開口(Passivation opening)103，以作為接墊101與金凸塊11的連接通道。由於開口103的結構設計，當金凸塊11經由高溫熔解而設置於晶片10上時，液態的金凸塊11會呈現凹陷表面113，其中開口103面積會影響凹陷表面113占整體表面積的比例(例如95%)。另一方面，引腳12形成於軟性薄膜基板13上，且引腳12的表面平整。
金凸塊11與引腳12可採用熱壓合方式來進行接合，以接合金凸塊11及引腳12。進一步地，為了讓金凸塊11的凹陷表面113與引腳12的接觸面積最大化，因此在接合時會施加一壓力或應力，讓引腳12嵌入金凸塊11，使得引腳12確實接觸金凸塊11的凹陷表面113，如此可確保接合強度，以避免晶片封裝結構1因封裝製程本身或是成品運送過程所導致的脫落與接觸不良問題。然而，上述施加壓力的接合方式存有晶片封裝結構1受損的風險，進而導致良率問題。例如，施加壓力可能會破壞金凸塊11下方的接墊101、保護層102及晶粒100等元件，導致晶片封裝結構1受損。
此外，為了確保引腳12能夠被嵌入金凸塊11，需要設計讓金凸塊11的寬度大於引腳12的寬度，以確保接合強度。然而，增加金凸塊11寬度，不僅會減少在單位面積下的訊號通道數，也會增加金凸塊11的材料使用量，導致製造 成本上升。
因此，實有必要提供一種晶片封裝結構及相關引腳接合方法，以符合上述需求。
因此，本發明的主要目的即在於提供一種晶片封裝結構及相關引腳接合方法，以符合上述需求。
本發明揭露一種晶片封裝結構，包含有一晶片，形成有一金凸塊；以及一軟性薄膜基板，形成有一引腳；其中該金凸塊包含一第一接合面以及數個側壁，該金凸塊透過一共晶材料包覆層電性連接該引腳，且該共晶材料包覆層覆蓋該第一接合面以及該數個側壁的至少一個。
本發明另揭露一種引腳接合方法，用於一晶片封裝結構，其中該晶片封裝結構包含一晶片以及一軟性薄膜基板。該方法包含有：將一金凸塊的一第一接合面接觸一引腳；將該金凸塊與該引腳加熱至一溫度範圍以於該金凸塊與該引腳之間形成一共晶材料包覆層；以及維持一預定時間，使該共晶材料包覆層覆蓋該第一接合面以及該數個側壁的至少一個。
本發明利用共晶材料包覆層形成於金凸塊表面時所產生的毛細效應，讓共晶材料包覆層在無施加外力的情況下，流向金凸塊的接合面以及至少一側壁，以增加共晶材料包覆層的覆蓋面積，如此可實現非嵌入式接合，以提升引腳與金凸塊的接合強度、降低接合阻抗、降低形變、避免結構損壞及降低 導線短路風險。再者，本發明的晶片封裝結構藉由縮減引腳與金凸塊尺寸，以實現細間距、提升灌封膠材流動性、增加散熱空間、節省原料使用、提升封裝精準度(容錯率)以及減少測試針刺造成的短路風險。
1、2、3‧‧‧晶片封裝結構
10、20、30‧‧‧晶片
11、21、31‧‧‧金凸塊
12、22、32‧‧‧引腳
13、23、33‧‧‧軟性薄膜基板
14、24、34‧‧‧共晶材料包覆層
100、200‧‧‧晶粒
101、201‧‧‧接墊
102、202‧‧‧保護層
103、203‧‧‧開口
211、211(1)、211(2)、311‧‧‧第一接合面
221、221(1)、221(2)、321‧‧‧第二接合面
212_L、212_R、212_B、312_L、312_R‧‧‧側壁
113、213‧‧‧凹陷表面
W21、W22、W31、W32‧‧‧寬度
X、Y、Z‧‧‧方向
GP1、GP2‧‧‧距離
A1、A2‧‧‧截面積
PCH‧‧‧間距
BP‧‧‧斷裂點
ANG1、ANG2‧‧‧角度
130‧‧‧流程
1300、1301、1302、1303、1304‧‧‧步驟
第1圖為一晶片封裝結構進行引腳接合操作的第一視角圖(XZ平面)。
第2圖為本發明實施例一晶片封裝結構進行引腳接合操作的第一視角圖(XZ平面)。
第3圖繪示本發明實施例引腳接合後的拉伸實驗結果。
第4圖為本發明實施例晶片封裝結構2的第二視角圖(YZ平面)。
第5圖為本發明實施例晶片封裝結構2的第三視角圖(XY平面)。
第6圖繪示引腳寬度與彎折次數的範例關係圖。
第7圖繪示金凸塊與引腳的空間配置比較圖。
第8圖為第1圖的晶片封裝結構的倒置第一視角圖(XZ平面)。
第9圖為本發明實施例第2圖的晶片封裝結構的倒置第一視角圖(XZ平面)。
第10圖為第8圖的晶片封裝結構的等角視圖。
第11圖為第9圖的晶片封裝結構的等角視圖。
第12圖為本發明實施例另一晶片封裝結構的倒置第一視角圖(XZ平面)。
第13圖本發明實施例一引腳接合流程的流程圖。
第2圖為本發明實施例一晶片封裝結構2進行引腳接合操作在一XZ平 面上的第一視角圖(沿一Y方向)。晶片封裝結構2包含一晶片20、一金凸塊21、一引腳22以及一軟性薄膜基板23。晶片20包含一晶粒200、至少一接墊201以及一保護層202。引腳22形成於軟性薄膜基板23上。
金凸塊21沿Y方向延伸，包含一第一接合面211以及數個側壁，各該數個側壁連接於該第一接合面211且為該金凸塊21的外周壁。引腳22沿Y方向延伸，包含一第二接合面221。金凸塊21的第一接合面211朝向引腳22的第二接合面221.使金凸塊21能夠與引腳22接合，例如引腳22的第二接合面221朝向-Z方向以接合金凸塊21的第一接合面211。
接墊201電性連接晶粒200，用來作為晶粒200的訊號通道。保護層202覆蓋晶粒200，其中保護層202形成有一開口203，以作為接墊201與金凸塊21的連接通道。值得注意的是，相較於第1圖的開口103，藉由讓保護層202的開口203面積減小(例如XY平面的面積減小)，可使金凸塊21的凹陷表面213占整體表面積的比例下降(例如5%)，因此金凸塊21的第一接合面211趨於平整而近似平面。另一方面，引腳22形成於軟性薄膜基板23上，且引腳22的表面平整。
金凸塊21與引腳22之間形成有一共晶材料包覆層(Eutectic Material Coverage，EMC)24，透過加熱並維持一段時間讓部分金凸塊21與部分引腳22形成合金，可形成共晶材料包覆層24。由於金凸塊21的第一接合面211近似平面，而小部分的凹陷表面213可被共晶材料包覆層24填滿，因此金凸塊21可透過共晶材料包覆層24電性連接引腳22，且共晶材料包覆層24覆蓋第一接合面211、第二接合面221以及數個側壁中的至少一個。
金凸塊21的數個側壁包含一第一側壁212_L及一第二側壁212_R。第一側壁212_L及第二側壁212_R平行於YZ平面且垂直於第一接合面221(例如，XY平面)以及X方向，且共晶材料包覆層24覆蓋第一側壁212_L及第二側壁212_R。在此結構下，可使金凸塊21與引腳22接合能夠抵抗X方向的外力，以增加接合強度。
金凸塊21的數個側壁還包含一第三側壁212_B，第三側壁212_B平行於XZ平面且垂直於第一接合面221以及Y方向，且共晶材料包覆層24覆蓋第三側壁212_B。在此結構下，可使金凸塊21與引腳22接合能夠抵抗Y方向的外力，以增加接合強度。
在進行金凸塊21與引腳22的接合時，可將金凸塊21的第一接合面211接觸引腳22的第二接合面221，再將金凸塊21與引腳22加熱至一溫度範圍以於該金凸塊與該引腳之間形成共晶材料包覆層24，最後維持一預定時間，使共晶材料包覆層24覆蓋第一接合面211、第二接合面221以及數個側壁212_L、212_R及212_B中的至少一個。於一實施例中，溫度範圍例如是400℃~500℃，預定時間例如是0.1~2秒。由於金凸塊21的第一接合面211近似平面，而小部分的凹陷表面213可被共晶材料包覆層24填滿，因此只需讓第一接合面211接觸第二接合面221，即可維持接合強度。
金凸塊21的寬度W21及引腳22的寬度W22分別是指引腳22及金凸塊21在X方向上的尺寸，其中X、Y、Z方向相互垂直。於一實施例中，金凸塊21的寬度W21可小於或等於引腳22的寬度W22，如此可使晶片封裝結構2在不需施加壓力的情況下進行引腳接合。
於第1圖的晶片封裝結構1中，金凸塊11的寬度大於引腳12的寬度，如此設計不僅會減少在單位面積下的訊號通道數，也會增加金凸塊11的材料使用量，導致製造成本上升；相較之下，晶片封裝結構2中的金凸塊21的寬度W21可小於或等於引腳22的寬度W22，如此可增加在單位面積下的訊號通道數，也可減少金凸塊21的材料使用量，以節省製造成本。
由於本發明實施例晶片封裝結構2是透過共晶材料包覆層24覆蓋第一接合面211、第二接合面221以及數個側壁212_L、212_R及212_B中的至少一個，以接合金凸塊21及引腳22。因此，接合時只需讓金凸塊21的第一接合面211接觸引腳22的第二接合面221即可，無須施加壓力讓引腳22嵌入金凸塊21。如此可省去嵌入接合所需的應力及壓力分析，有效簡化製程步驟，也可避免施加壓力所導致的結構受損風險，以實現非嵌入式接合。
第3圖繪示本發明實施例引腳接合後的拉伸實驗結果。由第3圖可看出，除了引腳22與金凸塊21的接合面(相當於第一接合面211、第二接合面221)，金凸塊21的側壁212_R、212_L、212_B及接合面211的延伸區域211_E會因為毛細效應而被共晶材料包覆層24所包覆。
詳細來說，金凸塊21的表面粗糙而形成非平滑表面，因此當高溫液態的共晶材料包覆層24形成於金凸塊21表面時，將產生毛細效應，讓共晶材料包覆層24流向金凸塊21的側壁212_R、212_L、212_B及第一接合面211的延伸區域211_E，以增加共晶材料包覆層24的覆蓋面積，並提升引腳22與金凸塊21的接合強度。再者，由於金凸塊21被共晶材料包覆層24覆蓋的面積增加，可提升金凸塊 21的強度並減少金凸塊21在接合後發生形變的情況，以降低短路風險；同時，共晶材料包覆層24覆蓋的面積增加，可降低引腳22與金凸塊21間的阻抗，以提升導電率。進一步地，當金凸塊21尺寸縮小後，可減少接合時熱膨脹效應所造成的影響，亦能提高封裝容錯率(tolerance)並增進封裝良率。
由第3圖可看出，拉伸實驗係施以一外力以分離金凸塊21及引腳22，結果顯示引腳22無法承受外力而斷裂，且斷裂點BP位於共晶材料包覆層24覆蓋以外的區域，可見引腳22與金凸塊21的接合強度優於引腳22本身的抗拉強度。再者，由於金凸塊21表面較粗糙，且共晶材料包覆層24會覆蓋其表面及側壁而不至於沿流至引腳22間形成短路。換言之，在引腳22寬度實質上大於等於金凸塊21寬度的條件下，可避免引腳22相互短路的風險。
第4圖為本發明實施例晶片封裝結構2在YZ平面上的第二視角圖(沿X方向)。第5圖為本發明實施例晶片封裝結構2在XY平面上的第三視角圖(沿Z方向)。如第4圖及第5圖所示，引腳22的第二接合面221(1)與金凸塊21的第一接合面211(1)在XY平面的投影完全重疊；或者，引腳22的第二接合面221(2)與金凸塊21的第一接合面211(2)在XY平面的投影部分重疊。由於共晶材料包覆層24可覆蓋金凸塊21的側壁212，因此在第一接合面211(2)與第二接合面221(2)部分重疊的情況下，仍可維持良好的接合度。
第6圖繪示引腳寬度與彎折次數的範例關係圖。在基板面積與引腳數量固定的情況下，當引腳間距越小，則引腳寬度越大，且引腳的機械強度(耐彎折強度)越高。於第6圖中，當引腳寬度由12微米增加到21.9微米時，彎折次數由400次增加到650次。因此，增加引腳寬度可增加彎折次數，以提升引腳的機 械強度。
第7圖繪示金凸塊與引腳的空間配置比較圖。在實際應用中，考量引腳接合的封裝製程精準度以及金凸塊和引腳的生產容錯率，一般而言，內排金凸塊對應的引腳與外排金凸塊邊緣的距離至少大於6微米，以避免封裝製程偏移造成短路風險。
根據第2圖可知，本發明實施例晶片封裝結構2的金凸塊21的寬度W21實質上小於或等於引腳22的寬度W22，相當於縮減金凸塊21的寬度W21，有助於增加一金凸塊21對應的引腳22與相鄰的另一金凸塊21邊緣的距離。詳言之，於一實施例中，當金凸塊21的寬度W21實質上小於引腳22的寬度W22時，例如金凸塊寬度W21為7微米，且引腳最大寬度W22為9微米時，引腳與外排金凸塊邊緣的距離GP1為7微米，如此可避免封裝製程偏移造成短路風險。於另一實施例中，當金凸塊21的寬度W21實質上等於引腳22的寬度W22時，例如金凸塊寬度W21為7微米，且引腳最大寬度W22為7微米時，引腳與外排金凸塊邊緣的距離GP2為8微米，如此可避免封裝製程偏移造成短路風險。
第8圖為現有晶片封裝結構1在XZ平面上的倒置第一視角圖，第9圖為本發明實施例晶片封裝結構2在XZ平面上的倒置第一視角圖。於第8圖中，金凸塊11的寬度大於引腳12的寬度；於第9圖中，金凸塊21的寬度小於引腳22的寬度。
比較第8圖與第9圖可看出，在相同間距(Pitch)PCH的情況下，晶片封裝結構1的兩個引腳12之間的截面積A1小於晶片封裝結構2的兩個引腳22之間截面積A2；此外，截面積A1的邊緣形狀較崎嶇(例如，金凸塊11與引腳12接合 處的邊角角度ANG1實質上小於90度)，而截面積A2的邊緣形狀較平整(例如，金凸塊21與引腳22接合處的邊角角度ANG2實質上大於90度)。再者，由於截面積A2大於截面積A1，故晶片封裝結構2的散熱空間較大，因此可提升散熱能力。
此外，金凸塊21的寬度小於金凸塊11的寬度(X方向的尺寸)，且引腳22的高度小大於引腳12的高度(Z方向的尺寸)，如此可節省原料使用(例如，黃金及銅等金屬)，讓晶片封裝結構2的成本更具優勢。引腳22的高度(Z方向的尺寸)小於引腳12的高度(Z方向的尺寸)，故引腳22與晶片20的距離大於引腳12與晶片10的距離，如此可讓晶片封裝結構2進行封裝測試時，減少測試針刺(test key burr)造成的短路風險。
第10圖為第8圖中現有晶片封裝結構1的等角視圖。如第10圖所示，在進行灌封(potting)製程時，由於晶片封裝結構1的截面積A1的邊緣形狀較崎嶇，此結構會使灌封膠材(potting glue)遭遇邊角或隙縫地形而產生紊流，進而導致膠材流動性不佳而讓氣泡滯留於晶片封裝結構1的情況。
第11圖為第10圖中本發明實施例晶片封裝結構2的等角視圖。如第11圖所示，相較之下，由於晶片封裝結構2的截面積A2的邊緣形狀較平整且面積較大，此結構有利於提供灌封膠材更大的流動空間以提升膠材流動性，進而降低氣泡滯留於晶片封裝結構2的情況，以提升灌封樹脂(potting resin)的均勻性。
第12圖為本發明實施例一晶片封裝結構3在一XZ平面上的第一視角圖(沿Y方向)。晶片封裝結構3包含一晶片30、一金凸塊31、一引腳32以及軟性薄膜基板33。金凸塊31包含一第一接合面311以及數個側壁313_L、313_R，各個 側壁313_L、313_R連接於該第一接合面311且為金凸塊31的外周壁。引腳32包含一第二接合面321。
金凸塊31與引腳32之間形成有共晶材料包覆層34，透過加熱並維持一段時間讓部分金凸塊31與部分引腳32形成合金，可以形成共晶材料包覆層34，其中金凸塊31可透過共晶材料包覆層34電性連接引腳32，且共晶材料包覆層34覆蓋第一接合面311、第二接合面321以及數個側壁33中的至少一個。
值得注意的是，金凸塊31的寬度W31及引腳32的寬度W32分別是指引腳32及金凸塊31在X方向上的尺寸。於本實施例中，金凸塊31的寬度W31大於引腳32的寬度W32。在適當控制寬度W31及W32差異的情況下，仍可實現非嵌入式接合，使共晶材料包覆層34覆蓋第一接合面311、第二接合面321以及該數個側壁313_L、313_R中的至少一個。
上述關於晶片封裝結構2或3的製造方式可歸納為一引腳接合流程130，如第13圖所示，其中引腳接合流程130可包含以下步驟。
步驟1300：於一晶片形成一金凸塊，該金凸塊具有一第一接合面以及數個側壁。
步驟1301：於一軟性薄膜基板形成一引腳，該引腳具有一第二接合面。
步驟1302：將該金凸塊的第一接合面接觸該引腳的第二接合面。
步驟1303：加熱至一溫度範圍(400℃~500℃)以於該金凸塊與該引腳之間形成一共晶材料包覆層。
步驟1304：維持一預定時間(0.1~2秒)，使該共晶材料包覆層覆蓋該 第一接合面、第二接合面以及該數個側壁中的至少一個。
上述關於引腳接合流程130的詳細操作方式可參考第2圖的相關描述，於此不贅述。
綜上所述，本發明利用共晶材料包覆層形成於金凸塊表面時所產生的毛細效應，讓共晶材料包覆層在無施加外力的情況下，流向金凸塊的至少一側壁，以增加共晶材料包覆層的覆蓋面積，如此可實現非嵌入式接合，以提升引腳與金凸塊的接合強度、降低接合阻抗、降低形變、結構損壞及導線短路風險。再者，本發明的晶片封裝結構藉由縮減引腳與金凸塊尺寸，以實現細間距、提升灌封膠材流動性、增加散熱空間、節省原料使用、提升封裝精準度(容錯率)以及減少測試針刺造成的短路風險。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
2‧‧‧晶片封裝結構
20‧‧‧晶片
21‧‧‧金凸塊
22‧‧‧引腳
23‧‧‧軟性薄膜基板
24‧‧‧共晶材料包覆層
200‧‧‧晶粒
201‧‧‧接墊
202‧‧‧保護層
203‧‧‧開口
211‧‧‧第一接合面
221‧‧‧第二接合面
212_L、212_R‧‧‧側壁
213‧‧‧凹陷表面
W21、W22‧‧‧寬度
X、Y、Z‧‧‧方向

Claims (18)

  1. 項】一種晶片封裝結構，包含有：一晶片，形成有一金凸塊；以及一軟性薄膜基板，形成有一引腳；其中該金凸塊包含一第一接合面以及數個側壁，該金凸塊透過一共晶材料包覆層電性連接該引腳，其中該共晶材料包覆層為因毛細效應而流向該金凸塊的該數個側壁的構造，且該共晶材料包覆層覆蓋該金凸塊的該第一接合面以及該金凸塊的該數個側壁的至少一個，其中該第一接合面或該數個側壁中至少一者為非平滑表面。
  2. 如請求項1所述的結構，其中該引腳及該金凸塊沿一第一方向延伸，該金凸塊朝一第二方向接觸該引腳，該金凸塊的寬度及該引腳的寬度分別是該引腳及該金凸塊在一第三方向上的尺寸，且該第一方向、該第二方向及該第三方向相互垂直。
  3. 如請求項2所述的結構，其中該金凸塊的寬度小於或等於該引腳的寬度。
  4. 如請求項2所述的結構，其中該金凸塊的寬度大於該引腳的寬度。
  5. 如請求項2所述的結構，其中該引腳包含一第二接合面，該第二接合面沿該第二方向朝向該金凸塊的該第一接合面，該共晶材料包覆層覆蓋該第二接合面。
  6. 如請求項5所述的結構，其中該第二接合面與該第一接合面平行於一第一平面，該第二接合面與該第一接合面在該第一平面的投影部分重疊或完全重疊，該數個側壁平行於一第二平面，且該第一平面垂直於該第二平面。
  7. 如請求項5所述的結構，其中該第二接合面與該第一接合面平行於一第一平面，該數個側壁平行於一第二平面，該第一平面垂直於該第二平面，該數個側壁包含：一第一側壁，連接該第一接合面，垂直於該第一接合面以及該第三方向；以及一第二側壁，連接該第一接合面，垂直於該第一接合面以及該第三方向，該共晶材料包覆層覆蓋該第一側壁及該第二側壁。
  8. 如請求項7所述的結構，其中該金凸塊包含：一第三側壁，連接該第一接合面、該第一側壁以及該第二側壁，垂直於該第一接合面以及該第一方向，且該共晶材料包覆層覆蓋該三側壁。
  9. 一種引腳接合方法，用於一晶片封裝結構，其中該晶片封裝結構包含一晶片以及一軟性薄膜基板，該方法包含有：將該晶片的一金凸塊的一第一接合面接觸該軟性薄膜基板的一引腳；將該金凸塊與該引腳加熱至一溫度範圍以於該金凸塊與該引腳之間形成一共晶材料包覆層；以及維持一預定時間，讓該共晶材料包覆層於該第一接合面上產生一毛細效應，使該共晶材料包覆層流向該金凸塊的數個側壁，以使該共晶材料包覆層 覆蓋該金凸塊的該第一接合面以及該金凸塊的該數個側壁的至少一個。
  10. 如請求項9所述的方法，另包含：於該晶片形成該金凸塊；以及於該軟性薄膜基板形成該引腳。
  11. 如請求項9所述的方法，其中該引腳及該金凸塊沿一第一方向延伸，該金凸塊朝一第二方向接觸該引腳，該金凸塊的寬度及該引腳的寬度分別是該引腳及該金凸塊在一第三方向上的尺寸，且該第一方向、該第二方向及該第三方向相互垂直。
  12. 如請求項11所述的方法，其中該金凸塊的寬度小於或等於該引腳的寬度。
  13. 如請求項11所述的方法，其中該金凸塊的寬度大於該引腳的寬度。
  14. 如請求項9所述的方法，其中該引腳包含一第二接合面，該第二接合面朝向該金凸塊的第一接合面，該共晶材料包覆層覆蓋該第二接合面。
  15. 如請求項14所述的方法，其中該第二接合面與該第一接合面平行於一第一平面，該第二接合面與該第一接合面在該第一平面的投影部分重疊或完全重疊，該數個側壁平行於一第二平面，且該第一平面垂直於該第二平面。
  16. 如請求項14所述的方法，其中該第二接合面與該第一接合面平行於一第一平面，該數個側壁平行於一第二平面，該第一平面垂直於該第二平面，該數個側壁包含：一第一側壁，連接該第一接合面，垂直於該第一接合面以及該第三方向；以及一第二側壁，連接該第一接合面，垂直於該第一接合面以及該第三方向，該共晶材料包覆層覆蓋該第一側壁及該第二側壁。
  17. 如請求項16所述的方法，其中該金凸塊包含：一第三側壁，連接該第一接合面、該第一側壁以及該第二側壁，垂直於該第一接合面以及該第一方向，且該共晶材料包覆層覆蓋該三側壁。
  18. 如請求項9所述的方法，其中溫度範圍是400℃~500℃，該預定時間是0.1~2秒。
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KR102047775B1 (ko) 2019-11-22
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