CN107978582A - 芯片封装结构及相关引脚接合方法 - Google Patents

芯片封装结构及相关引脚接合方法 Download PDF

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CN107978582A
CN107978582A CN201710955168.1A CN201710955168A CN107978582A CN 107978582 A CN107978582 A CN 107978582A CN 201710955168 A CN201710955168 A CN 201710955168A CN 107978582 A CN107978582 A CN 107978582A
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pin
convex block
composition surface
chip
plane
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CN107978582B (zh
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张盈桢
陈柏琦
曾国玮
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Sitronix Technology Corp
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Sitronix Technology Corp
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Abstract

本发明公开了一种芯片封装结构，包含有一芯片以及一软性薄膜基板。该芯片形成有一金凸块，该软性薄膜基板形成有一引脚，其中该金凸块包含一第一接合面以及数个侧壁。该金凸块通过一共晶材料包覆层，电性连接该引脚，且该共晶材料包覆层覆盖该第一接合面以及该数个侧壁的至少一个。

Description

芯片封装结构及相关引脚接合方法
技术领域
本发明涉及一种芯片封装结构及相关引脚的接合方法，尤其涉及一种采用非嵌入式接合的芯片封装结构及相关引脚的接合方法。
背景技术
薄膜覆晶(Chip on Film，COF)封装是一种将晶粒覆晶接合(Flip Chip Bonding)在软性薄膜基板(Film Substrate)上的技术，以取代传统打线(Wire Bonding)方式。通过薄膜覆晶封装，可运用软性薄膜基板作为芯片的载体，通过将芯片上的金凸块(Gold Bump)与软性薄膜基板上的引脚接合(Inner Lead Bonding)，以将芯片及其电子零件直接安置于软性薄膜基板上。如此可省去传统的印刷电路板，达到更轻薄短小的目的。
为了因应芯片性能提升(例如：分辨率增加)，或者为符合组件轻薄短小的需求，引脚接合技术面临了高脚数(High Pin Count)和细间距(Fine Pitch)的设计挑战。由于细间距引脚或金凸块接合的精密度要求较高，因此在设计对应封装技术时，须考虑引脚尺寸、金凸块尺寸、共晶材料、接合应力以及焊接温度等参数并加以优化分析，使得引脚与金凸块的接点具有良好的导电性、机械结合度以及足够的可靠度。
图1为一芯片封装结构1进行引脚接合操作在一XZ平面上的第一视角图(沿一Y方向)。芯片封装结构1包含一芯片10、一金凸块(Gold Bump)11、一引脚(Inner Lead)12以及一软性薄膜基板(Film substrate)13。芯片10包含一晶粒(Die)100、至少一接垫(Pad)101以及一保护层(Passivation layer)102。
接垫101电性连接晶粒100，用来作为晶粒100的信号通道。保护层102覆盖晶粒100，其中保护层102形成有一开口(Passivation opening)103，以作为接垫101与金凸块11的连接通道。由于开口103的结构设计，当金凸块11经由高温熔解而设置于芯片10上时，液态的金凸块11会呈现凹陷表面113，其中开口103面积会影响凹陷表面113占整体表面积的比例(例如95％)。另一方面，引脚12形成于软性薄膜基板13上，且引脚12的表面平整。
金凸块11与引脚12可采用热压合方式来进行接合，以接合金凸块11及引脚12。进一步地，为了让金凸块11的凹陷表面113与引脚12的接触面积最大化，因此在接合时会施加一压力或应力，让引脚12嵌入金凸块11，使得引脚12确实接触金凸块11的凹陷表面113，如此可确保接合强度，以避免芯片封装结构1因封装工艺本身或是成品运送过程所导致的脱落与接触不良问题。然而，上述施加压力的接合方式存有芯片封装结构1受损的风险，进而导致良率问题。例如，施加压力可能会破坏金凸块11下方的接垫101、保护层102及晶粒100等组件，导致芯片封装结构1受损。
此外，为了确保引脚12能够被嵌入金凸块11，需要设计让金凸块11的宽度大于引脚12的宽度，以确保接合强度。然而，增加金凸块11宽度，不仅会减少在单位面积下的信号通道数，也会增加金凸块11的材料使用量，导致制造成本上升。
因此，实有必要提供一种芯片封装结构及相关引脚接合方法，以符合上述需求。
发明内容
因此，本发明的主要目的即在于提供一种芯片封装结构及相关引脚接合方法，以符合上述需求。
本发明公开一种芯片封装结构，包含有一芯片，形成有一金凸块；以及一软性薄膜基板，形成有一引脚；其中该金凸块包含一第一接合面以及数个侧壁，该金凸块通过一共晶材料包覆层电性连接该引脚，且该共晶材料包覆层覆盖该第一接合面以及该数个侧壁的至少一个。
本发明还公开一种引脚接合方法，用于一芯片封装结构，其中该芯片封装结构包含一芯片以及一软性薄膜基板。该方法包含有：将一金凸块的一第一接合面接触一引脚；将该金凸块与该引脚加热至一温度范围以于该金凸块与该引脚之间形成一共晶材料包覆层；以及维持一预定时间，使该共晶材料包覆层覆盖该第一接合面以及该数个侧壁的至少一个。
本发明利用共晶材料包覆层形成于金凸块表面时所产生的毛细效应，让共晶材料包覆层在无施加外力的情况下，流向金凸块的接合面以及至少一侧壁，以增加共晶材料包覆层的覆盖面积，如此可实现非嵌入式接合，以提升引脚与金凸块的接合强度、降低接合阻抗、降低形变、避免结构损坏及降低导线短路风险。再者，本发明的芯片封装结构借由缩减引脚与金凸块尺寸，以实现细间距、提升灌封胶材流动性、增加散热空间、节省原料使用、提升封装精准度(容错率)以及减少测试针刺造成的短路风险。
附图说明
图1为一芯片封装结构进行引脚接合操作的第一视角图(XZ平面)。
图2为本发明实施例一芯片封装结构进行引脚接合操作的第一视角图(XZ平面)。
图3绘示本发明实施例引脚接合后的拉伸实验结果。
图4为本发明实施例芯片封装结构2的第二视角图(YZ平面)。
图5为本发明实施例芯片封装结构2的第三视角图(XY平面)。
图6绘示引脚宽度与弯折次数的范例关系图。
图7绘示金凸块与引脚的空间配置比较图。
图8为图1的芯片封装结构的倒置第一视角图(XZ平面)。
图9为本发明实施例图2的芯片封装结构的倒置第一视角图(XZ平面)。
图10为图8的芯片封装结构的等角视图。
图11为图9的芯片封装结构的等角视图。
图12为本发明实施例另一芯片封装结构的倒置第一视角图(XZ平面)。
图13为本发明实施例一引脚接合流程的流程图。
其中，附图标记说明如下：
1、2、3 芯片封装结构
10、20、30 芯片
11、21、31 金凸块
12、22、32 引脚
13、23、33 软性薄膜基板
14、24、34 共晶材料包覆层
100、200 晶粒
101、201 接垫
102、202 保护层
103、203 开口
211、211(1)、211(2)、311 第一接合面
221、221(1)、221(2)、321 第二接合面
212_L、212_R、212_B、312_L、312_R 侧壁
113、213 凹陷表面
W21、W22、W31、W32 宽度
X、Y、Z 方向
GP1、GP2 距离
A1、A2 截面积
PCH 间距
BP 断裂点
ANG1、ANG2 角度
130 流程
1300、1301、1302、1303、1304 步骤
具体实施方式
图2为本发明实施例一芯片封装结构2进行引脚接合操作在一XZ平面上的第一视角图(沿一Y方向)。芯片封装结构2包含一芯片20、一金凸块21、一引脚22以及一软性薄膜基板23。芯片20包含一晶粒200、至少一接垫201以及一保护层202。引脚22形成于软性薄膜基板23上。
金凸块21沿Y方向延伸，包含一第一接合面211以及数个侧壁，各该数个侧壁连接于该第一接合面211且为该金凸块21的外周壁。引脚22沿Y方向延伸，包含一第二接合面221。金凸块21的第一接合面211朝向引脚22的第二接合面221，使金凸块21能够与引脚22接合，例如引脚22的第二接合面221朝向-Z方向以接合金凸块21的第一接合面211。
接垫201电性连接晶粒200，用来作为晶粒200的信号通道。保护层202覆盖晶粒200，其中保护层202形成有一开口203，以作为接垫201与金凸块21的连接通道。值得注意的是，相较于图1的开口103，借由让保护层202的开口203面积减小(例如XY平面的面积减小)，可使金凸块21的凹陷表面213占整体表面积的比例下降(例如5％)，因此金凸块21的第一接合面211趋于平整而近似平面。另一方面，引脚22形成于软性薄膜基板23上，且引脚22的表面平整。
金凸块21与引脚22之间形成有一共晶材料包覆层(Eutectic MaterialCoverage，EMC)24，通过加热并维持一段时间让部分金凸块21与部分引脚22形成合金，可形成共晶材料包覆层24。由于金凸块21的第一接合面211近似平面，而小部分的凹陷表面213可被共晶材料包覆层24填满，因此金凸块21可通过共晶材料包覆层24电性连接引脚22，且共晶材料包覆层24覆盖第一接合面211、第二接合面221以及数个侧壁中的至少一个。
金凸块21的数个侧壁包含一第一侧壁212_L及一第二侧壁212_R。第一侧壁212_L及第二侧壁212_R平行于YZ平面且垂直于第一接合面221(例如，XY平面)以及X方向，且共晶材料包覆层24覆盖第一侧壁212_L及第二侧壁212_R。在此结构下，可使金凸块21与引脚22接合能够抵抗X方向的外力，以增加接合强度。
金凸块21的数个侧壁还包含一第三侧壁212_B，第三侧壁212_B平行于XZ平面且垂直于第一接合面221以及Y方向，且共晶材料包覆层24覆盖第三侧壁212_B。在此结构下，可使金凸块21与引脚22接合能够抵抗Y方向的外力，以增加接合强度。
在进行金凸块21与引脚22的接合时，可将金凸块21的第一接合面211接触引脚22的第二接合面221，再将金凸块21与引脚22加热至一温度范围以于该金凸块与该引脚之间形成共晶材料包覆层24，最后维持一预定时间，使共晶材料包覆层24覆盖第一接合面211、第二接合面221以及数个侧壁212_L、212_R及212_B中的至少一个。于一实施例中，温度范围例如是400℃～500℃，预定时间例如是0.1～2秒。由于金凸块21的第一接合面211近似平面，而小部分的凹陷表面213可被共晶材料包覆层24填满，因此只要让第一接合面211接触第二接合面221，即可维持接合强度。
金凸块21的宽度W21及引脚22的宽度W22分别是指引脚22及金凸块21在X方向上的尺寸，其中X、Y、Z方向相互垂直。于一实施例中，金凸块21的宽度W21可小于或等于引脚22的宽度W22，如此可使芯片封装结构2在不需施加压力的情况下进行引脚接合。
于图1的芯片封装结构1中，金凸块11的宽度大于引脚12的宽度，如此设计不仅会减少在单位面积下的信号通道数，也会增加金凸块11的材料使用量，导致制造成本上升；相较之下，芯片封装结构2中的金凸块21的宽度W21可小于或等于引脚22的宽度W22，如此可增加在单位面积下的信号通道数，也可减少金凸块21的材料使用量，以节省制造成本。
由于本发明实施例芯片封装结构2是通过共晶材料包覆层24覆盖第一接合面211、第二接合面221以及数个侧壁212_L、212_R及212_B中的至少一个，以接合金凸块21及引脚22。因此，接合时只要让金凸块21的第一接合面211接触引脚22的第二接合面221即可，无须施加压力让引脚22嵌入金凸块21。如此可省去嵌入接合所需的应力及压力分析，有效简化工艺步骤，也可避免施加压力所导致的结构受损风险，以实现非嵌入式接合。
图3绘示本发明实施例引脚接合后的拉伸实验结果。由图3可看出，除了引脚22与金凸块21的接合面(相当于第一接合面211、第二接合面221)，金凸块21的侧壁212_R、212_L、212_B及接合面211的延伸区域211_E会因为毛细效应而被共晶材料包覆层24所包覆。
详细来说，金凸块21的表面粗糙而形成非平滑表面，因此当高温液态的共晶材料包覆层24形成于金凸块21表面时，将产生毛细效应，让共晶材料包覆层24流向金凸块21的侧壁212_R、212_L、212_B及第一接合面211的延伸区域211_E，以增加共晶材料包覆层24的覆盖面积，并提升引脚22与金凸块21的接合强度。再者，由于金凸块21被共晶材料包覆层24覆盖的面积增加，可提升金凸块21的强度并减少金凸块21在接合后发生形变的情况，以降低短路风险；同时，共晶材料包覆层24覆盖的面积增加，可降低引脚22与金凸块21间的阻抗，以提升导电率。进一步地，当金凸块21尺寸缩小后，可减少接合时热膨胀效应所造成的影响，亦能提高封装容错率(tolerance)并增进封装良率。
由图3可看出，拉伸实验是施以一外力以分离金凸块21及引脚22，结果显示引脚22无法承受外力而断裂，且断裂点BP位于共晶材料包覆层24覆盖以外的区域，可见引脚22与金凸块21的接合强度优于引脚22本身的抗拉强度。再者，由于金凸块21表面较粗糙，且共晶材料包覆层24会覆盖其表面及侧壁而不至于沿流至引脚22间形成短路。换言之，在引脚22宽度实质上大于等于金凸块21宽度的条件下，可避免引脚22相互短路的风险。
图4为本发明实施例芯片封装结构2在YZ平面上的第二视角图(沿X方向)。图5为本发明实施例芯片封装结构2在XY平面上的第三视角图(沿Z方向)。如图4及图5所示，引脚22的第二接合面221(1)与金凸块21的第一接合面211(1)在XY平面的投影完全交叠；或者，引脚22的第二接合面221(2)与金凸块21的第一接合面211(2)在XY平面的投影部分交叠。由于共晶材料包覆层24可覆盖金凸块21的侧壁212，因此在第一接合面211(2)与第二接合面221(2)部分交叠的情况下，仍可维持良好的接合度。
图6绘示引脚宽度与弯折次数的范例关系图。在基板面积与引脚数量固定的情况下，当引脚间距越小，则引脚宽度越大，且引脚的机械强度(耐弯折强度)越高。于图6中，当引脚宽度由12微米增加到21.9微米时，弯折次数由400次增加到650次。因此，增加引脚宽度可增加弯折次数，以提升引脚的机械强度。
图7绘示金凸块与引脚的空间配置比较图。在实际应用中，考虑引脚接合的封装工艺精准度以及金凸块和引脚的生产容错率，一般而言，内排金凸块对应的引脚与外排金凸块边缘的距离至少大于6微米，以避免封装工艺偏移造成短路风险。
根据图2可知，本发明实施例芯片封装结构2的金凸块21的宽度W21实质上小于或等于引脚22的宽度W22，相当于缩减金凸块21的宽度W21，有助于增加一金凸块21对应的引脚22与相邻的另一金凸块21边缘的距离。详言之，于一实施例中，当金凸块21的宽度W21实质上小于引脚22的宽度W22时，例如金凸块宽度W21为7微米，且引脚最大宽度W22为9微米时，引脚与外排金凸块边缘的距离GP1为7微米，如此可避免封装工艺偏移造成短路风险。于另一实施例中，当金凸块21的宽度W21实质上等于引脚22的宽度W22时，例如金凸块宽度W21为7微米，且引脚最大宽度W22为7微米时，引脚与外排金凸块边缘的距离GP2为8微米，如此可避免封装工艺偏移造成短路风险。
图8为现有芯片封装结构1在XZ平面上的倒置第一视角图，图9为本发明实施例芯片封装结构2在XZ平面上的倒置第一视角图。于图8中，金凸块11的宽度大于引脚12的宽度；于图9中，金凸块21的宽度小于引脚22的宽度。
比较图8与图9可看出，在相同间距(Pitch)PCH的情况下，芯片封装结构1的两个引脚12之间的截面积A1小于芯片封装结构2的两个引脚22之间截面积A2；此外，截面积A1的边缘形状较崎岖(例如，金凸块11与引脚12接合处的边角角度ANG1实质上小于90度)，而截面积A2的边缘形状较平整(例如，金凸块21与引脚22接合处的边角角度ANG2实质上大于90度)。再者，由于截面积A2大于截面积A1，故芯片封装结构2的散热空间较大，因此可提升散热能力。
此外，金凸块21的宽度小于金凸块11的宽度(X方向的尺寸)，且引脚22的高度小大于引脚12的高度(Z方向的尺寸)，如此可节省原料使用(例如，黄金及铜等金属)，让芯片封装结构2的成本更具优势。引脚22的高度(Z方向的尺寸)小于引脚12的高度(Z方向的尺寸)，故引脚22与芯片20的距离大于引脚12与芯片10的距离，如此可让芯片封装结构2进行封装测试时，减少测试针刺(test key burr)造成的短路风险。
图10为图8中现有芯片封装结构1的等角视图。如图10所示，在进行灌封(potting)工艺时，由于芯片封装结构1的截面积A1的边缘形状较崎岖，此结构会使灌封胶材(pottingglue)遭遇边角或隙缝地形而产生紊流，进而导致胶材流动性不佳而让气泡滞留于芯片封装结构1的情况。
图11为图10中本发明实施例芯片封装结构2的等角视图。如图11所示，相较之下，由于芯片封装结构2的截面积A2的边缘形状较平整且面积较大，此结构有利于提供灌封胶材更大的流动空间以提升胶材流动性，进而降低气泡滞留于芯片封装结构2的情况，以提升灌封树脂(potting resin)的均匀性。
图12为本发明实施例一芯片封装结构3在一XZ平面上的第一视角图(沿Y方向)。芯片封装结构3包含一芯片30、一金凸块31、一引脚32以及软性薄膜基板33。金凸块31包含一第一接合面311以及数个侧壁313_L、313_R，各个侧壁313_L、313_R连接于该第一接合面311且为金凸块31的外周壁。引脚32包含一第二接合面321。
金凸块31与引脚32之间形成有共晶材料包覆层34，通过加热并维持一段时间让部分金凸块31与部分引脚32形成合金，可以形成共晶材料包覆层34，其中金凸块31可通过共晶材料包覆层34电性连接引脚32，且共晶材料包覆层34覆盖第一接合面311、第二接合面321以及数个侧壁33中的至少一个。
值得注意的是，金凸块31的宽度W31及引脚32的宽度W32分别是指引脚32及金凸块31在X方向上的尺寸。于本实施例中，金凸块31的宽度W31大于引脚32的宽度W32。在适当控制宽度W31及W32差异的情况下，仍可实现非嵌入式接合，使共晶材料包覆层34覆盖第一接合面311、第二接合面321以及该数个侧壁313_L、313_R中的至少一个。
上述关于芯片封装结构2或3的制造方式可归纳为一引脚接合流程130，如图13所示，其中引脚接合流程130可包含以下步骤。
步骤1300：于一芯片形成一金凸块，该金凸块具有一第一接合面以及数个侧壁。
步骤1301：于一软性薄膜基板形成一引脚，该引脚具有一第二接合面。
步骤1302：将该金凸块的第一接合面接触该引脚的第二接合面。
步骤1303：加热至一温度范围(400℃～500℃)以于该金凸块与该引脚之间形成一共晶材料包覆层。
步骤1304：维持一预定时间(0.1～2秒)，使该共晶材料包覆层覆盖该第一接合面、第二接合面以及该数个侧壁中的至少一个。
上述关于引脚接合流程130的详细操作方式可参考图2的相关描述，于此不赘述。
综上所述，本发明利用共晶材料包覆层形成于金凸块表面时所产生的毛细效应，让共晶材料包覆层在无施加外力的情况下，流向金凸块的至少一侧壁，以增加共晶材料包覆层的覆盖面积，如此可实现非嵌入式接合，以提升引脚与金凸块的接合强度、降低接合阻抗、降低形变、结构损坏及导线短路风险。再者，本发明的芯片封装结构借由缩减引脚与金凸块尺寸，以实现细间距、提升灌封胶材流动性、增加散热空间、节省原料使用、提升封装精准度(容错率)以及减少测试针刺造成的短路风险。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (18)

1.一种芯片封装结构，包含有：
一芯片，形成有一金凸块；以及
一软性薄膜基板，形成有一引脚；
其中该金凸块包含一第一接合面以及数个侧壁，该金凸块通过一共晶材料包覆层电性连接该引脚，且该共晶材料包覆层覆盖该第一接合面以及该数个侧壁的至少一个。
2.如权利要求1所述的结构，其特征在于，该引脚及该金凸块沿一第一方向延伸，该金凸块朝一第二方向接触该引脚，该金凸块的宽度及该引脚的宽度分别是该引脚及该金凸块在一第三方向上的尺寸，且该第一方向、第二方向及该第三方向相互垂直。
3.如权利要求2所述的结构，其特征在于，该金凸块的宽度小于或等于该引脚的宽度。
4.如权利要求2所述的结构，其特征在于，该金凸块的宽度大于该引脚的宽度。
5.如权利要求1所述的结构，其特征在于，该引脚包含一第二接合面，该第二接合面沿该第二方向朝向该金凸块的该第一接合面，该共晶材料包覆层覆盖该第二接合面。
6.如权利要求5所述的结构，其特征在于，该第二接合面与该第一接合面平行于一第一平面，该第二接合面与该第一接合在该第一平面的投影部分交叠或完全交叠，该数个侧壁平行于一第二平面，且该第一平面垂直于该第二平面。
7.如权利要求2所述的结构，其特征在于，该第二接合面与该第一接合面平行于一第一平面，该数个侧壁平行于一第二平面，该第一平面垂直于该第二平面，该数个侧壁包含：
一第一侧壁，连接该第一接合面，垂直于该第一接合面以及该第三方向；以及
一第二侧壁，连接该第一接合面，垂直于该第一接合面以及该第三方向，该共晶材料包覆层覆盖该第一侧壁及该第二侧壁。
8.如权利要求7所述的结构，其特征在于，该金凸块包含：
一第三侧壁，连接该第一接合面、该第一侧壁以及该第二侧壁，垂直于该第一接合面以及该第一方向，且该共晶材料包覆层覆盖该第三侧壁。
9.一种引脚接合方法，用于一芯片封装结构，其特征在于，该芯片封装结构包含一芯片以及一软性薄膜基板，该方法包含有：
将该芯片的一金凸块的一第一接合面接触该软性薄膜基板的一引脚；
将该金凸块与该引脚加热至一温度范围以于该金凸块与该引脚之间形成一共晶材料包覆层；以及
维持一预定时间，使该共晶材料包覆层覆盖该第一接合面以及该至少一侧壁。
10.如权利要求9所述的方法，其特征在于，该方法还包含：
于该芯片形成该金凸块；以及
于该软性薄膜基板形成该引脚。
11.如权利要求9所述的方法，其特征在于，该引脚及该金凸块沿一第一方向延伸，该金凸块朝一第二方向接触该引脚，该金凸块的宽度及该引脚的宽度分别是该引脚及该金凸块在一第三方向上的尺寸，且该第一方向、第二方向及该第三方向相互垂直。
12.如权利要求11所述的方法，其特征在于，该金凸块的宽度小于或等于该引脚的宽度。
13.如权利要求11所述的方法，其特征在于，该金凸块的宽度大于该引脚的宽度。
14.如权利要求9所述的方法，其特征在于，该引脚包含一第二接合面，该第二接合面朝向该金凸块的第一接合面，该共晶材料包覆层覆盖该第二接合面。
15.如权利要求14所述的方法，其特征在于，该第二接合面与该第一接合面平行于一第一平面，该第二接合面与该第一接合在该第一平面的投影部分交叠或完全交叠，该数个侧壁平行于一第二平面，且该第一平面垂直于该第二平面。
16.如权利要求11所述的方法，其特征在于，该第二接合面与该第一接合面平行于一第一平面，该数个侧壁平行于一第二平面，该第一平面垂直于该第二平面，该数个侧壁包含：
一第一侧壁，连接该第一接合面，垂直于该第一接合面以及该第三方向；以及
一第二侧壁，连接该第一接合面，垂直于该第一接合面以及该第三方向，该共晶材料包覆层覆盖该第一侧壁及该第二侧壁。
17.如权利要求16所述的方法，其特征在于，该金凸块包含：
一第三侧壁，连接该第一接合面、该第一侧壁以及该第二侧壁，垂直于该第一接合面以及该第一方向，且该共晶材料包覆层覆盖该第三侧壁。
18.如权利要求9所述的方法，其特征在于，温度范围是400℃～500℃，该预定时间是0.1～2秒。
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WO2021082898A1 (zh) * 2019-10-29 2021-05-06 颀中科技（苏州）有限公司 Cof封装方法
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CN113345879A (zh) * 2021-05-31 2021-09-03 Tcl华星光电技术有限公司 微型led显示面板
CN113345879B (zh) * 2021-05-31 2022-07-12 Tcl华星光电技术有限公司 微型led显示面板

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