200926390 九、發明說明： 【發明所屬之技術領域】 . 本發明係有關一種封膠技術，尤其是指一種利用特殊 之模板δ又e十，以對具有晶片以及電子元件之基板進行封膠 製程之一種晶片模組之封膠模板及其封膠方法。 【先前技術】 ❹ 現代消費性電子產品已經逐漸走向輕薄短小以 及整合多功能於一身的潮流。為了滿足上述的需求， 電子封裝技術無不精益求精’力求在有限空間内整合 不同功能之電子電路元件或晶片，以圖在市場上佔有 一席之地。因此，封裝技術的輔助是不可或缺的，而 在這類型的封裝技術中，可以分為好幾種，其中較為 人知的為多晶片模組（mu!ti chip module, MCM)封裝 或者是晶片直接封裝（chip on board, COB)等，為了 方便說明封裝後之結構，本發明以”晶片模組，，來作 統稱。前述之晶片模組的封裝技術，主要為在一基板 上整合多元之訊號處理電路，以運用於現代的各種電 子產品，如電腦、手機或數位相機等類之消費性電子 產品。 以C0B晶片模組為例，其關鍵技術在於打線 (wire bonding)以及封膠成形（m〇iding)，主要方法 疋將裸晶片直接黏在電路板或基板上，並結合晶片黏 著導線連接以及應用封膠技術等基本製程，將晶片 6 200926390 製造的封裝與測試步驟轉移到基板組裝階段。請表閱 圖一 A所示，一般而言C0B封裝為將裸露的積體電路 晶片（IC Chip)10封裝於一基板π上，其中晶片 藉由金屬線12,將其I/O經封裝體的線路延伸出來。 在圖一 A中僅一晶片1〇作代表，因為實際上為了整 合多兀性之功能’該基板11上可具有複數個晶片1 〇。200926390 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a sealing technique, in particular to a special template δ and e 10 for sealing a substrate having a wafer and an electronic component. A sealing template for a wafer module and a sealing method thereof. [Prior Art] ❹ Modern consumer electronics products have gradually moved toward a light, short, and versatile trend. In order to meet the above requirements, electronic packaging technology is constantly improving. It strives to integrate electronic circuit components or chips with different functions in a limited space, in order to occupy a place in the market. Therefore, the assistance of packaging technology is indispensable, and in this type of packaging technology, it can be divided into several types, among which the most known is a multi-chip module (MCM) package or a wafer. In order to facilitate the description of the packaged structure, the present invention is generally referred to as a "wafer module". The above-mentioned package technology of the chip module mainly integrates multiple components on a substrate. Signal processing circuits are used in modern electronic products such as computers, mobile phones or digital cameras. For example, in the case of C0B chip modules, the key technologies are wire bonding and gel forming ( M〇iding), the main method is to directly bond the bare wafer to the circuit board or substrate, and combine the wafer bonding wire connection and the basic process of applying the sealing technology to transfer the packaging and testing steps of the wafer 6 200926390 to the substrate assembly stage. As shown in FIG. 1A, in general, the C0B package is to package the exposed IC chip 10 on a substrate π, where the wafer The I/O is extended by the wiring of the package by the metal line 12. In Fig. 1A, only one wafer 1 is represented, because in order to integrate the function of the multiplicity, the substrate 11 may have a plurality of One wafer 1 〇.
接著，如圖一 B所示，在基板n上覆蓋一模板 13,模板13上開設有通孔14以提供容置該晶片1〇。 然後利用印刷（printing)的方式將封膠材料 15(enCaPSUlati〇n material)覆蓋於該晶片 u 之上 方，然後取下模板13以形成如圖一 c的結果。在圖 一 c中，該晶片10上方便覆蓋有一層封膠材15料以 保護該晶片10。接著如圖一 D所示，在該基板I〗上 利用表面黏著（surface m〇unting techn〇l〇灯⑽ 將電子元件16(例如：被動元件）等配置於佈局之位 剛述之過程為典型印刷封膠的製程，不過 下列缺點： | β 〇)由於晶片的成本加上封裝的成本，遠大於藉 由表面黏著技術配置於該基板11上的雷早开曰 此，如果先進行晶片10的貼合程序 郝淼敫*黏著電子元件16之製程失敗而造成 報廢整個模組時，會造成成本的增加。 (2)進行晶片jo接合雲 , 再造仵針^接口而要進仃一次熱處理，然後 再進订黏著電子元件16時又必須再進行一次 7 200926390 熱處理，因此如果按照前述圖一系列之製程， 晶片就額外增加一次不必要的焊爐熱衝擊，造 成晶片損壞之可能性增高。 ❹ (3)如果先貼合晶片的話，由於電路佈局之 故，因此在兩晶片1 〇間有需要佈置電子元件 16時，表面黏著就無法自動化處理。此時需 要藉助人工的方式將電子元件焊接於兩晶片 =率如此一來反而增加生產時間以及間接影響 ⑷在前述之f用技财，如果先將多個晶片10 貼合於基板11上再封膠的話，由於封膠材料 ^固化時的熱收縮;見象會產生應力使得基板 變形’如圖-E之狀態，進而容易造成在 後續進行電子元件之表面黏著製程時產生焊 接不良之問題。Next, as shown in FIG. 1B, a template 13 is covered on the substrate n. The template 13 is provided with a through hole 14 to provide the wafer 1 . A sealant material 15 (enCaPSUlati〇n material) is then overlaid over the wafer u by printing, and then the template 13 is removed to form the result as shown in Fig. 1. In Fig. 1c, the wafer 10 is conveniently covered with a layer of sealing material 15 to protect the wafer 10. Next, as shown in FIG. 1D, the process of arranging the electronic component 16 (for example, a passive component) on the substrate I using the surface adhesion (10), such as a passive component, is generally described. The process of printing the sealant, but the following disadvantages: | β 〇) due to the cost of the wafer plus the cost of the package, much larger than the lightning displacement on the substrate 11 by the surface adhesion technology, if the wafer 10 is first The fitting procedure Hao Hao* fails to process the entire module when the process of adhering to the electronic component 16 fails, which causes an increase in cost. (2) If the wafer is bonded to the cloud, the 仵 pin ^ interface is to be subjected to a heat treatment, and then the bonding of the electronic component 16 must be performed again. 7 200926390 heat treatment, so if the process according to the above series of processes, the wafer An additional increase in the thermal impact of the furnace is added, which increases the likelihood of wafer damage. ❹ (3) If the wafer is first bonded, due to the circuit layout, when there is a need to arrange the electronic component 16 between the two wafers, the surface adhesion cannot be automated. In this case, it is necessary to manually solder the electronic components to the two wafers. The rate is increased to increase the production time and indirect effects. (4) In the foregoing, if the plurality of wafers 10 are first bonded to the substrate 11, the capacitors are first sealed. In the case of glue, heat shrinkage occurs when the sealant material is cured; the appearance of stress causes the substrate to deform as shown in the state of FIG.-E, which may easily cause a problem of poor soldering in the subsequent surface adhesion process of the electronic component.
【發明内容】 本發明提供一種晶片模組之封膠模板，其係設計一種 ==:子元件以及晶片的模板，使得對二: 著製程之後進行’使得晶片模組 之怖局叹计更有彈性，增加生產可靠度。 本發明提供-種晶片模組之封膠方法，其係可先於基 200926390 ，上黏著電子元件再進行晶片㈣，藉 件以強化基板之強度減少晶Μ裝子元 . 本發明提供—種晶片模組之_方法^問通。 *板上黏著電子元件再進行晶片封裝其ς係可先於基 好電子元件，因此不但可以減先黏著 產良率與品質。 廢原物枓之成本，進而提昇生 ❹板，t係:=:面η: -種晶片模組之封膠模 ，面以及底面之至少-通孔以===: 形成有至少-溝槽，以提供容置該 法，其係包括有·^步晶二模組=膠方 ==子元件電性連接於該基板:;將 ❿土广連接；提供一封谬模板，其係具有一頂面以及 :=以有貫通該頂面以及底面之至少 有至少-溝槽，供面= 晶 片-封膠程序將膠材填入該至少-通孔内以封:該至τ 【實施方式】 能對本發明之特徵、目的及功能有 ，下文特將本發明之裝置的相關細 為使貴審查委員 更進一步的認知與瞭解 9 200926390 部結構以及設計的理念原由進行說明，以使得審查委員可 以了解本發明之特點，詳細說明陳述如下·· ΟSUMMARY OF THE INVENTION The present invention provides a sealing template for a wafer module, which is designed to design a ==: sub-element and a template of the wafer, so that the second: after the process is performed, the chip module is more stunned. Flexibility to increase production reliability. The invention provides a method for sealing a wafer module, which can be carried on the substrate 200926390, and then the electronic component is bonded to the wafer (4), and the substrate is used to reduce the strength of the substrate to reduce the wafer carrier. The invention provides a wafer. Module _ method ^ ask. *Adhesive electronic components on the board and chip packaging can be used before the electronic components, so not only can the adhesion yield and quality be reduced. The cost of the waste material, and then the growth of the green board, t series: =: surface η: - the sealing mold of the wafer module, at least the surface and the bottom surface - the through hole is formed with at least - groove Providing the method for accommodating the method, comprising: stepping the second module = glue square == the sub-element is electrically connected to the substrate: connecting the bauxite; providing a 谬 template having a The top surface and: = at least at least a groove through the top surface and the bottom surface, the surface = wafer-sealing process fills the at least the through hole to seal: the to τ [embodiment] The features, objects, and functions of the present invention are as follows. The following is a detailed description of the apparatus of the present invention, so that the reviewer can further understand and understand the rationale and structure of the 200926390 structure, so that the review committee can understand The features of the present invention are described in detail below.
請參閱圖二所示，該圖係為C0B基材示意圖。該c〇B 基材2上具有複數個C0B晶片模組2〇，每一個模組2〇上 具有至少一個晶片201以及複數個電子元件2〇2。該至少 了晶片2〇1係與基板203作電性接合，在本實施例中該c〇B 模組20上之晶片201雖以圖示顯示三個，但是實際上之數 量可根據設計而定’並不以圖示之數量為限。該複數個電 ，兀件202係佈設於該基板2〇3上，在本實施例中該複 數個電子元件2G2係為被動元件，例如：電阻、電容或者 是電感等。該COB晶片模組20係為習用之結構在此不作贅 如圖一A所示’该圖係為本發明之晶片模組之封膠模 2體示意圖。在本實施例中’該封膠模板3係與圖二之 小對應’該封膠模板3上具有一頂面3〇以及一底 ，該封賴板3上具有複數個模板區塊32，每一個模 H應著圖二中的⑽晶片模組2〇。另外該封膠 可所使用之材料也是根據需求而定，材料選擇 是非金屬材料，在本實施例中之封膠模板3 通每—個模板區塊32可以具有至少一個 該通Γ 賴頂面3G以及底面31，在本實施例中， 不以本： ’但其數量係為根據需要而定，並 不以本實％例之圖示為限。 姓構所示，該圖係為本發明之封膠模板底面 4立體不思圖。該封膠模板3之底面31上之每個模板區 200926390 塊32更具有複數個溝槽321與322，其設計與配置是根據 需求而定，在本發明之實施例中，凹槽321係沿著該通孔 , 320之外圍设置，使得每一個通孔320與該凹槽321間以 . 一凸部結構323作區隔。另外，在該模板區塊犯之其他位 置上也開設有凹槽322。由於圖三A與圖三β中之模板區 塊323係與圖二中之C0B晶片模組相對應，為了方便說明， 請參閱圖四所示，該圖係為其中之一模組區塊與其對應之 COB晶片模組剖面示意圖。每一個通孔32〇可提供容置晶 ❹ 片201，而底面上之凹槽321，則可以提供容置設置於該基 板203上之電子元件202。由於該通孔320係可容置晶片 201’而該凹槽321係可容置電子元件202,因此該通孔32〇 與该凹槽321之位置分佈是根據基板203上的電路佈局而 定’因此並不以本發明之實施例為限。 請參閱圖五所示，該圖係為本發明之晶片模組之封膠 方法流程示意圖。在本實施例中，該封膠方法其係包括有 下列步驟.首先進行步驟4〇 ’提供一基板，其係具有複數 •❹個C〇B晶片模組之佈局，該基板内係具有電路結構之佈 局，以與晶片與電子元件作電性連接，在本實施例中該 基板係為一印刷電路板（printed circuit board, PCB)。 如圖六A所示，為了方便說明，僅以代表一 c〇B模組2〇之 基板203作說明。接著進行步驟41，以一接著程序，將複 數個電子元件202接著於該基板203上之對應位置。該複 數個電子元件202係可為被動元件，如：電阻、電感或者 是電容等’但不以此為限。該接著程序係可選擇為手焊或 者是自動焊接的方式來達成。在本實施例中，該接著程序 11 200926390 係利用表面黏著技術（surface mounting technology，SMT) 將複數個電子元件202接著於該基板203上，其結果如圖 六B所示。至於表面黏著技術係屬於習用技術，在此不作 贅述。Please refer to FIG. 2, which is a schematic diagram of a C0B substrate. The c〇B substrate 2 has a plurality of C0B wafer modules 2, each of which has at least one wafer 201 and a plurality of electronic components 2〇2. At least the wafer 2〇1 is electrically connected to the substrate 203. In the embodiment, the wafer 201 on the c〇B module 20 is shown as three in the figure, but the actual number can be determined according to the design. 'Not limited to the number shown. The plurality of electrical components 202 are disposed on the substrate 2〇3. In the embodiment, the plurality of electronic components 2G2 are passive components, such as resistors, capacitors or inductors. The structure of the COB chip module 20 is conventional and will not be used here. As shown in Fig. 1A, the figure is a schematic view of the sealing mold of the wafer module of the present invention. In the present embodiment, the sealant template 3 corresponds to the small one of FIG. 2, and the sealant template 3 has a top surface 3〇 and a bottom. The sealing plate 3 has a plurality of template blocks 32, each of which has a plurality of template blocks 32. A mold H should be the (10) wafer module 2〇 in Figure 2. In addition, the material to be used for the sealant is also determined according to requirements, and the material selection is a non-metal material. In the embodiment, the seal template 3 can have at least one of the top surface 3G of each of the template blocks 32. And the bottom surface 31, in the present embodiment, does not mean: 'But the number is determined as needed, and is not limited to the illustration of the actual example. As shown by the surname structure, the figure is the bottom surface of the seal template of the present invention. Each of the template regions 200926390 32 on the bottom surface 31 of the sealant template 3 further has a plurality of grooves 321 and 322, which are designed and arranged according to requirements. In the embodiment of the present invention, the grooves 321 are along the edge. The through holes, 320 are disposed at the periphery, such that each of the through holes 320 and the groove 321 are separated by a convex portion structure 323. In addition, a recess 322 is also provided at other locations in the template block. Since the template block 323 in FIG. 3A and FIG. 3 corresponds to the C0B chip module in FIG. 2, for convenience of explanation, please refer to FIG. 4, which is one of the module blocks and Corresponding schematic diagram of the COB chip module. Each of the through holes 32A can provide the accommodating wafer 201, and the recess 321 on the bottom surface can provide the electronic component 202 disposed on the substrate 203. Since the through hole 320 can accommodate the chip 201 ′ and the groove 321 can accommodate the electronic component 202 , the position distribution of the through hole 32 〇 and the groove 321 is determined according to the circuit layout on the substrate 203 . Therefore, it is not limited to the embodiment of the invention. Referring to FIG. 5, the figure is a schematic flow chart of the sealing method of the wafer module of the present invention. In this embodiment, the encapsulation method includes the following steps. First, step 4 is performed to provide a substrate having a plurality of layouts of C C chip modules having a circuit structure. The layout is electrically connected to the chip and the electronic component. In the embodiment, the substrate is a printed circuit board (PCB). As shown in Fig. 6A, for convenience of explanation, only the substrate 203 representing a c〇B module 2A will be described. Next, in step 41, a plurality of electronic components 202 are followed by corresponding positions on the substrate 203 in a subsequent process. The plurality of electronic components 202 can be passive components such as resistors, inductors, or capacitors, etc., but are not limited thereto. This follow-up procedure can be achieved by either hand soldering or automatic soldering. In the present embodiment, the follow-up procedure 11 200926390 uses a surface mounting technology (SMT) to mount a plurality of electronic components 202 on the substrate 203. The result is shown in Fig. 6B. As for the surface adhesion technology, it is a conventional technique and will not be described here.
步驟41之後，接著進行步驟42,將至少一晶片2〇1與 該基板203作電性連接。如圖六c所示，在步驟42主要是 先將晶片201接著於該基板203上之特定位置，然後再進 行打線（wire bonding) ’以使該晶片201上之接腳與基板 203上之電性板作連接。至於如何接著晶片以及打線之技 術係為習用之技術，在此不作贅述。接下來進行步驟4 3 , k供封膝模板3罩覆於該基板203上，該封膠模板3之 特徵係如同前述圖三A與圖三B所示。如圖所示，為 了方便說明’圖六D中僅顯示著單—之模組區塊32，但實 際上該封膠模板是由複數個模板區塊32以陣列的形式排 列’以利進行大量生產。在步驟43中，當該封膠模板上罩 覆於基板203上時，C0B晶片模組2〇上之晶片2〇1則容置 =㈣H32G内’⑽晶片模組2()上之電子元件2〇2 則容置於對應之凹槽321内。 再回到圖五所示，隨後進行步驟 ^ l, ,* 利用一封膠程序 將膠材填入該至少一通孔内以封膠兮 :r所示，在本實施例中，該封r:序r為 的私序’其主要在該封膠模板 nn, 上供一封膠材料 90(encapsulation)，然後利用刮刀 Q1、办> 將該封膠材料填入至該通孔320内，3位移運動’ 曰μ ΟΛ1 从將該通孔320内之 晶片201封住。由於該通孔320與今如祕 亥凹槽32l之間具有凸 200926390 部結構323,在刮刀91施壓於該封膠模板之頂面3〇上時， 該凸部結構323可抵靠於該基板2〇3上，因此充填的封膠 材料90於通孔320的過程中，該封膠材料9〇不會流入凹 槽内321損害電子元件202，並碟保通孔内之晶片2〇1可 以完全被封住。最後，再將該封膠模板取出，以形成如 六F之結構。After step 41, step 42 is followed to electrically connect at least one wafer 2〇1 to the substrate 203. As shown in FIG. 6c, in step 42, the wafer 201 is first placed on a specific position on the substrate 203, and then wire bonding is performed to make the pins on the wafer 201 and the substrate 203 electrically. Sex board for connection. As for the technique of how to follow the wafer and the technology of the wire, it will not be described here. Next, step 4 3 is performed, and the knee-sealing template 3 is covered on the substrate 203. The sealing template 3 has the characteristics as shown in the foregoing FIG. 3A and FIG. 3B. As shown in the figure, for convenience of description, only the module block 32 of the single-block is shown in FIG. 6D, but actually the sealant template is arranged in an array by a plurality of template blocks 32 to facilitate a large number of produce. In step 43, when the encapsulation template is overlaid on the substrate 203, the wafer 2〇1 on the C0B wafer module 2 is accommodated in the (4) H32G electronic component 2 on the (10) wafer module 2 () 〇2 is placed in the corresponding groove 321 . Returning to FIG. 5, the following steps are performed, and the glue is filled into the at least one through hole by a glue program to show the sealant: r, in the embodiment, the seal r: The private sequence of the sequence r is mainly for providing a glue material 90 on the seal template nn, and then filling the sealant into the through hole 320 by using a doctor blade Q1, 3 The displacement motion '曰μ ΟΛ1 is sealed from the wafer 201 in the via 320. Since the through hole 320 has a convex 200926390 structure 323 between the current and the shovel 32l, the convex structure 323 can abut when the blade 91 is pressed against the top surface 3 of the sealing template. On the substrate 2〇3, during the process of filling the sealing material 90 in the through hole 320, the sealing material 9〇 does not flow into the groove 321 to damage the electronic component 202, and the wafer in the through hole is protected by the chip 2〇1. Can be completely sealed. Finally, the sealant template is removed to form a structure such as a six F.
Ο 圖七Α與圖七Β所示’該圖係為本發明之晶片模植 之，膠，版另—實施例示意圖。在本實施例中，轉模板 ，是針對具有高度比封膠模板3厚度還大的電子元件 4 =的設計方式。該封膠模板上3之每—模板區塊犯更 3 ^一個t罩33，其内之容置空間開口係位於該 個才-—·以提供容置電子元件2G4。本實施例中之每-上中之中空凸罩33雖然顯示—個’但是實際 實ί:!與圖七Β之實施例為限。至於在圖七Α之 也可以將過大之電子元物在佈局設計 避開封膠刮刀91行進的路線。 羽田在境裡需強調的是，雖然、步驟41與步驟42 #八幻我 之技術，但是本發明之方盥 _ r'n 透過本發明之Λ '、技術不同的是在於 基板上，因此增 =二於步驟41是先歸電子元件於 膠程序，造成i把:強度’減低了因為步驟44之封 :將電子元件黏著於基板上，再進面黏 破封裝之晶片可以減少額外的回烊爐所產生的熱衝 13 200926390 擊’ Jt而滅少晶片損壞的機率。此外 灯黏，電子元件再進行貼合程序，因此试，發明是先壤 者Γ子元件失敗報廢整個基板所造成的：習用技術固 “電：發明之封裝模板具有凹槽之設計，ίί:費。再 不會:響勒著電子元件之製程=電路伟局的多元性， 制本述ii僅為本發明之實施例，當不能以切 月之，砷和範圍，故都應視為本發明的進一步實二^發 综合h+、丄々 員他狀/兄。 ❹ 膠方法，^ α，本發明提供之晶片模組之封膠模板及其甸· 產之球疮可以使得晶片模組之佈局設計更有彈性以提昇蝥 率與。及減少晶片封膠時的生產成本進而提昇生產Ρ 競二口質。因此可以滿足業界之需求，進而提高該產業二 及帶動週遭產業之發展，誠已符合發明專利法 申^，清^明所需具備之要件，故爰依法呈提發明專利之 為二i謹請貴審查委員允撥時間惠予審視，並賜准專利 14 200926390 【圖式簡單說明】 圖一 A至圖一 D係為習用之晶片模組封裝流程示意圖。 ' 圖一 E係為習用之封裝晶片模組基板變形示意圖。 • 圖二係為C0B基材示意圖。 圖三A係為本發明之晶片模組之封膠模板立體示意圖。 圖三B係為本發明之封膠模板底面結構立體示意圖。 圖四係為其中之一模組區塊與其對應之C0B晶片模組剖面 & 不意圖。 圖五係為本發明之晶片模組之封膠方法流程示意圖。 圖六A至圖六F係為本發明之晶片模組之封膠方法流程中 各階段之結構剖面示意圖。 圖七A與圖七B係為本發明之晶片模組之封膠模版另一實 施例示意圖。 【主要元件符號說明】 β 10-晶片 . 11-基板 12- 金屬線 13- 模板 14- 通孔 15- 封膠材料 16- 電子元件 2-C0B基材 15 200926390 20-COB晶片模組 201- 晶片 202- 電子元件 2 0 3 -基板 204-電子元件 3 _封膠模板 30-頂面 31 -底面 32- 模板區塊 320-通孔 321、322-溝槽 3 2 3 -凸部結構 33- 中空凸罩 4-晶片模組之封膠方法 40〜44-步驟 90_封膠材料 91-刮刀 910-開口 16Ο Figure 7Α and Figure 7Β' is a schematic view of the wafer molding of the present invention, the glue, and the other embodiment. In the present embodiment, the transfer template is designed for an electronic component 4 = having a height greater than the thickness of the sealant template 3. Each of the stencil templates on the stencil template 3 is made up of a ^ hood 33, and the accommodating space opening therein is located at the slab to provide the accommodating electronic component 2G4. The hollow convex cover 33 in each of the above embodiments is limited to the embodiment shown in the figure. As for the figure 7 也, it is also possible to avoid the route of the large size of the electronic element in the layout design avoiding the sealing blade 91. In the context of Haneda, it should be emphasized that, although, step 41 and step 42 #八幻我的技术, the method of the present invention 盥 r r 'n through the invention 、 ', the technology is different on the substrate, thus increasing = Second, in step 41, the electronic component is first applied to the glue program, resulting in i: the strength is reduced because the seal of step 44: the electronic component is adhered to the substrate, and then the surface is stuck to the packaged wafer to reduce the additional feedback. The heat generated by the furnace 13 200926390 hits 'Jt and destroys the probability of wafer damage. In addition, the lamp is glued, and the electronic components are then subjected to the bonding process. Therefore, the invention is caused by the failure of the first scorpion component to scrap the entire substrate: the conventional technology is solid: the invention package template has a groove design, ίί: fee No longer: the process of electronic components = the diversity of the circuit, the system ii is only an embodiment of the present invention, when it can not be cut into the moon, arsenic and range, it should be regarded as the present invention Further real two-integrated h+, 丄々人他/兄. ❹ Glue method, ^ α, the sealing template of the wafer module provided by the invention and the ball sore produced by the dian can make the layout design of the chip module It is more flexible to increase the defect rate and reduce the production cost of wafer encapsulation and thus improve the production quality. Therefore, it can meet the needs of the industry, thereby improving the industry and driving the development of the surrounding industries. The patent law applies for the purpose of clearing the requirements, so it is necessary to provide the invention patent according to law. Please ask the review committee to allow the time to review and grant the patent 14 200926390 [Simple diagram] One A Figure 1D is a schematic diagram of a conventional wafer module packaging process. 'Figure 1E is a schematic diagram of a conventional packaged package module substrate. 2. Figure 2 is a schematic diagram of a C0B substrate. Figure 3A is a wafer mold of the present invention. Figure 3B is a perspective view showing the structure of the bottom surface of the sealing template of the present invention. Figure 4 is a schematic view of one of the module blocks and its corresponding C0B chip module & The flow chart of the sealing method of the wafer module of the present invention is shown in Fig. 6A to Fig. 6F. Fig. 7A and Fig. 7B are schematic diagrams showing the structure of each stage of the sealing method of the wafer module of the present invention. It is a schematic diagram of another embodiment of the sealing stencil of the wafer module of the present invention. [Main component symbol description] β 10-wafer. 11-substrate 12-metal wire 13-template 14-through hole 15-sealing material 16- Electronic component 2-C0B substrate 15 200926390 20-COB wafer module 201 - wafer 202 - electronic component 2 0 3 - substrate 204 - electronic component 3 - sealing template 30 - top surface 31 - bottom surface 32 - template block 320 - Through hole 321, 322-groove 3 2 3 - convex structure 33- Hollow convex cover 4-chip module sealing method 40~44-step 90_sealing material 91-scraper 910-opening 16