CN111627865B - Semiconductor packaging structure and manufacturing method thereof - Google Patents

Semiconductor packaging structure and manufacturing method thereof Download PDF

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Publication number
CN111627865B
CN111627865B CN201910143924.XA CN201910143924A CN111627865B CN 111627865 B CN111627865 B CN 111627865B CN 201910143924 A CN201910143924 A CN 201910143924A CN 111627865 B CN111627865 B CN 111627865B
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power chip
layer
electrode layout
patterned conductive
conductive layer
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CN111627865A (en
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许哲玮
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Phoenix Pioneer Technology Co Ltd
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Phoenix Pioneer Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Abstract

The invention discloses a semiconductor packaging structure, which comprises a first patterned conducting layer, a first power chip, a second power chip, a conducting adhesive layer, a second patterned conducting layer, a first conducting connecting element, a second conducting connecting element and a molding layer. The first power chip and the second power chip are embedded in the molding layer in a manner that the front surface and the back surface are reversed. In addition, one side of the first power chip and one side of the second power chip are fixed on the first patterned conductive layer through the conductive adhesive layer. The invention also discloses a manufacturing method of the semiconductor packaging structure.

Description

Semiconductor packaging structure and manufacturing method thereof
Technical Field
The present invention relates to a package structure and a method for fabricating the same, and more particularly, to a semiconductor package structure and a method for fabricating the same.
Background
With the increasing demand of credit and automotive electronics, Quad Flat No-Lead (QFN) package structures have become important semiconductor package technologies due to their better heat dissipation, lower impedance and electromagnetic interference.
In QFN packages, copper clip (copper clip) is a technology that is required for high power. The copper sheet is designed into an arch bridge shape with high and low drop height, and is jointed with the wafer by using a solder paste (solder paste) process, so that the copper sheet has smaller resistance to bear large current and can bear deformation caused by thermal stress, and the copper sheet is suitable for high-power elements such as transistors.
Referring to fig. 1A to 1D, a portion of a conventional package structure using a copper bridging technique for connecting transistors is briefly described.
As shown in fig. 1A, a solder paste layer 102 is formed on a lead frame (lead frame) 101 by performing a screen printing process. Next, as shown in FIG. 1B, a transistor chip 103 is placed on the solder paste layer 102. Then, as shown in fig. 1C, solder 104 is formed on the transistor chip 103. Finally, as shown in fig. 1D, a bridge copper 105 is placed on the corresponding solder paste layer 102 and solder 104, and the lead frame 101, the transistor chip 103 and the bridge copper 105 are bonded to each other after a high temperature reflow process at 380 ℃.
The above process and the finished product have at least the following problems:
(1) the package structure uses the lead frame and the bridging copper sheet, so the height (thickness) of the package cannot be reduced, and the application field of the package is limited.
(2) Solder or solder paste contains a relatively high proportion of lead, and lead metal causes environmental pollution and has a considerable impact on human health.
(3) Individual component displacement may occur before the high temperature reflow process at 380 degrees celsius fixes all components, resulting in a decrease in accuracy.
Therefore, it is an important issue to provide a semiconductor package structure capable of integrating high power devices and a method for manufacturing the same.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which can reduce the height of the semiconductor package containing high power devices and increase the electrical performance. Another objective of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which can meet the requirement of environmental protection regulations without using a lead-containing process.
To achieve the above objective, the present invention provides a semiconductor package structure, which includes a first patterned conductive layer, a first power chip, a second power chip, a conductive adhesive layer, a second patterned conductive layer, a first conductive connecting element, a second conductive connecting element, and a molding layer.
The first power chip has a first front surface and a first back surface, and the first front surface is disposed toward the first patterned conductive layer. The first front surface of the first power chip has a first electrode layout, and the first back surface has a second electrode layout. The second power chip is adjacent to the first power chip, has a second front surface and a second back surface, and is disposed with the second back surface facing the first patterned conductive layer. The second front surface of the second power chip has a third electrode layout, and the second back surface has a fourth electrode layout. The conductive adhesive layer is electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer. In addition, the conductive adhesive layer is also electrically connected between the fourth electrode layout of the second power chip and the first patterned conductive layer. The second patterned conductive layer is arranged opposite to the first patterned conductive layer, and the first back surface of the first power chip and the second front surface of the second power chip are arranged towards the second patterned conductive layer. The first conductive connecting element is electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and is electrically connected between the third electrode layout of the second power chip and the second patterned conductive layer. The second conductive connecting element is electrically connected between the first patterned conductive layer and the second patterned conductive layer and electrically connected with the first patterned conductive layer and the second patterned conductive layer. The mold sealing layer covers the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connecting element and the second conductive connecting element.
According to an embodiment of the present invention, the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip.
According to an embodiment of the present invention, the first power chip and the second power chip are a transistor chip respectively.
According to an embodiment of the present invention, the first electrode layout and the third electrode layout respectively include a gate and a source, and the second electrode layout and the fourth electrode layout respectively include a drain.
According to an embodiment of the present invention, the drain of the second electrode layout is electrically connected to the source of the third electrode layout.
According to an embodiment of the present invention, the material of the molding layer is a molding compound, which uses phenolic-based resin, epoxy-based resin or silicon-based resin as a main matrix.
In addition, to achieve the above object, the present invention provides a method for manufacturing a semiconductor package structure, comprising the steps of: the method comprises the following steps: providing a bearing plate; step two: forming a first patterned conductive layer on a surface of the carrier plate; step three: arranging a conductive adhesive layer on part of the first patterned conductive layer; step four: arranging a first power wafer on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power wafer is contacted with the conductive adhesive layer; step five: disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout of a second back surface of the second power chip contacts the conductive adhesive layer; step six: forming at least one conductive connecting element on the first patterned conductive layer without the conductive adhesive layer, a second electrode layout on a first back surface of the first power chip and/or a third electrode layout on a second front surface of the second power chip; step seven: forming a mold sealing layer on the carrier plate and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the conductive connecting element; step eight: forming a second patterned conductive layer on the molding layer and electrically connected to the conductive connecting element exposed to the molding layer; step nine: and removing the bearing plate.
According to an embodiment of the present invention, at least one drain of the first back surface of the first power chip is electrically connected to at least one source of the second front surface of the second power chip.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor package structure, comprising the steps of: the method comprises the following steps: providing a bearing plate; step two: forming a first patterned conductive layer on a surface of the carrier plate; step three: arranging a conductive adhesive layer on part of the first patterned conductive layer; step four: arranging a first power wafer on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power wafer is contacted with the conductive adhesive layer; step five: disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout of a second back surface of the second power chip contacts the conductive adhesive layer; step six: forming at least one second conductive connecting element on the first patterned conductive layer without the conductive adhesive layer; step seven: forming a mold sealing layer on the carrier plate and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the second conductive connecting element; step eight: forming a plurality of openings on the molding layer corresponding to a second electrode layout of a first back surface of the first power chip and a third electrode layout of a second front surface of the second power chip; step nine: forming a first conductive connecting element on the openings; step ten: forming a second patterned conductive layer on the molding layer and electrically connected to the first conductive connecting element and the second conductive connecting element exposed to the molding layer; and step eleven: and removing the bearing plate.
According to an embodiment of the present invention, the first conductive connecting element and the second patterned conductive layer are formed simultaneously in one process.
In view of the above, the first power chip and the second power chip, such as transistor chips, are disposed in an inverted manner, so as to shorten the distance between the electrical connections between the chips and increase the electrical performance. On the other hand, the semiconductor process is used for replacing the existing lead-containing and high-temperature reflow soldering process, so that the precision of the packaging structure can be greatly improved, and the lead-free environment-friendly process trend requirement can be met.
Drawings
Fig. 1A to 1D are schematic diagrams illustrating a method for manufacturing a junction transistor by using a copper bridging technique in a package structure of the prior art.
Fig. 2A to 2I are schematic diagrams illustrating a method for manufacturing a semiconductor package structure according to a first embodiment of the invention.
Fig. 3A to 3D are schematic views illustrating a method for manufacturing a portion of a semiconductor package structure according to a second embodiment of the invention.
Fig. 4 is a schematic view of the semiconductor package structure disposed on a circuit board according to the preferred embodiment of the invention.
Fig. 5 is a schematic view of a circuit board on which a semiconductor package structure carrying electronic components according to a preferred embodiment of the invention is mounted.
Description of the reference numerals
101. A lead frame; 102. a solder paste layer; 103. a transistor chip; 104. soldering tin;
105. bridging the copper sheets; 20. a semiconductor package structure; 21. a carrier plate;
211. a surface; 22. a first patterned conductive layer; 23. a conductive adhesive layer;
24. a first power chip; 241. a first front surface; 242. a first back surface;
25. a second power chip; 251. a second front surface; 252. a second back surface;
261. a first conductive connecting element; 262. a second conductive connecting element;
27. molding and sealing the layer; 27a, a protective layer;
271. 272, 273, 274, 275: an opening;
28. a second patterned conductive layer; 30. a circuit board; 33. an electronic component;
32. 34: a conductive bump;
d1, D2: a drain electrode;
g1, G2: a gate electrode;
s1, S2: a source electrode;
t01, T02: a top end.
Detailed Description
This summary is explained below by way of examples, which are not intended to limit the invention to any particular environment, application, or particular manner in which the invention may be practiced as described in the examples. Therefore, the description of the embodiments is for the purpose of illustration only, and not for the purpose of limitation. It should be noted that, in the following embodiments and the accompanying drawings, elements not directly related to the present invention have been omitted and not shown; and the dimensional relationships between the various elements in the drawings are merely for ease of understanding and are not intended to be limiting in nature. In the following embodiments, the same elements will be described with the same reference numerals.
Fig. 2A to fig. 2I are schematic diagrams illustrating a method for manufacturing a semiconductor package structure according to a first embodiment of the invention. The method of manufacturing the semiconductor package structure includes steps S11 to S20.
As shown in fig. 2A, in step S11, a first patterned conductive layer 22 is formed on a surface 211 of a carrier 21. The carrier plate 21 may be a metal plate or an insulating plate. The material of the first patterned conductive layer 22 is a conductive metal, such as copper, silver, nickel or an alloy thereof, and the first patterned conductive layer 22 is formed by performing an exposure development and an etching process with an additional photoresist layer (not shown) and an electroplating process by using a photolithography and etching technique.
It should be particularly noted that in the conventional wafer type (wafer type) process, the packaging process can be performed only on the chips (chips) or the dies (die) formed in a single wafer at the same time, which is time-consuming and has many limitations in process. Compared with the traditional wafer type packaging process, the invention adopts a large-size board type (panel level type) packaging process. Wherein, the area of the carrier plate 21 is multiple times of the area of a single wafer. Accordingly, the carrier 21 of the present invention can simultaneously perform a packaging process for all chips (or dies) cut from a plurality of wafers, thereby effectively saving the manufacturing time.
Next, as shown in fig. 2B, step S12 is to dispose a conductive adhesive layer 23 on a portion of the first patterned conductive layer 22. The conductive adhesive layer 23 may be a conductive adhesive, and the material thereof may include a high heat dissipation conductive material, such as silver or copper. In other embodiments, the conductive adhesive layer 23 may also be an anisotropic conductive adhesive to provide vertical (Z-axis) conduction.
Next, as shown in fig. 2C, step S13 is to dispose a first power chip 24 on the conductive adhesive layer 23. The first power chip 24 has a first front surface 241 and a first back surface 242. The first front surface 241 has a first electrode layout and the first back surface 242 has a second electrode layout. The first electrode layout of the first front surface 241 is in contact with the conductive adhesive layer 23.
Next, in step S14, a second power chip 25 is disposed on the conductive adhesive layer 23. The second power chip 25 has a second front surface 251 and a second back surface 252. The second front side 251 has a third electrode layout, and the second back side 252 has a fourth electrode layout. The fourth electrode layout of the second back surface 252 is in contact with the conductive adhesive layer 23.
In the present embodiment, the first power chip 24 and the second power chip 25 are respectively a Transistor chip, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) chip. Therefore, the first electrode layout and the third electrode layout respectively include a Gate (Gate) G1, G2 and a Source (Source) S1, S2. On the other hand, the second electrode layout and the fourth electrode layout respectively include a Drain (Drain) D1 and D2. In other embodiments, the Transistor chip can be a Bipolar Junction Transistor (BJT) chip or an Insulated Gate Bipolar Transistor (IGBT) chip.
Based on the above, the first power chip 24 and the second power chip 25 have the same elements, so the first electrode layout of the first power chip 24 is the same as the third electrode layout of the second power chip 25, and the second electrode layout of the first power chip 24 is the same as the fourth electrode layout of the second power chip 25. In other words, the first power chip 24 and the second power chip 25 are disposed on the conductive adhesive layer 23 in an inverted manner.
Next, as shown in fig. 2D, in step S15, a first conductive connecting element 261 is formed on the second electrode layout of the first back surface 242 of the first power chip 24 and the third electrode layout of the second front surface 251 of the second power chip 25. The first conductive connecting elements 261 can be formed by performing an exposure, development and etching process with an additional photoresist layer (not shown) and performing an electroplating process by using a photolithography and etching technique.
Next, as shown in fig. 2E, step S16 is to form a second conductive connecting element 262 on the first patterned conductive layer 22 without the conductive adhesive layer 23. The second conductive connecting elements 262, such as conductive pillars, are made of metal and can be directly formed on the first patterned conductive layer 22 through an electroplating process, which not only provides an electrical conduction path, but also increases the supporting strength. In other embodiments, the second conductive connecting element 262 may be pre-formed and fixed and electrically connected to the first patterned conductive layer 22 (not shown) by a conductive adhesive.
Next, as shown in fig. 2F, in step S17, a molding layer 27 is formed on the carrier 21 and covers the first patterned conductive layer 22, the conductive adhesive layer 23, the first power chip 24, the second power chip 25, the first conductive connecting element 261 and the second conductive connecting element 262. The molding compound 27 may be a high filler content dielectric material (molding compound), such as a phenolic-Based Resin (Novolac-Based Resin), an Epoxy-Based Resin (Epoxy-Based Resin) or a silicon-Based Resin (silicon-Based Resin) as a main matrix, and is formed by doping a filler in a proportion of about 8 wt.% to about 12 wt.% Based on the entire molding compound and in a proportion of about 70 wt.% to about 90 wt.% Based on the entire molding compound. Wherein, the filler can comprise silicon dioxide and aluminum oxide, so as to achieve the effects of increasing mechanical strength, reducing linear thermal expansion number, increasing heat conduction, increasing water resistance and reducing glue overflow.
In this embodiment, the step S17 further includes grinding the top of the molding layer 27 by a grinding process to expose the top ends T01, T02 of the first conductive connecting element 261 and the second conductive connecting element 262.
Next, as shown in fig. 2G, step S18 forms a second patterned conductive layer 28 on the molding layer 27 and electrically connected to the first conductive connecting element 261 and the second conductive connecting element 262 exposed to the molding layer 27.
Next, as shown in fig. 2H, in step S19, a protection layer (cover layer) 27a is formed on the molding layer 27 and covers the second patterned conductive layer 28, so as to protect the devices embedded in the molding layer 27 and the protection layer 27 a. In this embodiment, a polishing process may also be selectively performed to polish the top of the passivation layer 27 a.
Finally, as shown in fig. 2I, the carrier 21 is removed in step S20, thereby forming a semiconductor package structure 20. In the present embodiment, the first power chip 24 and the second power chip 25 are disposed upside down, and the drain D1 of the first power chip 24 is electrically connected to the source S2 of the second power chip 25 through the first conductive connecting element 261 and the second patterned conductive layer 28. Accordingly, the electrical conduction distance between the drain D1 and the source S2 can be shortened, thereby increasing the electrical performance, and on the other hand, the semiconductor package structure can be applied to a half-bridge circuit.
The following describes a method for manufacturing a semiconductor package according to a second embodiment of the present invention. In the present embodiment, the method for manufacturing the semiconductor package structure includes steps S31 to S40. Since the manufacturing method of this embodiment has some steps shown to be the same as those of the manufacturing method of the first embodiment, the description of the same steps will be omitted. In addition, in the present embodiment, the same elements as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment.
First, steps S31 to S34 are the same as steps S11 to S14 of the first embodiment, and thus are not described herein again.
Next, as shown in fig. 3A, step S35 forms a second conductive connecting element 262 on the first patterned conductive layer 22 without the conductive adhesive layer 23. As in the previous embodiments, the second conductive connecting elements 262, such as conductive pillars, are made of metal and can be directly formed on the first patterned conductive layer 22 through an electroplating process, which not only provides an electrical conduction path, but also increases the supporting strength. In other embodiments, the second conductive connecting element 262 may be pre-formed and fixed and electrically connected to the first patterned conductive layer 22 (not shown) by a conductive adhesive.
Next, as shown in fig. 3B, in step S36, a molding layer 27 is formed on the carrier 21 and covers the first patterned conductive layer 22, the conductive adhesive layer 23, the first power chip 24, the second power chip 25 and the second conductive connecting element 262. In addition, the step S36 may further include grinding the top of the molding layer 27 through a grinding process to expose the top end T02 of the second conductive connecting element 262.
Next, as shown in fig. 3C, in step S37, three openings 271, 272 and 273 are formed in the molding layer 27 by laser drilling (laser drilling) technology at positions corresponding to the drain D1 of the first power chip 24 and the source S2 and the gate G2 of the second power chip 25, respectively, so as to expose the drain D1 of the first power chip 24 and the source S2 and the gate G2 of the second power chip 25.
Next, as shown in fig. 3D, step S38 forms a first conductive connecting element 261 in the openings 271, 272, 273 and forms a second patterned conductive layer 28 on the molding layer 27, and electrically connects the first conductive connecting element 261 and the second conductive connecting element 262 exposed to the molding layer 27. In the present embodiment, the first conductive connecting element 261 and the second patterned conductive layer 28 can be formed simultaneously, and the photolithography and etching technique can be used in combination with an additional photoresist layer (not shown) to perform the exposure, development and etching processes, and the electroplating process can be performed to form the first conductive connecting element 261 and the second patterned conductive layer 28.
Next, steps 39 and 40 are the same as steps S19 and S20 of the first embodiment, and therefore are not described again.
The semiconductor package 20 of the present invention can be electrically connected to a circuit board 30 through the conductive bumps 32 as shown in fig. 4. The circuit board 30 may be a printed circuit board, a metal core (metal core) circuit board, or a glass circuit board.
In addition, as shown in fig. 5, openings 274 and 275 are formed on the passivation layer 27a by laser drilling to expose a portion of the second patterned conductive layer 28, and an electronic component 33 is electrically connected to the second patterned conductive layer 28 through the conductive bump 34.
In summary, the semiconductor package and the manufacturing method thereof according to the present invention dispose the first power chip and the second power chip, such as transistor chips, in an inverted manner, and have the following features:
(1) the first power chip and the second power chip are disposed in a reversed manner, so that the distance between the chips for electrical connection is shortened to increase the electrical performance, and the height of the package structure is reduced.
(2) The semiconductor process is used for replacing the existing reflow process so as to greatly improve the precision of the packaging structure.
(3) The process abandons the reflow process containing lead, thereby meeting the environmental protection trend and the requirement of the law.
(4) One side of the power chip is fixed on the first patterned conductive layer by using the heat conduction adhesion layer, so that the process can be simplified.
It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Claims (12)

1. A semiconductor package structure, comprising:
a first patterned conductive layer;
a first power chip having a first front surface and a first back surface, and disposed with the first front surface facing the first patterned conductive layer, the first front surface of the first power chip having a first electrode layout, and the first back surface having a second electrode layout;
a second power chip, disposed adjacent to the first power chip, having a second front surface and a second back surface, and disposed with the second back surface facing the first patterned conductive layer, wherein the second front surface of the second power chip has a third electrode layout, and the second back surface has a fourth electrode layout, wherein the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the fourth electrode layout of the second power chip;
a conductive adhesive layer electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer, and electrically connected between the fourth electrode layout of the second power chip and the first patterned conductive layer;
the second patterned conductive layer is arranged opposite to the first patterned conductive layer, and the first back surface of the first power wafer and the second front surface of the second power wafer face the second patterned conductive layer;
a first conductive connecting element electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and electrically connected between the third electrode layout of the second power chip and the second patterned conductive layer;
a second conductive connecting element electrically connected between the first patterned conductive layer and the second patterned conductive layer; and
and the molding sealing layer is used for coating the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connecting element and the second conductive connecting element.
2. The semiconductor package according to claim 1, wherein the first power chip and the second power chip are each a transistor chip.
3. The semiconductor package according to claim 2, wherein the first electrode layout and the third electrode layout respectively comprise a gate and a source, and the second electrode layout and the fourth electrode layout respectively comprise a drain.
4. The semiconductor package according to claim 3, wherein the drain of the second electrode layout is electrically connected to the source of the third electrode layout.
5. The semiconductor package according to claim 1, wherein the molding compound is a phenolic-based resin, an epoxy-based resin, or a silicon-based resin.
6. A method for manufacturing a semiconductor package structure, comprising:
providing a bearing plate;
forming a first patterned conductive layer on a surface of the carrier plate;
arranging a conductive adhesive layer on part of the first patterned conductive layer;
disposing a first power chip on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power chip contacts the conductive adhesive layer;
disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout of a second back surface of the second power chip contacts the conductive adhesive layer, wherein the first electrode layout of the first power chip is identical to the third electrode layout of the second power chip, and the second electrode layout of the first power chip is identical to the fourth electrode layout of the second power chip;
forming at least one conductive connecting element on the first patterned conductive layer without the conductive adhesive layer, a second electrode layout on a first back surface of the first power chip, and/or a third electrode layout on a second front surface of the second power chip;
forming a mold sealing layer on the carrier plate and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the conductive connecting element;
forming a second patterned conductive layer on the molding layer and electrically connected to the conductive connecting element exposed to the molding layer; and
the carrier plate is removed.
7. The method as claimed in claim 6, wherein at least one drain of the first back side of the first power chip is electrically connected to at least one source of the second front side of the second power chip.
8. The method of manufacturing a semiconductor package according to claim 6, further comprising:
forming a protective layer on the molding layer to cover the second patterned conductive layer.
9. A method for manufacturing a semiconductor package structure, comprising:
providing a bearing plate;
forming a first patterned conductive layer on a surface of the carrier plate;
arranging a conductive adhesive layer on part of the first patterned conductive layer;
disposing a first power chip on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power chip contacts the conductive adhesive layer;
disposing a second power chip on the conductive adhesive layer, wherein a fourth electrode layout of a second back surface of the second power chip contacts the conductive adhesive layer, wherein the first electrode layout of the first power chip is identical to the third electrode layout of the second power chip, and the second electrode layout of the first power chip is identical to the fourth electrode layout of the second power chip;
forming at least one second conductive connecting element on the first patterned conductive layer without the conductive adhesive layer;
forming a mold sealing layer on the carrier plate and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the second conductive connecting element;
forming a plurality of openings on the molding layer corresponding to a second electrode layout on a first back surface of the first power chip and a third electrode layout on a second front surface of the second power chip;
forming a first conductive connecting element on the openings;
forming a second patterned conductive layer on the molding layer and electrically connected to the first conductive connecting element and the second conductive connecting element exposed to the molding layer; and
the carrier plate is removed.
10. The method as claimed in claim 9, wherein at least one drain of the first back side of the first power chip is electrically connected to at least one source of the second front side of the second power chip.
11. The method of manufacturing a semiconductor package according to claim 9, further comprising:
forming a protective layer on the molding layer to cover the second patterned conductive layer.
12. The method of claim 9, wherein the first conductive connecting element and the second patterned conductive layer are formed simultaneously in one process.
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