TWI682513B - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
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- TWI682513B TWI682513B TW108106686A TW108106686A TWI682513B TW I682513 B TWI682513 B TW I682513B TW 108106686 A TW108106686 A TW 108106686A TW 108106686 A TW108106686 A TW 108106686A TW I682513 B TWI682513 B TW I682513B
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
Description
本發明係關於一種封裝結構及其製造方法,特別關於一種半導體封裝結構及其製造方法。 The invention relates to a packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure and a manufacturing method thereof.
隨著資訊與車用電子的需求大幅增長,四方平面無引腳封裝(Quad Flat No-Lead;QFN)封裝結構因為具備較佳的散熱效果以及較低的阻抗值及電磁干擾,目前已成為重要的半導體封裝技術。 As the demand for information and automotive electronics has grown significantly, the Quad Flat No-Lead (QFN) package structure has become more important because of its better heat dissipation and lower impedance and electromagnetic interference. Semiconductor packaging technology.
而在QFN封裝結構中,銅片橋接(copper clip)技術是因應大功率需求而產生的技術。銅片設計成具有高低落差的拱橋形狀,利用點錫膏製程(solder dispenser)將銅片與晶片接合,其具有較小的阻抗以承載大電流,並且可承受熱應力產生的變形,因而適用於例如電晶體等高功率元件。 In the QFN packaging structure, copper clip technology is a technology that is generated in response to high power requirements. The copper sheet is designed as an arch bridge with a high and low drop. The solder sheet is used to join the copper sheet to the wafer. It has a small impedance to carry large currents and can withstand the deformation caused by thermal stress, so it is suitable for For example, high-power components such as transistors.
以下請參照第1A圖至第1D圖,以簡單說明習知的封裝結構中利用銅片橋接技術接合電晶體的部份。 In the following, please refer to FIGS. 1A to 1D to briefly explain the part of the conventional package structure that uses the copper bridge technology to join the transistors.
如第1A圖所示,係於一導線架(lead frame)101上配合網版印刷形成一錫膏層102。接著,如第1B圖,將一電晶體晶片103置放於錫膏層102上。而後,如第1C圖,於電晶體晶片103上形成銲錫104。最後,如第1D圖,將一橋接銅片105置放於對應的錫膏層102以及銲錫104上,並經過攝氏380度的高溫回銲製程後而使導線架101、電晶體晶片103及橋接銅片105相互接合。
As shown in FIG. 1A, a
上述的製程及成品至少具有下列問題: The above process and finished products have at least the following problems:
(1)封裝結構使用了導線架以及橋接銅片,因此封裝的高度(厚度)無法降低,而限制了其應用領域。 (1) The package structure uses lead frames and bridging copper sheets, so the height (thickness) of the package cannot be reduced, which limits its application field.
(2)銲錫或錫膏中皆含有相當高比例的鉛,而鉛金 屬會造成環境污染且對人體健康有著相當程度的影響。 (2) Both solder and solder paste contain a relatively high percentage of lead, while lead gold Genera cause environmental pollution and have a considerable impact on human health.
(3)在攝氏380度的高溫回銲製程固定所有元件之前可能發生各個元件位移,而導致精度下降。 (3) The displacement of each component may occur before fixing all components in the high-temperature reflow process of 380 degrees Celsius, resulting in a decrease in accuracy.
因此,如何改善上述缺點而提供一種能夠整合高功率元件的半導體封裝結構及其製造方法,實屬當前重要課題之一。 Therefore, how to improve the above-mentioned shortcomings and provide a semiconductor package structure capable of integrating high-power devices and a manufacturing method thereof are indeed one of the current important issues.
有鑑於上述,本發明之一目的是提供一種半導體封裝結構及其製造方法,其能夠降低含有高功率元件的半導體封裝結構的高度,同時可以增加電性效能。本發明之另一目的是提供一種半導體封裝結構及其製造方法,其能夠不使用含鉛的製程而可符合環保法令之需求。 In view of the above, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which can reduce the height of a semiconductor package structure containing high-power components and can increase electrical performance. Another object of the present invention is to provide a semiconductor packaging structure and a manufacturing method thereof, which can meet the requirements of environmental protection laws without using a lead-containing manufacturing process.
為達上述目的,本發明提供一種半導體封裝結構,其包括一第一圖案化導電層、一第一功率晶片、一第二功率晶片、一導電黏著層、一第二圖案化導電層、一第一導電連接元件、一第二導電連接元件以及一模封層。 To achieve the above object, the present invention provides a semiconductor package structure including a first patterned conductive layer, a first power chip, a second power chip, a conductive adhesive layer, a second patterned conductive layer, a first A conductive connection element, a second conductive connection element and a mold seal layer.
第一功率晶片具有一第一正面及一第一背面,並且係以第一正面朝向第一圖案化導電層設置。第一功率晶片之第一正面具有一第一電極布局,而於第一背面具有一第二電極布局。 The first power chip has a first front surface and a first back surface, and is disposed with the first front surface facing the first patterned conductive layer. The first front surface of the first power chip has a first electrode layout, and the first back surface has a second electrode layout.
第二功率晶片鄰設於第一功率晶片,並且具有一第二正面及一第二背面,且係以第二背面朝向第一圖案化導電層設置。第二功率晶片之第二正面具有一第三電極布局,而於第二背面具有一第四電極布局。 The second power chip is adjacent to the first power chip, and has a second front surface and a second back surface, and is disposed with the second back surface facing the first patterned conductive layer. The second front surface of the second power chip has a third electrode layout, and the second rear surface has a fourth electrode layout.
導電黏著層電性連接於第一功率晶片之第一電極布局與第一圖案化導電層之間。另外,導電黏著層亦電性連接於第二功率晶片之第四電極布局與第一圖案化導電層之間。 The conductive adhesive layer is electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer. In addition, the conductive adhesive layer is also electrically connected between the fourth electrode layout of the second power chip and the first patterned conductive layer.
第二圖案化導電層與第一圖案化導電層相對設置,且第一功率晶片之第一背面及第二功率晶片之第二正面係朝向第二圖案化導電層設置。 The second patterned conductive layer is disposed opposite to the first patterned conductive layer, and the first back surface of the first power chip and the second front surface of the second power chip are disposed toward the second patterned conductive layer.
第一導電連接元件電性連接於第一功率晶片之第二電極布局與第二圖案化導電層之間,以及電性連接於第二功率晶 片之第三電極布局與第二圖案化導電層之間。 The first conductive connection element is electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and electrically connected to the second power crystal Between the third electrode layout of the sheet and the second patterned conductive layer.
第二導電連接元件電性連接於第一圖案化導電層與第二圖案化導電層之間,並使其電性連接。 The second conductive connection element is electrically connected between the first patterned conductive layer and the second patterned conductive layer, and is electrically connected.
模封層係包覆第一圖案化導電層、導電黏著層、第一功率晶片、第二功率晶片、第一導電連接元件及第二導電連接元件。 The mold sealing layer covers the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connection element and the second conductive connection element.
依據本發明之一實施例,其中第一功率晶片之第一電極布局相同於第二功率晶片之第三電極布局,且第一功率晶片之第二電極布局相同於第二功率晶片之第四電極布局。 According to an embodiment of the present invention, the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the fourth electrode of the second power chip layout.
依據本發明之一實施例,其中第一功率晶片及第二功率晶片係分別為一電晶體晶片。 According to an embodiment of the present invention, the first power chip and the second power chip are respectively a transistor chip.
依據本發明之一實施例,其中第一電極布局及第三電極布局係分別包含一閘極及一源極,而第二電極布局及第四電極布局係分別包含一汲極。 According to an embodiment of the present invention, the first electrode layout and the third electrode layout include a gate electrode and a source electrode, respectively, and the second electrode layout and the fourth electrode layout include a drain electrode, respectively.
依據本發明之一實施例,其中第二電極布局之汲極係電性連接於第三電極布局之源極。 According to an embodiment of the invention, the drain electrode of the second electrode layout is electrically connected to the source electrode of the third electrode layout.
依據本發明之一實施例,其中模封層之材質係為鑄模化合物,其係以酚醛基樹脂、環氧基樹脂或矽基樹脂為主要基質。 According to an embodiment of the present invention, the material of the mold sealing layer is a mold compound, which is based on phenolic resin, epoxy resin or silicon resin.
另外,為達上述目的,本發明提供一種半導體封裝結構的製造方法,其包括下列步驟:步驟一係提供一承載板;步驟二係形成一第一圖案化導電層於承載板之一表面;步驟三係設置一導電黏著層於部分之第一圖案化導電層上;步驟四係設置一第一功率晶片於導電黏著層上,其中第一功率晶片之一第一正面之一第一電極布局係接觸於導電黏著層;步驟五係設置一第二功率晶片於導電黏著層上,其中第二功率晶片之一第二背面之一第四電極布局係接觸於導電黏著層;步驟六係形成至少一導電連接元件於未設置導電黏著層之第一圖案化導電層、第一功率晶片之一第一背面之一第二電極布局及/或第二功率晶片之一第二正面之一第三電極布局;步驟七係形成一模封層於承載板上,並且包覆
第一圖案化導電層、導電黏著層、第一功率晶片、第二功率晶片及導電連接元件;步驟八係形成一第二圖案化導電層於模封層上,並且電性連接於暴露於模封層之導電連接元件;步驟九係移除承載板。
In addition, to achieve the above object, the present invention provides a method for manufacturing a semiconductor package structure, which includes the following steps: step one is to provide a carrier board; step two is to form a first patterned conductive layer on one surface of the carrier board; step Three sets a conductive adhesive layer on part of the first patterned conductive layer; Step 4 sets a first power chip on the conductive adhesive layer, wherein the first electrode layout on a first front side of a first power chip Contact with the conductive adhesive layer; Step 5 is to set a second power chip on the conductive adhesive layer, wherein the fourth electrode layout of the second back surface of the second power chip is in contact with the conductive adhesive layer; Step 6 is to form at least one The layout of the conductive connection element on the first patterned conductive layer without the conductive adhesive layer, the second electrode on the first back surface of the first power chip and/or the third electrode on the second front surface of the second power chip ;
依據本發明之一實施例,其中第一功率晶片之第一背面之至少一汲極係電性連接於第二功率晶片之第二正面之至少一源極。 According to an embodiment of the invention, at least one drain electrode of the first back surface of the first power chip is electrically connected to at least one source electrode of the second front surface of the second power chip.
再者,為達上述目的,本發明提供一種半導體封裝結構的製造方法包括下列步驟:步驟一係提供一承載板;步驟二係形成一第一圖案化導電層於承載板之一表面;步驟三係設置一導電黏著層於部分之第一圖案化導電層上;步驟四係設置一第一功率晶片於導電黏著層上,其中第一功率晶片之一第一正面之一第一電極布局係接觸於導電黏著層;步驟五係設置一第二功率晶片於導電黏著層上,其中第二功率晶片之一第二背面之一第四電極布局係接觸於導電黏著層;步驟六係形成至少一第二導電連接元件於未設置導電黏著層之第一圖案化導電層;步驟七係形成一模封層於承載板上,並且包覆第一圖案化導電層、導電黏著層、第一功率晶片、第二功率晶片及第二導電連接元件;步驟八係於模封層上對應於第一功率晶片之一第一背面之一第二電極布局及第二功率晶片之一第二正面之一第三電極布局形成複數個開口;步驟九係形成一第一導電連接元件於該些開口;步驟十係形成一第二圖案化導電層於模封層上,並且電性連接於暴露於模封層之第一導電連接元件及第二導電連接元件;以及步驟十一係移除承載板。
Furthermore, in order to achieve the above object, the present invention provides a method for manufacturing a semiconductor package structure including the following steps: step one is to provide a carrier board; step two is to form a first patterned conductive layer on one surface of the carrier board; step three A conductive adhesive layer is provided on part of the first patterned conductive layer; Step 4 is to set a first power chip on the conductive adhesive layer, wherein a first electrode layout on a first front side of a first power chip is in contact In the conductive adhesive layer; Step 5 is to set a second power chip on the conductive adhesive layer, wherein a fourth electrode layout on the second back surface of the second power chip is in contact with the conductive adhesive layer; Step 6 is to form at least a first The two conductive connection elements are on the first patterned conductive layer without the conductive adhesive layer;
依據本發明之一實施例,其中第一導電連接元件及第二圖案化導電層係同時於一工序中形成。 According to an embodiment of the present invention, the first conductive connection element and the second patterned conductive layer are simultaneously formed in one process.
承上所述,本發明之一種半導體封裝結構及其製造方法係將例如為電晶體晶片的第一功率晶片以及第二功率晶片以相互顛倒的方式設置,據以縮短晶片之間電性連接的距離以增加電性效能。另一方面,利用半導體製程取代習知的含鉛及高溫回 銲製程,除了能夠大幅度的提高封裝結構的精度,更能符合無鉛的環保製程趨勢需求。 As mentioned above, a semiconductor package structure and a manufacturing method thereof according to the present invention arrange the first power chip and the second power chip, which are, for example, transistor chips, in an inverted manner to shorten the electrical connection between the chips Distance to increase electrical performance. On the other hand, the semiconductor process is used to replace the conventional lead and high temperature return In addition to greatly improving the accuracy of the packaging structure, the soldering process can also meet the trend of lead-free environmental protection process.
101‧‧‧導線架 101‧‧‧ Lead frame
102‧‧‧錫膏層 102‧‧‧ solder paste layer
103‧‧‧電晶體晶片 103‧‧‧Transistor chip
104‧‧‧銲錫 104‧‧‧Solder
105‧‧‧橋接銅片 105‧‧‧bridging copper
20‧‧‧半導體封裝結構 20‧‧‧Semiconductor packaging structure
21‧‧‧承載板 21‧‧‧Bearing plate
211‧‧‧表面 211‧‧‧Surface
22‧‧‧第一圖案化導電層 22‧‧‧The first patterned conductive layer
23‧‧‧導電黏著層 23‧‧‧ conductive adhesive layer
24‧‧‧第一功率晶片 24‧‧‧ First power chip
241‧‧‧第一正面 241‧‧‧First positive
242‧‧‧第一背面 242‧‧‧The first back
25‧‧‧第二功率晶片 25‧‧‧ Second power chip
251‧‧‧第二正面 251‧‧‧Second front
252‧‧‧第二背面 252‧‧‧Second back
261‧‧‧第一導電連接元件 261‧‧‧First conductive connecting element
262‧‧‧第二導電連接元件 262‧‧‧Second conductive connecting element
27‧‧‧模封層 27‧‧‧mold seal layer
27a‧‧‧保護層 27a‧‧‧Protection layer
271、272、273、274、275‧‧‧開口 271, 272, 273, 274, 275
28‧‧‧第二圖案化導電層 28‧‧‧Second patterned conductive layer
30‧‧‧電路板 30‧‧‧ circuit board
33‧‧‧電子元件 33‧‧‧Electronic components
32、34‧‧‧導電凸塊 32, 34‧‧‧ conductive bump
D1、D2‧‧‧汲極 D1, D2‧‧‧ji
G1、G2‧‧‧閘極 G1, G2 ‧‧‧ gate
S1、S2‧‧‧源極 S1, S2‧‧‧Source
T01、T02‧‧‧頂端 T01, T02‧‧‧Top
第1A圖至第1D圖係顯示先前技術之封裝結構中利用銅片橋接技術接合電晶體的製造方法示意圖。 FIGS. 1A to 1D are schematic diagrams showing a manufacturing method of bonding transistors using a copper bridge technology in a packaging structure of the prior art.
第2A圖至第2I圖係顯示依據本發明第一實施例之半導體封裝結構之製造方法示意圖。 FIGS. 2A to 2I are schematic diagrams showing the manufacturing method of the semiconductor package structure according to the first embodiment of the present invention.
第3A圖至第3D圖係顯示依據本發明第二實施例之部分半導體封裝結構之製造方法示意圖。 FIGS. 3A to 3D are schematic diagrams showing a method of manufacturing a partial semiconductor package structure according to the second embodiment of the present invention.
第4圖係本發明較佳實施例之半導體封裝結構設置於電路板之一示意圖。 FIG. 4 is a schematic diagram of a semiconductor package structure provided on a circuit board according to a preferred embodiment of the present invention.
第5圖係本發明較佳實施例之承載有電子元件之半導體封裝結構設置於電路板之一示意圖。 FIG. 5 is a schematic diagram of a semiconductor package structure with electronic components mounted on a circuit board according to a preferred embodiment of the present invention.
以下將透過實施例來解釋本發明內容,本發明的實施例並非用以限制本發明須在如實施例所述之任何特定的環境、應用或特殊方式方能實施。因此,關於實施例之說明僅為闡釋本發明之目的,而非用以限制本發明。須說明者,以下實施例及圖式中,與本發明非直接相關之元件已省略而未繪示;且圖式中各元件間之尺寸關係僅為求容易瞭解,非用以限制實際比例。另外,以下實施例中,相同的元件將以相同的元件符號加以說明。 The following will explain the content of the present invention through the embodiments. The embodiments of the present invention are not intended to limit the invention to be implemented in any specific environment, application, or special manner as described in the embodiments. Therefore, the description of the embodiments is only for the purpose of explaining the present invention, not for limiting the present invention. It should be noted that, in the following embodiments and drawings, elements not directly related to the present invention have been omitted and not shown; and the dimensional relationship between the elements in the drawings is only for easy understanding and is not intended to limit the actual scale. In addition, in the following embodiments, the same elements will be described with the same element symbols.
以下請參照第2A圖至第2I圖,其係本發明第一實施例之半導體封裝結構的製造方法示意圖。半導體封裝結構的製造方法包括步驟S11至步驟S20。 The following refers to FIGS. 2A to 2I, which are schematic diagrams of the method for manufacturing the semiconductor package structure according to the first embodiment of the present invention. The manufacturing method of the semiconductor package structure includes steps S11 to S20.
如第2A圖所示,步驟S11係於一承載板21之一表面211上形成一第一圖案化導電層22。承載板21可以係為金屬板或為絕緣板。第一圖案化導電層22之材料係為導電金屬,例如銅、銀、鎳或其組成之合金,其可利用微影蝕刻技術,配合額外之光阻層(圖中未顯示)執行曝光顯影以及蝕刻工序,並執行電鍍工序,
以形成第一圖案化導電層22。
As shown in FIG. 2A, step S11 is to form a first patterned
於此要特別說明的是,於傳統之晶圓型式(wafer type)之製程中,僅能針對形成於單一晶圓內之晶片(chip)或晶粒(die)同時進行封裝製程,其較為耗時且具有製程上之諸多限制。相較於傳統之晶圓型式之封裝製程,本發明採用大尺寸板面型式(panel level type)之封裝製程。其中,承載板21之面積為單一晶圓面積之複數倍。據此,本發明之承載板21能夠對於切割自複數個晶圓之全部晶片(或晶粒)同時進行封裝製程,而能有效節省製造時間。
It should be particularly noted that in the conventional wafer type process, only the chip or die formed in a single wafer can be packaged simultaneously, which is more expensive Sometimes there are many limitations in the manufacturing process. Compared with the conventional wafer type packaging process, the present invention uses a large-sized panel level type packaging process. The area of the
接著,如第2B圖所示,步驟S12係設置一導電黏著層23於部分之第一圖案化導電層22上。導電黏著層23係可為導電膠,其材料可包含高散熱導電材料,例如銀或銅。在其他實施例中,導電黏著層23還可以是異方性導電膠,以提供垂直(Z軸)導通之用。
Next, as shown in FIG. 2B, step S12 is to provide a conductive
接著,如第2C圖所示,步驟S13係設置一第一功率晶片24於導電黏著層23上。第一功率晶片24具有一第一正面241及一第一背面242。在第一正面241具有一第一電極布局,而在第一背面242具有一第二電極布局。其中,第一正面241之第一電極布局係接觸於導電黏著層23。
Next, as shown in FIG. 2C, step S13 is to set a
接著,步驟S14係設置一第二功率晶片25於導電黏著層23上。第二功率晶片25具有一第二正面251及一第二背面252。在第二正面251具有一第三電極布局,而在第二背面252則具有一第四電極布局。其中,第二背面252之第四電極布局係接觸於導電黏著層23。
Next, step S14 is to set a
在本實施例中,第一功率晶片24以及第二功率晶片25係分別為一電晶體晶片,例如金屬氧化物半導體場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor;MOSFET)晶片。因此,第一電極布局以及第三電極布局係分別包括一閘極(Gate)G1、G2及一源極(Source)S1、S2。另一方面,第二電極布局以及第四電極布局則係分別包括一汲極(Drain)D1、D2。
在其他實施例中,電晶體晶片還可以是雙極性接面電晶體(bipolar junction transistor;BJT)晶片或是絕緣柵雙極電晶體(Insulated Gate Bipolar Transistor;IGBT)晶片等。
In this embodiment, the
基於上述,第一功率晶片24以及第二功率晶片25係相同的元件,因此第一功率晶片24之第一電極布局係相同於第二功率晶片25之第三電極布局,且第一功率晶片24之第二電極布局係相同於第二功率晶片25之第四電極布局。換言之,第一功率晶片24以及第二功率晶片25係以相互顛倒的方式設置於導電黏著層23上。
Based on the above, the
接著,如第2D圖所示,步驟S15係形成一第一導電連接元件261於第一功率晶片24之第一背面242之第二電極布局及第二功率晶片25之第二正面251之第三電極布局。第一導電連接元件261可以利用微影蝕刻技術,配合額外之光阻層(圖中未顯示)執行曝光顯影以及蝕刻工序,並執行電鍍工序而形成。
Next, as shown in FIG. 2D, step S15 is to form a first
接著,如第2E圖所示,步驟S16係形成一第二導電連接元件262於未設置導電黏著層23之第一圖案化導電層22上。第二導電連接元件262,例如導電柱,其材質係為金屬,可以透過電鍍工序而直接形成於第一圖案化導電層22上,除了提供電傳導路徑之外,還可增加支撐強度。在其他實施例中,第二導電連接元件262還可以預先成形後再藉由導電膠而固定並且電性連接於第一圖案化導電層22(圖中未示)。
Next, as shown in FIG. 2E, step S16 forms a second
接著,如第2F圖所示,步驟S17係形成一模封層27於承載板21上,並且包覆第一圖案化導電層22、導電黏著層23、第一功率晶片24、第二功率晶片25、第一導電連接元件261以及第二導電連接元件262。其中,模封層27之材質可以為高填料含量介電材(high filler content dielectric material),例如為鑄模化合物(molding compound),其係以酚醛基樹脂(Novolac-Based Resin)、環氧基樹脂(Epoxy-Based Resin)或矽基樹脂(Silicone-Based Resin)為主要基質,其佔鑄模化合物之整體比例約為8wt.%~12wt.%,並摻雜佔整體比例約70wt.%~90wt.%的
填充劑而形成。其中,填充劑可以包括二氧化矽及氧化鋁,以達到增加機械強度、降低線性熱膨脹係數、增加熱傳導、增加阻水及減少溢膠的功效。
Next, as shown in FIG. 2F, step S17 forms a
在本實施例中,步驟S17還包括透過研磨工序研磨模封層27之頂部,以顯露出第一導電連接元件261以及第二導電連接元件262之頂端T01、T02。
In this embodiment, step S17 further includes grinding the top of the
接著,如第2G圖所示,步驟S18係形成一第二圖案化導電層28於模封層27上,並且電性連接於暴露於模封層27之第一導電連接元件261及第二導電連接元件262。
Next, as shown in FIG. 2G, step S18 forms a second patterned
接著,如第2H圖所示,步驟S19係形成保護層(cover layer)27a於模封層27上,並且包覆第二圖案化導電層28,據以保護嵌埋於模封層27以及保護層27a內之元件。在本實施例中,還可選擇性地執行研磨工序研磨保護層27a之頂部。
Next, as shown in FIG. 2H, step S19 is to form a
最後,如第2I圖所示,步驟S20係移除承載板21,據以形成一半導體封裝結構20。在本實施例中,第一功率晶片24以及第二功率晶片25係以相互顛倒的方式設置,且第一功率晶片24之汲極D1係透過第一導電連接元件261以及第二圖案化導電層28而與第二功率晶片25之源極S2電性連接。據此,可以縮短汲極D1以及源極S2之間的電傳導距離,而可增加電性效果,另一方面,也使得半導體封裝結構能夠應用於半橋電路。
Finally, as shown in FIG. 2I, step S20 is to remove the
以下接著說明本發明第二實施例之半導體封裝結構的製造方法。在本實施例中,半導體封裝結構的製造方法包括步驟S31至步驟S40。由於本實施例之製造方法與第一實施例之製造方法有部分的步驟示相同的,因此將省略該相同的步驟敘述。另外,在本實施例中係沿用第一實施例之元件符號。 Next, a method of manufacturing the semiconductor package structure according to the second embodiment of the present invention will be explained. In this embodiment, the manufacturing method of the semiconductor package structure includes steps S31 to S40. Since the manufacturing method of this embodiment is partially the same as the manufacturing method of the first embodiment, the description of the same steps will be omitted. In addition, in this embodiment, the element symbols of the first embodiment are used.
首先,步驟S31至步驟S34係與第一實施例之步驟S11至步驟S14相同,故於此不再加以贅述。 First, steps S31 to S34 are the same as steps S11 to S14 of the first embodiment, so they will not be repeated here.
接著,如第3A圖所示,步驟S35係形成第二導電連接元件262於未設置導電黏著層23之第一圖案化導電層22上。與上述實施例相同,第二導電連接元件262,例如導電柱,其材質係為金
屬,可以透過電鍍工序而直接形成於第一圖案化導電層22上,除了提供電傳導路徑之外,還可增加支撐強度。在其他實施例中,第二導電連接元件262還可以預先成形後再藉由導電膠而固定並且電性連接於第一圖案化導電層22(圖中未示)。
Next, as shown in FIG. 3A, step S35 is to form a second
接著,如第3B圖所示,步驟S36係形成模封層27於承載板21上,並且包覆第一圖案化導電層22、導電黏著層23、第一功率晶片24、第二功率晶片25以及第二導電連接元件262。另外,步驟S36還可包括透過研磨工序研磨模封層27之頂部,以顯露出第二導電連接元件262之頂端T02。
Next, as shown in FIG. 3B, step S36 forms a
接著,如第3C圖所示,步驟S37係以雷射鑽孔(laser drilling)技術於模封層27分別對應於第一功率晶片24之汲極D1以及第二功率晶片25之源極S2及閘極G2之位置形成三個開口271、272、273,以暴露出第一功率晶片24之汲極D1以及第二功率晶片25之源極S2及閘極G2。
Next, as shown in FIG. 3C, step S37 is to use a laser drilling technique on the
接著,如第3D圖所示,步驟S38係形成第一導電連接元件261於開口271、272、273以及形成第二圖案化導電層28於模封層27上,並且電性連接於暴露於模封層27之第一導電連接元件261及第二導電連接元件262。在本實施例中,第一導電連接元件261以及第二圖案化導電層28係可同時形成,可利用微影蝕刻技術配合額外之光阻層(圖中未顯示)執行曝光顯影以及蝕刻工序,並執行電鍍工序以形成第一導電連接元件261以及第二圖案化導電層28。
Next, as shown in FIG. 3D, step S38 is to form the first
接著,步驟39及步驟40係與第一實施例之步驟S19及步驟S20相同,故於此不再加以贅述。 Next, Step 39 and Step 40 are the same as Step S19 and Step S20 of the first embodiment, so they will not be repeated here.
本發明之半導體封裝結構20可以如第4圖所示,藉由導電凸塊32而電性連接於一電路板30上。其中,電路板30可以是印刷電路板、金屬核心(metal core)電路板或玻璃電路板。
The
另外,還可如第5圖所示,於保護層27a上以雷射鑽孔技術形成開口274、275以暴露出部分的第二圖案化導電層28,並將一電子元件33透過導電凸塊34而電性連接於第二圖案化導電
層28。
In addition, as shown in FIG. 5,
綜上所述,本發明之一種半導體封裝結構及其製造方法係將例如為電晶體晶片的第一功率晶片以及第二功率晶片以相互顛倒的方式設置,其具有下列特點: In summary, a semiconductor package structure and a manufacturing method thereof according to the present invention arrange the first power chip and the second power chip, which are, for example, transistor chips, in an inverse manner, which has the following characteristics:
(1)將第一功率晶片以及第二功率晶片以相互顛倒的方式設置,得縮短晶片之間電性連接的距離以增加電性效能,且可減少封裝結構的高度。 (1) The first power chip and the second power chip are arranged in an inverse manner to shorten the distance of the electrical connection between the chips to increase the electrical performance and reduce the height of the packaging structure.
(2)利用半導體製程取代習知的回銲製程,以大幅度的提高封裝結構的精度。 (2) The semiconductor process is used to replace the conventional reflow process to greatly improve the accuracy of the packaging structure.
(3)製程中捨棄含鉛的回銲製程,因而可以符合環保的趨勢以及法令的需求。 (3) Abandon the lead-containing reflow process in the process, so it can meet the trend of environmental protection and the requirements of laws and regulations.
(4)功率晶片之一側係使用導熱黏著層來固定於第一圖案化導電層,可以簡化製程。 (4) One side of the power chip is fixed to the first patterned conductive layer using a thermally conductive adhesive layer, which can simplify the manufacturing process.
本發明符合發明專利之要件,爰依法提出專利申請。惟,以上所述者僅為本發明之較佳實施例,自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士,爰依本案發明精神所作之等效修飾或變化,皆應包括於以下之申請專利範圍內。 This invention meets the requirements of the invention patent, and the patent application is filed in accordance with the law. However, the above are only the preferred embodiments of the present invention, and thus cannot limit the scope of patent application in this case. Anyone who is familiar with the skills of this case and equivalent modifications or changes made in accordance with the spirit of the invention of this case should be included in the scope of the following patent applications.
20‧‧‧半導體封裝結構 20‧‧‧Semiconductor packaging structure
22‧‧‧第一圖案化導電層 22‧‧‧The first patterned conductive layer
23‧‧‧導電黏著層 23‧‧‧ conductive adhesive layer
24‧‧‧第一功率晶片 24‧‧‧ First power chip
25‧‧‧第二功率晶片 25‧‧‧ Second power chip
261‧‧‧第一導電連接元件 261‧‧‧First conductive connecting element
262‧‧‧第二導電連接元件 262‧‧‧Second conductive connecting element
27‧‧‧模封層 27‧‧‧mold seal layer
27a‧‧‧保護層 27a‧‧‧Protection layer
28‧‧‧第二圖案化導電層 28‧‧‧Second patterned conductive layer
G1、G2‧‧‧閘極 G1, G2 ‧‧‧ gate
S1、S2‧‧‧源極 S1, S2‧‧‧Source
D1、D2‧‧‧汲極 D1, D2‧‧‧ji
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