TWI682513B - Semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor package structure includes a first patterned conductive layer, a first power chip, a second power chip, a conductive adhesive layer, a second patterned conductive layer, a first conductive connection component, a second conductive connection component and a mold layer. The first power chip and the second power chip are embedded in the mold layer in such a manner that the positive side and the negative side are opposite to each other. In addition, one side of the first power chip and the second power chip are fixed to the first patterned conductive layer through the conductive adhesive layer. Furthermore, a manufacturing method of semiconductor package structures is also disclosed.

Description

Semiconductor packaging structure and manufacturing method thereof

The invention relates to a packaging structure and a manufacturing method thereof, in particular to a semiconductor packaging structure and a manufacturing method thereof.

As the demand for information and automotive electronics has grown significantly, the Quad Flat No-Lead (QFN) package structure has become more important because of its better heat dissipation and lower impedance and electromagnetic interference. Semiconductor packaging technology.

In the QFN packaging structure, copper clip technology is a technology that is generated in response to high power requirements. The copper sheet is designed as an arch bridge with a high and low drop. The solder sheet is used to join the copper sheet to the wafer. It has a small impedance to carry large currents and can withstand the deformation caused by thermal stress, so it is suitable for For example, high-power components such as transistors.

In the following, please refer to FIGS. 1A to 1D to briefly explain the part of the conventional package structure that uses the copper bridge technology to join the transistors.

As shown in FIG. 1A, a solder paste layer 102 is formed on a lead frame 101 by screen printing. Next, as shown in FIG. 1B, a transistor wafer 103 is placed on the solder paste layer 102. Then, as shown in FIG. 1C, solder 104 is formed on the transistor wafer 103. Finally, as shown in FIG. 1D, a bridging copper sheet 105 is placed on the corresponding solder paste layer 102 and solder 104, and after a high temperature reflow process of 380 degrees Celsius, the lead frame 101, the transistor chip 103 and the bridge The copper sheets 105 are joined to each other.

The above process and finished products have at least the following problems:

(1) The package structure uses lead frames and bridging copper sheets, so the height (thickness) of the package cannot be reduced, which limits its application field.

(2) Both solder and solder paste contain a relatively high percentage of lead, while lead gold Genera cause environmental pollution and have a considerable impact on human health.

(3) The displacement of each component may occur before fixing all components in the high-temperature reflow process of 380 degrees Celsius, resulting in a decrease in accuracy.

Therefore, how to improve the above-mentioned shortcomings and provide a semiconductor package structure capable of integrating high-power devices and a manufacturing method thereof are indeed one of the current important issues.

In view of the above, an object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same, which can reduce the height of a semiconductor package structure containing high-power components and can increase electrical performance. Another object of the present invention is to provide a semiconductor packaging structure and a manufacturing method thereof, which can meet the requirements of environmental protection laws without using a lead-containing manufacturing process.

To achieve the above object, the present invention provides a semiconductor package structure including a first patterned conductive layer, a first power chip, a second power chip, a conductive adhesive layer, a second patterned conductive layer, a first A conductive connection element, a second conductive connection element and a mold seal layer.

The first power chip has a first front surface and a first back surface, and is disposed with the first front surface facing the first patterned conductive layer. The first front surface of the first power chip has a first electrode layout, and the first back surface has a second electrode layout.

The second power chip is adjacent to the first power chip, and has a second front surface and a second back surface, and is disposed with the second back surface facing the first patterned conductive layer. The second front surface of the second power chip has a third electrode layout, and the second rear surface has a fourth electrode layout.

The conductive adhesive layer is electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer. In addition, the conductive adhesive layer is also electrically connected between the fourth electrode layout of the second power chip and the first patterned conductive layer.

The second patterned conductive layer is disposed opposite to the first patterned conductive layer, and the first back surface of the first power chip and the second front surface of the second power chip are disposed toward the second patterned conductive layer.

The first conductive connection element is electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and electrically connected to the second power crystal Between the third electrode layout of the sheet and the second patterned conductive layer.

The second conductive connection element is electrically connected between the first patterned conductive layer and the second patterned conductive layer, and is electrically connected.

The mold sealing layer covers the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connection element and the second conductive connection element.

According to an embodiment of the present invention, the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the fourth electrode of the second power chip layout.

According to an embodiment of the present invention, the first power chip and the second power chip are respectively a transistor chip.

According to an embodiment of the present invention, the first electrode layout and the third electrode layout include a gate electrode and a source electrode, respectively, and the second electrode layout and the fourth electrode layout include a drain electrode, respectively.

According to an embodiment of the invention, the drain electrode of the second electrode layout is electrically connected to the source electrode of the third electrode layout.

According to an embodiment of the present invention, the material of the mold sealing layer is a mold compound, which is based on phenolic resin, epoxy resin or silicon resin.

In addition, to achieve the above object, the present invention provides a method for manufacturing a semiconductor package structure, which includes the following steps: step one is to provide a carrier board; step two is to form a first patterned conductive layer on one surface of the carrier board; step Three sets a conductive adhesive layer on part of the first patterned conductive layer; Step 4 sets a first power chip on the conductive adhesive layer, wherein the first electrode layout on a first front side of a first power chip Contact with the conductive adhesive layer; Step 5 is to set a second power chip on the conductive adhesive layer, wherein the fourth electrode layout of the second back surface of the second power chip is in contact with the conductive adhesive layer; Step 6 is to form at least one The layout of the conductive connection element on the first patterned conductive layer without the conductive adhesive layer, the second electrode on the first back surface of the first power chip and/or the third electrode on the second front surface of the second power chip ; Step 7 is to form a mold seal layer on the carrier board, and cover The first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, and the conductive connection elements; Step 8 is to form a second patterned conductive layer on the mold encapsulation layer, and electrically connected to the exposed mold The conductive connection element of the sealing layer; Step 9 is to remove the carrier board.

According to an embodiment of the invention, at least one drain electrode of the first back surface of the first power chip is electrically connected to at least one source electrode of the second front surface of the second power chip.

Furthermore, in order to achieve the above object, the present invention provides a method for manufacturing a semiconductor package structure including the following steps: step one is to provide a carrier board; step two is to form a first patterned conductive layer on one surface of the carrier board; step three A conductive adhesive layer is provided on part of the first patterned conductive layer; Step 4 is to set a first power chip on the conductive adhesive layer, wherein a first electrode layout on a first front side of a first power chip is in contact In the conductive adhesive layer; Step 5 is to set a second power chip on the conductive adhesive layer, wherein a fourth electrode layout on the second back surface of the second power chip is in contact with the conductive adhesive layer; Step 6 is to form at least a first The two conductive connection elements are on the first patterned conductive layer without the conductive adhesive layer; Step 7 is to form a mold sealing layer on the carrier board and cover the first patterned conductive layer, the conductive adhesive layer, the first power chip, The second power chip and the second conductive connection element; Step 8 is a second electrode layout corresponding to a first back surface of the first power chip and a third of the second front surface of the second power chip on the molding layer The electrode layout forms a plurality of openings; step nine is to form a first conductive connection element at the openings; step ten is to form a second patterned conductive layer on the molding layer, and is electrically connected to the exposed molding layer The first conductive connection element and the second conductive connection element; and step eleven is to remove the carrier board.

According to an embodiment of the present invention, the first conductive connection element and the second patterned conductive layer are simultaneously formed in one process.

As mentioned above, a semiconductor package structure and a manufacturing method thereof according to the present invention arrange the first power chip and the second power chip, which are, for example, transistor chips, in an inverted manner to shorten the electrical connection between the chips Distance to increase electrical performance. On the other hand, the semiconductor process is used to replace the conventional lead and high temperature return In addition to greatly improving the accuracy of the packaging structure, the soldering process can also meet the trend of lead-free environmental protection process.

101‧‧‧ Lead frame

102‧‧‧ solder paste layer

103‧‧‧Transistor chip

104‧‧‧Solder

105‧‧‧bridging copper

20‧‧‧Semiconductor packaging structure

21‧‧‧Bearing plate

211‧‧‧Surface

22‧‧‧The first patterned conductive layer

23‧‧‧ conductive adhesive layer

24‧‧‧ First power chip

241‧‧‧First positive

242‧‧‧The first back

25‧‧‧ Second power chip

251‧‧‧Second front

252‧‧‧Second back

261‧‧‧First conductive connecting element

262‧‧‧Second conductive connecting element

27‧‧‧mold seal layer

27a‧‧‧Protection layer

271, 272, 273, 274, 275

28‧‧‧Second patterned conductive layer

30‧‧‧ circuit board

33‧‧‧Electronic components

32, 34‧‧‧ conductive bump

D1, D2‧‧‧ji

G1, G2 ‧‧‧ gate

S1, S2‧‧‧Source

T01, T02‧‧‧Top

FIGS. 1A to 1D are schematic diagrams showing a manufacturing method of bonding transistors using a copper bridge technology in a packaging structure of the prior art.

FIGS. 2A to 2I are schematic diagrams showing the manufacturing method of the semiconductor package structure according to the first embodiment of the present invention.

FIGS. 3A to 3D are schematic diagrams showing a method of manufacturing a partial semiconductor package structure according to the second embodiment of the present invention.

FIG. 4 is a schematic diagram of a semiconductor package structure provided on a circuit board according to a preferred embodiment of the present invention.

FIG. 5 is a schematic diagram of a semiconductor package structure with electronic components mounted on a circuit board according to a preferred embodiment of the present invention.

The following will explain the content of the present invention through the embodiments. The embodiments of the present invention are not intended to limit the invention to be implemented in any specific environment, application, or special manner as described in the embodiments. Therefore, the description of the embodiments is only for the purpose of explaining the present invention, not for limiting the present invention. It should be noted that, in the following embodiments and drawings, elements not directly related to the present invention have been omitted and not shown; and the dimensional relationship between the elements in the drawings is only for easy understanding and is not intended to limit the actual scale. In addition, in the following embodiments, the same elements will be described with the same element symbols.

The following refers to FIGS. 2A to 2I, which are schematic diagrams of the method for manufacturing the semiconductor package structure according to the first embodiment of the present invention. The manufacturing method of the semiconductor package structure includes steps S11 to S20.

As shown in FIG. 2A, step S11 is to form a first patterned conductive layer 22 on a surface 211 of a carrier board 21. The bearing plate 21 may be a metal plate or an insulating plate. The material of the first patterned conductive layer 22 is a conductive metal, such as copper, silver, nickel or alloys composed of it, which can use lithography etching technology with an additional photoresist layer (not shown) to perform exposure development and Etching process, and performing electroplating process, To form the first patterned conductive layer 22.

It should be particularly noted that in the conventional wafer type process, only the chip or die formed in a single wafer can be packaged simultaneously, which is more expensive Sometimes there are many limitations in the manufacturing process. Compared with the conventional wafer type packaging process, the present invention uses a large-sized panel level type packaging process. The area of the carrier board 21 is a multiple of the area of a single wafer. According to this, the carrier board 21 of the present invention can simultaneously perform the packaging process for all wafers (or die) diced from a plurality of wafers, and can effectively save manufacturing time.

Next, as shown in FIG. 2B, step S12 is to provide a conductive adhesive layer 23 on part of the first patterned conductive layer 22. The conductive adhesive layer 23 may be a conductive adhesive, and its material may include a high heat dissipation conductive material, such as silver or copper. In other embodiments, the conductive adhesive layer 23 may also be an anisotropic conductive glue to provide vertical (Z-axis) conduction.

Next, as shown in FIG. 2C, step S13 is to set a first power chip 24 on the conductive adhesive layer 23. The first power chip 24 has a first front surface 241 and a first back surface 242. The first front surface 241 has a first electrode layout, and the first back surface 242 has a second electrode layout. The first electrode layout of the first front surface 241 is in contact with the conductive adhesive layer 23.

Next, step S14 is to set a second power chip 25 on the conductive adhesive layer 23. The second power chip 25 has a second front surface 251 and a second back surface 252. The second front surface 251 has a third electrode layout, and the second rear surface 252 has a fourth electrode layout. The fourth electrode layout of the second back surface 252 is in contact with the conductive adhesive layer 23.

In this embodiment, the first power chip 24 and the second power chip 25 are respectively a transistor chip, such as a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor; MOSFET) chip. Therefore, the first electrode layout and the third electrode layout include a gate G1 and G2 and a source S1 and S2, respectively. On the other hand, the second electrode layout and the fourth electrode layout respectively include a drain D1, D2. In other embodiments, the transistor chip may also be a bipolar junction transistor (BJT) chip or an insulated gate bipolar transistor (IGBT) chip.

Based on the above, the first power chip 24 and the second power chip 25 are the same device, so the first electrode layout of the first power chip 24 is the same as the third electrode layout of the second power chip 25, and the first power chip 24 The second electrode layout is the same as the fourth electrode layout of the second power chip 25. In other words, the first power chip 24 and the second power chip 25 are disposed on the conductive adhesive layer 23 in an inverted manner.

Next, as shown in FIG. 2D, step S15 is to form a first conductive connection element 261 on the second electrode layout of the first back surface 242 of the first power chip 24 and the third of the second front surface 251 of the second power chip 25. Electrode layout. The first conductive connection element 261 can be formed by performing a photolithography etching technique, an additional photoresist layer (not shown in the figure), performing an exposure development and an etching process, and performing an electroplating process.

Next, as shown in FIG. 2E, step S16 forms a second conductive connection element 262 on the first patterned conductive layer 22 without the conductive adhesive layer 23. The second conductive connection element 262, such as a conductive pillar, is made of metal, and can be directly formed on the first patterned conductive layer 22 through an electroplating process. In addition to providing an electrical conduction path, it can also increase the support strength. In other embodiments, the second conductive connection element 262 may be pre-shaped and then fixed by conductive adhesive and electrically connected to the first patterned conductive layer 22 (not shown).

Next, as shown in FIG. 2F, step S17 forms a mold sealing layer 27 on the carrier board 21 and covers the first patterned conductive layer 22, the conductive adhesive layer 23, the first power chip 24, and the second power chip 25. The first conductive connection element 261 and the second conductive connection element 262. The material of the mold sealing layer 27 may be a high filler content dielectric material, such as a molding compound, which is made of Novolac-Based Resin and epoxy resin. (Epoxy-Based Resin) or silicon-based resin (Silicone-Based Resin) as the main matrix, which accounts for the overall proportion of the mold compound is about 8wt.% ~ 12wt.%, and doping accounted for the overall proportion of about 70wt.% ~ 90wt. %of Filler. Among them, the filler may include silica and alumina to achieve the effects of increasing mechanical strength, reducing linear thermal expansion coefficient, increasing heat conduction, increasing water resistance and reducing overflow glue.

In this embodiment, step S17 further includes grinding the top of the molding layer 27 through a grinding process to expose the top ends T01 and T02 of the first conductive connection element 261 and the second conductive connection element 262.

Next, as shown in FIG. 2G, step S18 forms a second patterned conductive layer 28 on the mold layer 27, and is electrically connected to the first conductive connection element 261 and the second conductive exposed to the mold layer 27 Connecting element 262.

Next, as shown in FIG. 2H, step S19 is to form a cover layer 27a on the mold layer 27 and cover the second patterned conductive layer 28 to protect the embedding in the mold layer 27 and the protection Components in layer 27a. In this embodiment, the top of the protective layer 27a may also be selectively polished.

Finally, as shown in FIG. 2I, step S20 is to remove the carrier board 21, thereby forming a semiconductor package structure 20. In this embodiment, the first power chip 24 and the second power chip 25 are arranged in an inverted manner, and the drain D1 of the first power chip 24 passes through the first conductive connection element 261 and the second patterned conductive layer 28 and electrically connected to the source S2 of the second power chip 25. According to this, the electrical conduction distance between the drain electrode D1 and the source electrode S2 can be shortened, and the electrical effect can be increased. On the other hand, the semiconductor package structure can also be applied to a half-bridge circuit.

Next, a method of manufacturing the semiconductor package structure according to the second embodiment of the present invention will be explained. In this embodiment, the manufacturing method of the semiconductor package structure includes steps S31 to S40. Since the manufacturing method of this embodiment is partially the same as the manufacturing method of the first embodiment, the description of the same steps will be omitted. In addition, in this embodiment, the element symbols of the first embodiment are used.

First, steps S31 to S34 are the same as steps S11 to S14 of the first embodiment, so they will not be repeated here.

Next, as shown in FIG. 3A, step S35 is to form a second conductive connection element 262 on the first patterned conductive layer 22 where the conductive adhesive layer 23 is not provided. As in the previous embodiment, the second conductive connection element 262, such as a conductive post, is made of gold It can be directly formed on the first patterned conductive layer 22 through an electroplating process. In addition to providing an electrical conduction path, it can also increase the support strength. In other embodiments, the second conductive connection element 262 may be pre-shaped and then fixed by conductive adhesive and electrically connected to the first patterned conductive layer 22 (not shown).

Next, as shown in FIG. 3B, step S36 forms a molding layer 27 on the carrier board 21 and covers the first patterned conductive layer 22, the conductive adhesive layer 23, the first power chip 24, and the second power chip 25与第二电动连接元件262. In addition, step S36 may further include grinding the top of the mold sealing layer 27 through a grinding process to expose the top T02 of the second conductive connection element 262.

Next, as shown in FIG. 3C, step S37 is to use a laser drilling technique on the mold layer 27 to respectively correspond to the drain electrode D1 of the first power chip 24 and the source electrode S2 of the second power chip 25 and Three openings 271, 272, 273 are formed at the position of the gate G2 to expose the drain D1 of the first power chip 24 and the source S2 and the gate G2 of the second power chip 25.

Next, as shown in FIG. 3D, step S38 is to form the first conductive connection element 261 on the openings 271, 272, 273 and the second patterned conductive layer 28 on the molding layer 27, and electrically connect to the exposed mold The first conductive connection element 261 and the second conductive connection element 262 of the sealing layer 27. In this embodiment, the first conductive connection element 261 and the second patterned conductive layer 28 can be formed at the same time, and exposure and development and etching processes can be performed using lithography etching technology with an additional photoresist layer (not shown in the figure). And perform a plating process to form the first conductive connection element 261 and the second patterned conductive layer 28.

Next, Step 39 and Step 40 are the same as Step S19 and Step S20 of the first embodiment, so they will not be repeated here.

The semiconductor package structure 20 of the present invention can be electrically connected to a circuit board 30 through conductive bumps 32 as shown in FIG. 4. The circuit board 30 may be a printed circuit board, a metal core circuit board or a glass circuit board.

In addition, as shown in FIG. 5, openings 274 and 275 may be formed on the protective layer 27a by laser drilling technology to expose a portion of the second patterned conductive layer 28, and an electronic element 33 may be transmitted through the conductive bumps 34 and electrically connected to the second patterned conductive Layer 28.

In summary, a semiconductor package structure and a manufacturing method thereof according to the present invention arrange the first power chip and the second power chip, which are, for example, transistor chips, in an inverse manner, which has the following characteristics:

(1) The first power chip and the second power chip are arranged in an inverse manner to shorten the distance of the electrical connection between the chips to increase the electrical performance and reduce the height of the packaging structure.

(2) The semiconductor process is used to replace the conventional reflow process to greatly improve the accuracy of the packaging structure.

(3) Abandon the lead-containing reflow process in the process, so it can meet the trend of environmental protection and the requirements of laws and regulations.

(4) One side of the power chip is fixed to the first patterned conductive layer using a thermally conductive adhesive layer, which can simplify the manufacturing process.

This invention meets the requirements of the invention patent, and the patent application is filed in accordance with the law. However, the above are only the preferred embodiments of the present invention, and thus cannot limit the scope of patent application in this case. Anyone who is familiar with the skills of this case and equivalent modifications or changes made in accordance with the spirit of the invention of this case should be included in the scope of the following patent applications.

20‧‧‧Semiconductor packaging structure

22‧‧‧The first patterned conductive layer

23‧‧‧ conductive adhesive layer

24‧‧‧ First power chip

25‧‧‧ Second power chip

261‧‧‧First conductive connecting element

262‧‧‧Second conductive connecting element

27‧‧‧mold seal layer

27a‧‧‧Protection layer

28‧‧‧Second patterned conductive layer

G1, G2 ‧‧‧ gate

S1, S2‧‧‧Source

D1, D2‧‧‧ji

Claims (13)

A semiconductor package structure includes: a first patterned conductive layer; a first power chip having a first front surface and a first back surface, and the first front surface is disposed toward the first patterned conductive layer, the The first front face of the first power chip has a first electrode layout, and the first back face has a second electrode layout; a second power chip, adjacent to the first power chip, has a second front face and A second back surface, which is disposed with the second back surface facing the first patterned conductive layer, the second front surface of the second power chip has a third electrode layout, and a fourth electrode on the second back surface Layout; a conductive adhesive layer, electrically connected between the first electrode layout of the first power chip and the first patterned conductive layer, and electrically connected to the fourth electrode layout of the second power chip Between the first patterned conductive layer; a second patterned conductive layer, opposite to the first patterned conductive layer, the first back surface of the first power chip and the second front surface of the second power chip Facing the second patterned conductive layer; a first conductive connection element electrically connected between the second electrode layout of the first power chip and the second patterned conductive layer, and electrically connected to the first Between the third electrode layout of the two power chips and the second patterned conductive layer; a second conductive connection element electrically connected between the first patterned conductive layer and the second patterned conductive layer; and A mold sealing layer covers the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip, the first conductive connection element and the second conductive connection element. The semiconductor package structure of claim 1, wherein the first electrode layout of the first power chip is the same as the third electrode layout of the second power chip, and the second electrode layout of the first power chip is the same as the first electrode chip The fourth electrode layout of the second power chip. The semiconductor package structure of claim 1, wherein the first power chip and the second The power chip is a transistor chip. The semiconductor package structure of claim 3, wherein the first electrode layout and the third electrode layout include a gate electrode and a source electrode, and the second electrode layout and the fourth electrode layout include a drain electrode, respectively. The semiconductor package structure of claim 4, wherein the drain electrode of the second electrode layout is electrically connected to the source electrode of the third electrode layout. The semiconductor packaging structure according to claim 1, wherein the material of the mold encapsulation layer is a mold compound, which is based on phenolic resin, epoxy resin or silicon resin. A method for manufacturing a semiconductor package structure includes: providing a carrier board; forming a first patterned conductive layer on a surface of the carrier board; providing a conductive adhesive layer on part of the first patterned conductive layer; providing a The first power chip is on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power chip is in contact with the conductive adhesive layer; a second power chip is disposed on the conductive adhesive layer, wherein A fourth electrode layout on a second back surface of the second power chip is in contact with the conductive adhesive layer; forming at least one conductive connection element on the first patterned conductive layer without the conductive adhesive layer, the first power A second electrode layout on a first back surface of a chip and/or a third electrode layout on a second front surface of the second power chip; forming a mold sealing layer on the carrier board and covering the first pattern Conductive layer, the conductive adhesive layer, the first power chip, the second power chip, and the conductive connection element; forming a second patterned conductive layer on the mold encapsulation layer, and electrically connected to the mold exposed The conductive connection element of the sealing layer; and removing the carrier board. The method for manufacturing a semiconductor package structure according to claim 7, wherein at least one drain of the first back surface of the first power chip is electrically connected to at least one source electrode of the second front surface of the second power chip. The manufacturing method of the semiconductor package structure according to claim 7 further includes: A protective layer is formed on the mold sealing layer to cover the second patterned conductive layer. A method for manufacturing a semiconductor package structure includes: providing a carrier board; forming a first patterned conductive layer on a surface of the carrier board; providing a conductive adhesive layer on part of the first patterned conductive layer; providing a The first power chip is on the conductive adhesive layer, wherein a first electrode layout of a first front surface of the first power chip is in contact with the conductive adhesive layer; a second power chip is disposed on the conductive adhesive layer, wherein A fourth electrode layout on a second back surface of the second power chip is in contact with the conductive adhesive layer; forming at least a second conductive connection element on the first patterned conductive layer without the conductive adhesive layer; forming a A mold sealing layer on the carrier board, and covering the first patterned conductive layer, the conductive adhesive layer, the first power chip, the second power chip and the second conductive connection element; on the mold sealing layer A plurality of openings are formed corresponding to a second electrode layout on a first back surface of the first power chip and a third electrode layout on a second front surface of the second power chip; a first conductive connection element is formed on these Opening; forming a second patterned conductive layer on the molding layer, and electrically connected to the first conductive connection element and the second conductive connection element exposed to the molding layer; and removing the carrier board. The method for manufacturing a semiconductor package structure according to claim 10, wherein at least one drain of the first back surface of the first power chip is electrically connected to at least one source electrode of the second front surface of the second power chip. The method for manufacturing a semiconductor package structure according to claim 10 further includes: forming a protective layer on the mold encapsulation layer to cover the second patterned conductive layer. The method for manufacturing a semiconductor package structure according to claim 10, wherein the first conductive connection element and the second patterned conductive layer are formed simultaneously in one process.

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